LNA SWITCH MODULE

Abstract

A switched LNA module comprising: a silicon-on-insulator wafer, SOI, comprising a silicon substrate and an active layer separated by a buried oxide layer, BOX, wherein said SOI substrate is a high-resistance SOI substrate, HR, comprising a silicon manipulation layer having a resistivity greater than 1 kΩ-cm; a switch comprising a plurality of SOI transistors; a low-noise amplifier, LNA, located in said SOI wafer and connected to an output of said switch, wherein said LNA comprises a bipolar transistor formed in a bulk region of said SOI wafer where said BOX layer is removed; and a thick metal layer for connection to the switch and the LNA. Figure for the abstract: Fig. 5

Description

Title of the invention: SWITCH-ON LNA MODULE technical field

[0001] The present invention relates to low noise amplifier (LNA) modules with switching, i.e. circuits comprising a switch with silicon-on-insulator (SOI) transistors and an LNA. CONTEXT

[0002] New telecommunications technologies require new and improved devices at the semiconductor level. The new standard, 5G-NR, can enable higher data rates (> 100 Mbit / s, max. 20 Gbit / s), greater density (more connected devices / km2) and lower latency (ideally from 10 to 1 ms).

[0003] For 5G, semiconductor technologies from the IILV group (e.g., GaAs) look promising, but have some drawbacks such as high power consumption, low quality factor passive components, low level of integration, difficult mass production and high costs.

[0004] In silicon-on-insulator (SOI) technology, circuits are formed in a silicon layer that is isolated from the substrate by an electrically insulating layer. This has the advantage of reducing parasitic capacitance, thus enabling a more desirable power-speed performance horizon. SOI structures can therefore be advantageous for high-frequency applications such as radio frequency (RF) communication circuits. SUMMARY

[0005] In accordance with a first aspect of the invention, a switchable LNA module is provided which comprises: - a silicon-on-insulator wafer, SOI, comprising a silicon substrate and an active layer, separated by a buried oxide layer, BOX, wherein said SOI substrate is a high-strength SOI substrate, HR, comprising a silicon handling layer having a resistivity greater than 1 kQ-cm; - a switch comprising a plurality of SOI transistors; - a low-noise amplifier, LNA, located in said SOI slice and connected to an output of said switch, wherein said LNA comprises a bipolar transistor formed in a massive region of said SOI slice where said BOX layer is removed; and a thick metallic layer for connection to the switch and the LNA.

[0006] In an embodiment of the first aspect, said bipolar transistor is a SiGe transistor.

[0007] In an embodiment of the first aspect, said silicon manipulation layer has a resistivity greater than 3 kQ-cm.

[0008] In an embodiment of the first aspect, said LNA switch module further comprises a plurality of passive components formed in or on said SOI slice on said BOX layer, wherein said passive components are formed from and / or are connected by the thick metallic layer and a second thick metallic layer that at least partially overlaps it.

[0009] In an embodiment of the first aspect, the or each thick metallic layer has a thickness in the range of 2 pm to 4 pm.

[0010] In an embodiment of the first aspect, said LNA comprises a cascode structure including said bipolar transistor which is a common emitter of said cascode structure.

[0011] In an embodiment of the first aspect, said LNA includes a second bipolar transistor which is a common base of said cascode structure.

[0012] In an embodiment of the first aspect, said LNA switch module further includes an SOI transistor, in which said cascode structure includes said SOI transistor which is a common gate of said cascode structure.

[0013] In an embodiment of the first aspect, said SOI transistor is a complementary metal-oxide-semiconductor (CMOS) transistor.

[0014] In an embodiment of the first aspect, said LNA switch module includes a first-stage amplification circuit and a second-stage amplification circuit, in which said first-stage amplification circuit includes said bipolar transistor and in which said second-stage amplification circuit includes a cascode structure.

[0015] In an embodiment of the first aspect, said cascode structure comprises a first SOI transistor which is a common source of said cascode structure and a second SOI transistor which is a common gate of said cascode structure.

[0016] In an embodiment of the first aspect, said cascode structure includes a second bipolar transistor in a massive region of said SOI slice, in which said second bipolar transistor is a common emitter of said cascode structure, and an SOI transistor that is a common gate of said cascode structure.

[0017] In an embodiment of the first aspect, said first-stage amplification circuit includes a second cascode structure comprising said bipolar transistor which is a common emitter of said second cascode structure.

[0018] In an embodiment of the first aspect, said second cascode structure includes a second bipolar transistor located in a massive region of said SOI slice, in which said second bipolar transistor is a common base of said cascode structure.

[0019] In an embodiment of the first aspect, said second cascode structure includes an SOI transistor which is a common gate of said cascode structure.

[0020] According to a second aspect of the invention, a telecommunications device is provided comprising a switchable LNA module according to any one of the embodiments of the first aspect, in which the switch of the switchable LNA module is arranged in said device to switch from a receiver mode to a transmitter mode of said device.

[0021] Preferred embodiments of the invention are described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Fig. 1 represents a diagram of part of a telecommunications system, such as a user equipment (UE) or other telecommunications device, according to one embodiment;

[0023] [Fig.2] represents a diagram of a series / parallel series bidirectional unipolar switch (SPDT) comprising SOI transistors;

[0024] Fig. 3 represents a diagram of a switch;

[0025] Fig. 4 represents the small and large signal traces of a switch;

[0026] Figure 5 shows a schematic diagram of a switchable LNA module in a mode implementation comprising a two-stage low-noise amplifier (LNA), where the first stage is a SiGe transistor while the second stage is a cascode structure comprising SiGe and SOI transistors;

[0027] Fig. 6 represents the simulated small-signal plots of the embodiment;

[0028] Fig. 7 represents the simulated large-signal plots of the embodiment;

[0029] Figure 8 shows a schematic diagram of a switchable LNA module according to another embodiment comprising a single-stage LNA comprising a cascode structure comprising two SiGe transistors in a massive region of an SOI wafer;

[0030] Fig. 9 represents a schematic of a switched LNA module according to an embodiment comprising a single-stage LNA comprising a cascode structure including a SiGe transistor and an SOI transistor;

[0031] Fig. 10 represents a schematic of a switched LNA module according to another embodiment comprising a two-stage LNA including a SiGe transistor in the first stage and a cascode structure including two SOI transistors in the second stage;

[0032] Figure 11 shows a schematic cross-section of part of a switchable LNA module according to one embodiment; and

[0033] Fig. 12 represents a diagram of part of an LNA illustrating the SOI slice and the back stack comprising metallic layers. DETAILED DESCRIPTION

[0034] Figure 1 represents part of a telecommunications system 2 comprising an antenna 4 for transmitting and receiving electromagnetic signals, a switch 6 connected to the antenna for switching between transmit (Tx) and receive (Rx) modes, and a low-noise amplifier (LNA) 8 for amplifying the signals received from the antenna 4. The system further comprises a band shifter 10 for shifting the signals up or down, wherein the band shifter includes a frequency synthesizer 12. The system 2 may be part of a node such as a base node in a 5G telecommunications network, or of a user device (UE) such as a mobile phone.

[0035] Figure 2 shows a circuit diagram of a switch 6 according to one embodiment, which may be the switch 6 of the system illustrated in Figure 1. The same reference numerals are used for similar or equivalent features in different figures for ease of understanding and are not intended to limit the embodiments shown. The switch 6 is connected to the antenna 4 and to a transmit path 14 for transmitting signals with the antenna 4 and to a receive path 16 for receiving signals with the antenna 4. The switch 6 comprises a plurality of SOI transistors (for example, CMOS transistors formed on the SOI wafer). The switch comprises transistors stacked in series / parallel. The SOI wafer may include a high-resistance (HR) SOI substrate. For example, the SOI wafer may include a silicon manipulation layer having a resistivity greater than 3 kΩ-cm.

[0036] Figure 3 shows a circuit diagram of a switch 6 configured to switch an antenna 4 between a transmit path 14 and a receive path 16 for operation in the respective TX and RX modes. The switch 6 is a semiconductor switch, operated by applying a voltage across different transistors within the switch. The switch 6 may be the switch as illustrated in Figure 1 and / or Figure 2.

[0037] Figure 4 shows the small- and large-signal plots of an SPDT switch according to an embodiment implemented using a SOI, such as the switch illustrated in Figure 2 or Figure 3. From the plots, the switch exhibits approximately 0.6 dB of insertion loss at 28 GHz, and a soft break around 38 dBm.

[0038] Figure 5 shows a schematic of an embodiment comprising an SOI switch 6 and an LNA 8. The switch 6 is configured to connect an antenna line 18 to the LNA 8, which is configured to amplify the signal and output the amplified signal on an output line 20. The switch 6 and the LNA 8 are located on the same SOI substrate. The SOI wafer comprises a silicon substrate (also called the manipulation slice) and an active silicon layer (also called the device layer) separated by a buried oxide layer (BOX). Switch 6 includes a plurality of switching transistors formed in the active silicon layer above the BOX layer. Switch 6 also includes a plurality of passive components (e.g., resistors) connected to the transistors, which are also formed above the BOX layer to benefit from the improved electrical isolation provided by the SOL slice. One of the outputs of switch 6 is directly connected to LNA 8. LNA 8 includes a first amplification stage comprising a SiGe 24 transistor formed in a bulk region of the SOI slice, in which the BOX layer has been removed from the bulk region and replaced with silicon.In the figures, a dashed rectangle is used to illustrate a device formed in a massive region. Local removal of the BOX layer can improve heat conduction from the SiGe transistor 24 since it is directly connected to the underlying silicon substrate. The second amplification stage of the LNA 8 comprises a cascode structure with a first transistor 28, which is the common emitter of said cascode structure, and a second transistor 30, which is the common gate of said cascode structure. The first transistor 28 is another SiGe transistor formed in a second massive region of the SOL wafer. The SOI transistors 24 and 28 can improve the noise figure of the LNA 8, compared to a single SOI transistor, particularly in the millimeter wave frequency range. The second transistor 30 of the cascode structure is an SOI transistor (e.g., an NMOS transistor) located above the BOX layer of the SOI wafer.The SOI transistor can improve the linearity of the LNA 8. The LNA8 also includes a plurality of passive components (e.g., capacitors and inductors) that can also benefit from the SOI slice. The combination of the SOI SPDT switch and the SOI LNA with massive SiGe transistors can provide an improved receiver structure for a telecommunications system, such as for a UE in a 5G network.

[0039] Figure 6 shows small-signal plots from simulations of the switch and the LNA system illustrated in Figure 5. From the plots, there is sufficient gain covering the frequency range of interest from approximately 24 GHz to 32 GHz and an excellent noise figure (nf) of around 2.2 dB at 28 GHz.

[0040] Figure 7 shows the large-signal plots from simulations of the switch and the LNA system illustrated in Figure 5. The large-signal simulation shows a 1 dB compression occurring at -10 dBm input power. The large-signal behavior meets the requirements for a 5G system.

[0041] Figure 8 shows a diagram of another system according to an embodiment comprising a switch 6 and an LNA 8. The system is similar to that of the [Fig. 5], but the LNA 8 comprises a single amplification stage instead of two. The LNA 8 includes a cascode structure comprising a first transistor 28, which is the common emitter, and a second transistor 30, which is the common base of said cascode structure. Both transistors 28 and 30 are SiGe transistors formed in the massive region(s) of the SOL slice. The SiGe transistors can reduce the noise of the LNA 8 compared to SOL transistors.

[0042] Figure 9 shows a schematic diagram of another system according to an embodiment comprising a switch 6 and an LNA 8. The system is similar to that of Figure 8, but instead of having two SiGe transistors in a cascode structure, the LNA 8 comprises a first transistor 28, which is a SiGe transistor in a massive region, and a second transistor 30, which is an SOI transistor in what is referred to here as a hybrid cascode structure. The SiGe transistor can reduce noise, while the SOI transistor can improve linearity.

[0043] Figure 10 shows a schematic diagram of another system according to an embodiment comprising a switch 6 and an LNA 8. The system is similar to that of Figure 5, but instead of having a hybrid cascode structure in the second amplification stage, the second amplification stage comprises a cascode structure with first and second transistors 28, 32 which are SOL transistors

[0044] Figure 11 shows a schematic cross-section of a portion of a switched LNA module, such as a portion of the switch or the LNA, like LNA 8 of Figure 5, 8, 9, or 10. The module comprises a silicon wafer 22 including a silicon substrate 38, a BOX layer 40, and an active silicon layer 42. The wafer 22 also includes a silicon-filled bulk region 44 where the BOX layer has been locally removed. The LNA includes a SiGe transistor 46 in the active silicon layer 42 within the bulk region 44.

[0045] Figure 12 shows a schematic of part of a switch according to one embodiment. In particular, the metal layers 48 (M1 to M4, MI, and MJ) on the SOI substrate, which connect to the SOI transistors 50 above the BOX layer 40, are illustrated. Passive components, such as inductor coils, can be formed from or connected to the thicker upper metal layers MI and MJ. The low resistivity of the thick metal layers MI and MJ can improve the performance of the passive components and reduce LNA noise. The thick metal layers MI and MJ can be about 3 µm thick. The metal layers 51 can generally be formed in the back end of the line (BEOL) of a CMOS process. The "normal" metal layers (M1 to M4) are about 0.35 µm thick. Silicon substrate 38 is an HR substrate with a resistivity greater than approximately 3 kQ-cm.

[0046] In general, the embodiments disclosed herein provide an LNA module to A switch comprising a silicon-on-insulator (SOI) wafer consisting of a silicon substrate and an active layer, separated by a buried oxide layer (BOX), a switch comprising a plurality of SOI transistors (which are formed in the SOI wafer above the BOX layer, for example, by CMOS), and a low-noise amplifier (LNA) located in said SOI wafer and connected to an output of said switch, wherein said LNA comprises a bipolar transistor (for example, a SiGe transistor) formed in a bulk region of said SOI wafer where said BOX layer is removed. Generally, the switch is a series / parallel unipolar bidirectional switch (SPDT). The SPDT may be formed entirely in / on the SOI wafer in the active layer above the BOX layer. The SOI wafer comprises a high-resistance (HR) SOI substrate, including a silicon manipulation layer having a resistivity greater than 1 kΩ-cm.The LNA switch module further includes a thick metallic layer (e.g. > 2 µm thick) for connection to the switch and the LNA.

[0047] The silicon manipulation layer may have a resistivity greater than 3 kQ-cm. For example, the silicon manipulation layer can have a thickness in the range of 500 µm to 1000 µm. The HR SOI substrate can reduce parasitic capacitances. The LNA can further include a plurality of passive components (e.g., inductors, resistors, and capacitors) formed on said SOI substrate above said BOX layer. The BOX layer can, for example, have a thickness in the range of 2 µm to 4 µm. The active silicon layer is usually less than 1 µm thick, for example, about 0.1 µm or 0.2 µm. Devices located in the active silicon layer above the BOX layer, such as transistors, are usually separated by STIs.

[0048] Passive components can be formed from and / or connected by a thick metal layer (for example, the top metal of a CMOS back stack) or by two thick metal layers that at least partially overlap. The thick metal layer(s) generally comprise copper. The thick metal layers can be thicker than 1 µm. For example, the thick metal layers can be in the range of 2 µm to 4 µm, for example, about 3 µm. A greater thickness can reduce resistance and improve the performance of at least some of the passive components. For example, the inductor coils of the switchable LNA module can be formed by one or more coil turns in the thick metal layer(s).Typically, a plurality of metal layers are located on the SOI substrate, in which the thickest metal layer(s) are located on top (furthest from the active silicon layer). Metal 1 is the first metal layer located closest to the active silicon and can be directly connected to it. Bipolar transistor. The first metal layer can be less than 1 µm thick, for example, about 0.3 µm thick, which is significantly thinner than the thicker metal layer(s). The plurality of metal layers can be separated by interdielectric layers (for example, silicon oxide layers) and electrically connected by vias.

[0049] The LNA may include a cascode structure (also called a cascode topology) comprising said bipolar transistor, which is a common emitter of said cascode structure. The common base of the cascode structure may be a second bipolar transistor (for example, a SiGe transistor) in a bulk region of the SOI substrate or a "normal" SOI transistor (for example, a CMOS transistor) formed in the active silicon layer above the BOX layer of the SOL substrate

[0050] The LNA may comprise two amplification stages, for example, a first-stage amplification circuit and a second-stage amplification circuit, wherein said first-stage amplification circuit comprises said bipolar transistor and wherein said second-stage amplification circuit comprises a cascode structure. The cascode structure may comprise a first SOI transistor that is a common source of said cascode structure and a second SOI transistor that is a common gate of said cascode structure. In this embodiment, the second amplification stage may comprise only SOI transistors (for example, CMOS transistors), which may improve the linearity of the LNA.In another embodiment, the cascode structure may include a second bipolar transistor in a solid-state region of the SOI substrate, wherein the second bipolar transistor is a common emitter of the cascode structure, and wherein the cascode structure includes an SOI transistor that is a common gate of the cascode structure. That is, the second amplification stage comprises a hybrid cascode structure. The first amplification stage typically includes a single common emitter (no cascode structure), which is the bipolar transistor in the solid-state region. Alternatively, the first-stage amplifier circuit may include a second cascode structure comprising the bipolar transistor that is a common emitter of the second cascode structure.The second cascode structure may include a second bipolar transistor located in a bulk region of the SOI substrate, wherein the second bipolar transistor is a common base of the cascode structure. That is, both transistors of the cascode structure in the first amplification stage are bipolar transistors (e.g., SiGe transistors) formed in a bulk region of the SOI substrate in this embodiment. In another embodiment, the second cascode structure includes an SOI transistor that is a common gate of the cascode structure (to form a hybrid cascode structure with the transistor). bipolar).

[0051] Other embodiments provide user equipment (UE), such as a mobile phone, for telecommunications comprising a switch according to any of the embodiments detailed herein, wherein the switch is arranged in the UE to switch between a receive mode and a transmit mode of the UE. For example, the switch is connected to an antenna that is arranged to receive and transmit electromagnetic signals. In receive mode (RX), the switch connects the antenna to the LNA of the LNA-to-switch module so that the received signals are amplified by the LNA.

[0052] Although specific embodiments of the invention have been described above, it will be obvious to a person skilled in the art that modifications can be made to the invention as described without departing from the scope of the claims set forth below. Each feature disclosed or illustrated in this specification can be incorporated into the invention, either alone or in any suitable combination with any other feature disclosed or illustrated herein.

Claims

Demands

1. A switched LNA module comprising: - a silicon-on-insulator wafer (22) comprising a silicon substrate (38) and an active layer (42) separated by a buried oxide layer (40), wherein said silicon substrate is a high-resistance silicon substrate comprising a silicon handling layer having a resistivity greater than 1 kQ-cm; - a switch (6) comprising a plurality of SOI transistors; - a low-noise amplifier (8) located in said silicon-on-insulator wafer (22) and connected to an output of said switch (6), wherein said low-noise amplifier (8) comprises a cascode structure comprising a bipolar transistor (46) which is a common emitter of said cascode structure; said bipolar transistor (46) being formed in a bulk region (44) of said silicon-on-insulator wafer (22) where said buried oxide layer is removed;and a thick metallic layer (MI, MJ) for connection to the switch (6) and the low-noise amplifier (8).;

2. Switched LNA module according to claim 1, wherein said bipolar transistor (46) is a SiGe transistor.

3. Switchable LNA module according to claim 1 or 2, wherein said silicon handling layer has a resistivity greater than 3 kQ-cm.

4. Switchable LNA module according to any one of the preceding claims, further comprising a plurality of passive components formed in or on said silicon-on-insulator wafer (22) on said buried oxide layer (40), wherein said passive components are formed from and / or are connected by the thick metal layer and a second thick metal layer (MI, MJ) that at least partially overlaps it.

5. Switchable LNA module according to any one of the preceding claims, wherein the or each thick metallic layer (MI, MJ) has a thickness in the range of 2 pm to 4 pm.

6. Switchable LNA module according to claim 1, wherein said low noise amplifier (8) comprises a second bipolar transistor (30) which is a common base of said cascode structure.

7. Switchable LNA module according to claim 1, comprising in in addition to an SOI transistor (28, 32), in which said cascode structure comprises said SOI transistor which is a common gate of said cascode structure.

8. Switched LNA module according to claim 7, wherein said SOI transistor is a complementary metal-oxide-semiconductor (CMOS) transistor.

9. Switchable LNA module according to any one of claims 1 to 5, and comprising a first-stage amplification circuit and a second-stage amplification circuit, wherein said first-stage amplification circuit comprises said bipolar transistor and wherein said second-stage amplification circuit comprises a second cascode structure.

10. Switched LNA module according to claim 9, wherein said second cascode structure comprises a first SOI transistor which is a common source of said cascode structure and a second SOI transistor which is a common gate of said second cascode structure.

11. Switched LNA module according to claim 9, wherein said second cascode structure comprises a second bipolar transistor in a bulk region (44) of said silicon-on-insulator wafer (22), wherein said second bipolar transistor is a common emitter of said second cascode structure, and an SOI transistor which is a common gate of said second cascode structure.

12. Telecommunications apparatus comprising a switchable LNA module according to any one of the preceding claims, wherein the switch of the switchable LNA module is arranged in said apparatus to switch from a receive mode to a transmit mode of said apparatus.

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