Amplification circuit

Abstract

To provide an amplifier circuit capable of reducing influences of an error caused by electric charges generated at turn-off of switches and electric charges for parasitic capacitance as much as possible when using such a configuration that the switches and resistive elements are combined with an amplifier.SOLUTION: A first switched register part 9 is configured by connecting a first switch 5 and a first resistive element 6 in series, and one end of the first switched register part 9 is connected with an input terminal of an amplifier 2. A second resistive element 7 is connected between the other end of the first switched register part 9 and an output terminal of the amplifier 2. A second switch 8 is connected between a common connection point of the first switched register part 9 and the second resistive element 7 and a reset potential point. A control circuit turns ON the first switch 5 and the second switch 8 exclusively.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit that combines an amplifier with a switched resistor unit that has a switch and a resistance element. [Background technology]

[0002] Fig. 16, which corresponds to Fig. 2 of Patent Document 1, discloses a stacked switch resistor element that realizes a high-resistance resistor in an integrated circuit. This stacked switch resistor element includes multiple segments connected in series. Each segment includes a resistor with an inherent parasitic capacitance and a switch connected in series with the resistor. The switch is configured to connect and disconnect the resistor from the multiple segments in response to a predetermined clock signal.

[0003] Figure 17, which corresponds to Figure 1 of Patent Document 2, discloses an amplifier device including an amplifier having an inverting terminal and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage applied to the first capacitor, a second capacitor connected to the inverting terminal, an output terminal of the amplifier, and a duty-cycle resistor. A first resistor is connected in parallel to the second capacitor. The duty-cycle resistor is configured to connect the first resistor to the inverting terminal and disconnect the first resistor from the reset voltage node during a first time interval included in a period during which the resistor completes an on-off cycle, and to connect the first resistor to the reset voltage node and disconnect the first resistor from the inverting terminal during a second time interval included in the period. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,644,675 [Patent Document 2] U.S. Patent Publication No. 20220123700 Summary of the Invention [Problem to be solved by the invention]

[0005] In the above configuration, MOSFETs and the like are generally used as switches for connecting and disconnecting each element. As shown in Figure 18, when a MOSFET is turned on, a charge is stored directly below the gate terminal. When the MOSFET is turned off, the charge stored in the gate is injected into the source and drain terminals. This injected charge appears as an error Δqi. This phenomenon is called charge injection. Hereinafter, charge injection may be simply referred to as injection.

[0006] If the configuration of Patent Document 1 is implemented between the input and output terminals of an amplifier, the presence of many segments may result in a longer time for the input voltage bias to settle on the output side. Furthermore, because all switches are turned on and off simultaneously, the effect of injection errors becomes significant before and after that timing. For example, when viewed from the node to the right of switch 208B, if switch 208B, which is located in the subsequent stage, turns off later than switch 208A, which is located in the preceding stage, the error Δqi generated in switch 208A will be perceived as an error. However, if switch 208B turns off earlier, the error Δqi will not be perceived as an error from the node to the right of switch 208B.

[0007] Furthermore, in the configuration of Patent Document 2, when the switch 111 is turned off, the error Δqi appears directly at the inverting input terminal of the amplifier 109. Furthermore, since the resistance element also has parasitic capacitance, the charge stored in the parasitic capacitance may also appear as an error.

[0008] The present invention has been made in view of the above circumstances, and its purpose is to provide an amplifier circuit that can minimize the influence of charges generated when a switch is turned off and charges due to parasitic capacitance, which cause errors when a configuration combining a switch and a resistance element is used in an amplifier. [Means for solving the problem]

[0009] According to the amplifier circuit of claim 1, the first switched resistor section is configured by connecting a first resistor element, which is made up of one or more resistor elements, and a first switch in series, one end of which is connected to the input terminal of the amplifier. The second resistor section is connected between the other end of the first switched resistor section and the output terminal of the amplifier, and the second switch is connected between the common connection point of the first switched resistor section and the second resistor element and the reset potential point. The control circuit exclusively turns on the first switch and the second switch.

[0010] Because the first switch and the second switch are turned on exclusively, the effects of errors due to their respective charge injections are not superimposed. Because the first resistor element and the first switch are connected in series, the input terminal of the amplifier is directly affected by errors due to the parasitic capacitance of either the first resistor element or the first switch, but the effect of errors from the other element is mitigated. As a result, the effects of errors due to the parasitic capacitance of each element can be reduced overall. The amplifier circuit of claim 1 further includes a third switch (21) connected in series with the first switched resistor section and the second resistor section, or in series within the first switched resistor section or the second resistor section, and arranged closer to the output terminal of the amplifier than the first switch. The control circuit turns on / off the third switch with a delay relative to the on / off timing of the first switch, and delays the on period to a range that overlaps with part of the on period of the first switch. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing the configuration of an amplifier circuit in a first embodiment; [Figure 2] Timing chart showing the control signals for each switch [Figure 3] FIG. 10 is a diagram showing the configuration of an amplifier circuit in a second embodiment. [Figure 4] FIG. 10 is a diagram showing the configuration of an amplifier circuit in a third embodiment. [Figure 5] FIG. 10 is a diagram showing the configuration of an amplifier circuit in a fourth embodiment. [Figure 6] Timing chart showing the control signals for each switch [Figure 7] Diagram (part 1) showing the wiring that is energized when each switch is turned ON for each phase of the timing chart shown in Figure 6 [Figure 8]Diagram showing the wiring that is energized when each switch is turned ON (part 2) [Figure 9] Diagram showing the wiring that is energized when each switch is turned ON (part 3) [Figure 10] Diagram showing the wiring that is energized when each switch is turned ON (part 4) [Figure 11] FIG. 13 is a diagram showing the configuration of an amplifier circuit in a fifth embodiment. [Figure 12] FIG. 13 is a diagram showing the configuration of an amplifier circuit in a sixth embodiment. [Figure 13] FIG. 13 is a diagram showing the configuration of an amplifier circuit in a seventh embodiment. [Figure 14] Timing chart showing the control signals for each switch [Figure 15] 13 is a timing chart showing control signals for each switch in the eighth embodiment. [Figure 16] Figure equivalent to Figure 2 in Patent Document 1 [Figure 17] Figure equivalent to Figure 1 in Patent Document 2 [Figure 18] Diagram explaining charge injection DETAILED DESCRIPTION OF THE INVENTION

[0012] (First embodiment) As shown in FIG. 1, the amplifier circuit 1 of this embodiment includes a differential amplifier 2, and the inverting and non-inverting input terminals of the differential amplifier 2 are connected to an input voltage V inp , V inm is applied via capacitors 3a and 3b. Note that the configurations of the positive and negative sides of the differential amplifier 2 are symmetrical, and the symbols "a" and "b" are added to the respective reference numerals in the drawings. In the following, when it is not necessary to specify the configurations of the positive and negative sides, the symbols will be explained without adding "a" and "b."

[0013] A capacitor 4 corresponding to a first capacitance element is connected between the input terminal and output terminal of the differential amplifier 2. A series circuit of a first switch 5, a first resistance element 6, and a second resistance element 7 is connected in parallel to the capacitor 4. A second switch 8 is connected between the common connection point of the first resistance element 6 and the second resistance element 7 and ground. Ground is a reset potential point, and the ground potential corresponds to the reset potential. The first switch 5 and the first resistance element 6 constitute a first switched resistor section 9. The second resistance element 7 corresponds to a second resistance element section. The switches 5 and 8 are configured using, for example, N-channel MOSFETs.

[0014] The first switch 5 and the second switch 8 are controlled by control signals Φ1 and Φ2, respectively, output by a control circuit (not shown), and the control signals Φ1 and Φ2 are turned OFF at low level and ON at high level. In the figure, the parasitic capacitance C of the first resistor element 6a is shown by a dashed line, and the charge accumulated in this parasitic capacitance C is denoted as Δqr. Furthermore, the charge due to charge injection that occurs when the first switch 5a is turned OFF is denoted as Δqi. These charges Δqr and Δqi are referred to as "errors."

[0015] 2, the periods during which the control signals Φ1 and Φ2 are at high level are set so as not to overlap, and the first switch 5 and the second switch 8 are controlled to be exclusively ON. The amplifier circuit 1 is intended to be used when configuring, for example, a ΔΣ A / D converter.

[0016] Next, the operation of this embodiment will be described. When the control signal Φ2 goes high and the second switch 8 turns ON, the potential at the common connection point of the resistor elements 6 and 7 goes to the ground potential, which is the common mode voltage. When the control signal Φ1 goes high and the first switch 5 turns ON, charge injection occurs in the first switch 5. After that, when the first switch 5 turns OFF, the error Δqi appears directly at the input terminal of the differential amplifier 2, but the error Δqr does not appear.

[0017] As described above, according to this embodiment, the first switched resistor unit 9 is configured by connecting the first switch 5 and the first resistor element 6 in series, and one end of the first switched resistor unit 9 is connected to the input terminal of the amplifier 2. The second resistor element 7 is connected between the other end of the first switched resistor unit 9 and the output terminal of the amplifier 2, and the second switch 8 is connected between the common connection point of the first switched resistor unit 9 and the second resistor element 7 and the reset potential point. The control circuit turns on the first switch 5 and the second switch 8 exclusively.

[0018] Because the first switch 5 and the second switch 8 are turned ON exclusively, the effects of errors due to their respective charge injections are not superimposed. By connecting the first switch 5 and the first resistance element 7 in series, the input terminal of the amplifier 2 is directly affected by the error Δqi due to the charge injection of the first switch 5, but is not affected by the error Δqr of the other switch. As a result, the effects of errors due to the parasitic capacitance of each element can be reduced overall.

[0019] (Second embodiment) Hereinafter, the same parts as those in the first embodiment will be assigned the same reference numerals and their explanation will be omitted, and only the different parts will be explained. As shown in Fig. 3, an amplifier circuit 11 of the second embodiment has a configuration in which the connection order of the first switch 5 and the first resistor element 6 of the first switched resistor unit 9 in the amplifier circuit 1 is reversed. These constitute a first switched resistor unit 12. Because the first resistor element 6 is connected to the input terminal of the differential amplifier 2, an error Δqr appears at the input terminal, but the error Δqi is mitigated by the presence of the first resistor element 6.

[0020] (Third embodiment) 4, the amplifier circuit 13 of the third embodiment includes a first switched resistor section 14 and a second resistor section 15. The first switched resistor section 14 is configured with a series circuit of a resistor element 16, a first switch 5, and a resistor element 17, and the second switched resistor section 15 is configured with a series circuit of a second switch 8, a resistor element 18, and a resistor element 19. The resistor elements 16 and 17 correspond to the first resistor element, and the resistor elements 18 and 19 correspond to the second resistor section.

[0021] If the resistance value of the resistor elements 6 and 7 is R, the resistance value of the resistor elements 16 to 19 is set to R / 2. Since the parasitic capacitance value of a resistor element is proportional to the resistance value, the error due to the parasitic capacitance of the resistor elements 16 to 19 is Δqr / 2. According to the amplifier circuit 13, as in the second embodiment, the presence of the first resistor element 6 alleviates the error Δqi, and the error appearing at the input terminal of the differential amplifier 2 becomes smaller.

[0022] (Fourth embodiment) As shown in Fig. 5, the amplifier circuit 20 of the fourth embodiment has a configuration in which a third switch 21 is added between the resistor element 7 and the output terminal of the differential amplifier 2 in the amplifier circuit 1 of the first embodiment. The third switch 21 is controlled by a control signal Φ3. As shown in Fig. 6, the period in which the control signal Φ3 is at a high level does not overlap with the control signal Φ2 and is slightly delayed with respect to the control signal Φ1. The degree to which the control signal Φ3 is delayed with respect to the control signal Φ1 is limited to the extent that the ON periods of both signals overlap.

[0023] 7 to 10 correspond to each phase of the timing chart shown in FIG. 6, and the thick lines indicate the wiring that is energized when switches 5, 8, and 21 are turned ON. When switches 5 are turned OFF first as shown in FIG. 8, from a state in which switches 5 and 21 are both ON as shown in FIG. 7, an error Δqi appears at the input terminal of differential amplifier 2. Next, as shown in FIG. 9, switch 21 is turned OFF, causing an error Δqi, but because switch 5 is OFF, this does not affect the input terminal of differential amplifier 2. After that, switch 8 is turned ON as shown in FIG. 10, and the common connection point of resistor elements 6 and 8 becomes ground potential.

[0024] (Fifth embodiment) 11, an amplifier circuit 22 of the fifth embodiment has a configuration in which a switch 21 is connected between the switch 5 and the resistance element 7 in the amplifier circuit 11 of the second embodiment. The effect of the fifth embodiment is the effect of the second embodiment added to the effect of the fourth embodiment.

[0025] (Sixth embodiment) 12, an amplifier circuit 23 of the sixth embodiment has a configuration in which a switch 21 is connected between the resistance elements 18 and 19 in the amplifier circuit 13 of the third embodiment. The effect of the sixth embodiment is the effect of the fourth embodiment added to the effect of the third embodiment.

[0026] (Seventh embodiment) 13, the amplifier circuit 24 of the seventh embodiment has a configuration in which chopping switches 25 and 25B are connected to the front stage of the capacitor 3 in the amplifier circuit 20 of the fourth embodiment, and chopping switches 26 and 26B are also connected to the output terminal of the differential amplifier 2. The chopping switches 25 and 25B are controlled by control signals Φ4 and Φ4B, respectively, and the chopping switches 26 and 26B are controlled by control signals Φ5 and Φ5B, respectively.

[0027] As shown in Figure 14, if the switching frequency of the control signal Φ1 is Fs, then the switching frequencies of the control signals Φ4 and Φ4B and Φ5 and Φ5B are Fs / 2. Furthermore, the phases of the control signals Φ5 and Φ5B are delayed by 90° relative to the control signals Φ4 and Φ4B. If the frequency of the control signal Φ1 is sin(Fst), then the frequency of the control signals Φ4 and Φ4B is expressed as cos(Fs / 2)t, and the frequency of the control signals Φ5 and Φ5B is expressed as sin(Fs / 2)t.

[0028] The chopping switch 25 or 25B is turned on for a period exceeding the length of the period, including the period during which the first switch 5 is turned on. By setting the control signals Φ4 and Φ4B not to switch at the timing when the control signals Φ1 to Φ3 switch, errors occurring in charge conservation due to the ON / OFF of the chopping switches 25 and 25B are reduced.

[0029] (Eighth embodiment) In the eighth embodiment, assuming that the timing chart shown in FIG. 6 is an operation phase for the amplifier circuit 20 of the fourth embodiment, a reset phase is provided before the operation phase starts, as shown in FIG. 15. In the reset phase, the control signals Φ1 and Φ3 are set to high level, and the control signal Φ2 is set to low level. This allows the initial state of the amplifier circuit 20 to be determined.

[0030] (Other embodiments) The first to third switches are not limited to N-channel MOSFETs, and may be configured using other semiconductor elements. The first resistive element and the second resistive element section may be configured with three or more resistive elements. Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0031] In the drawing, 1 indicates an amplifier circuit, 2 indicates a differential amplifier, 3 and 4 indicate capacitors, 5 indicates a first switch, 6 indicates a first resistor element, 7 indicates a second resistor element, 8 indicates a second switch, and 9 indicates a first switched resistor unit.

Claims

1. Amplifier (2), a first switched resistor section (9, 14) configured by connecting in series a first resistor element (6, 16, 17) consisting of one or more resistor elements and a first switch (5), one end of which is connected to an input terminal of the amplifier; a second resistor element section (7, 18, 19) connected between the other end of the first switched resistor section and the output terminal of the amplifier and consisting of one or more resistor elements; a second switch (8) connected between a common connection point of the first switched resistor section and the second resistive element section and a reset potential point; a control circuit that exclusively turns on the first switch and the second switch; a third switch (21) connected in series with the first switched resistor unit and the second resistor unit, or in series within the first switched resistor unit or the second resistor unit, and arranged closer to the output terminal of the amplifier than the first switch, The control circuit is an amplifier circuit that delays the ON / OFF timing of the third switch from the ON / OFF timing of the first switch and delays the ON period to a range that overlaps with part of the ON period of the first switch.

2. A reset period is provided before the circuit operation begins.

2. The amplifier circuit according to claim 1, wherein the control circuit turns on the first switch and the third switch and turns off the second switch during the reset period.

3. 3. The amplifier circuit according to claim 1, further comprising a first capacitance element (4) connected between the input terminal and the output terminal of the amplifier.

4. An input side chopping switch (25); a second capacitance element (3) connected between the input side chopping switch and the input terminal of the amplifier; an output-side chopping switch (26) connected to the output terminal of the amplifier; When the control circuit drives the first switch at a predetermined phase timing of a frequency Fs, turning on the input side chopping switch at a frequency of Fs / 2 for a period including an ON period of the first switch; 4. The amplifier circuit according to claim 3, wherein the output side chopping switch is turned on at a frequency of Fs / 2.

Images