Semiconductor device and integrated circuit

Abstract

The present invention provides a semiconductor device capable of reducing the offset drift of an amplifier caused by the NBTI of a p-channel MOS transistor. The semiconductor device comprises: an n-channel MOS transistor formed on a major surface of a substrate using silicon carbide, and a p-channel MOS transistor formed on a major surface of a substrate using silicon carbide.Furthermore, both the n-channel MOS transistor and the p-channel MOS transistor have a gate electrode on the main surface of the substrate via a gate oxide film, a hanging bond at an interface between the substrate and the gate oxide film is passivated by an added element, and the concentration of the element with which the hanging bond is passivated in the p-channel MOS transistor is lower than that with which the hanging bond is passivated in the n-channel MOS transistor.

Description

BACKGROUND

[0001] The present invention relates to a semiconductor device with a substrate made of SiC (silicon carbide) and an integrated circuit provided with the semiconductor device.

[0002] General-purpose devices that use silicon cannot generally be used in products that operate under high-temperature conditions, and even if such products are equipped with a cooling device to solve this problem, a reduction in the size, weight, or cost of the products cannot be readily achieved.

[0003] However, a semiconductor device (see, for example, Japanese patent application no. 2019-12780) with a substrate made of SiC (silicon carbide) is known as a device that can be operated at high temperatures.

[0004] Furthermore, nuclear instrumentation devices, particularly those including pressure transmitters, must exhibit improved radiation resistance. The use of a SiC amplifier for nuclear instrumentation devices contributes to a further improvement in the safety of a nuclear power plant, as it eliminates the need for a shielding wall. SUMMARY

[0005] The SiC amplifier consists of a multitude of n-channel and p-channel MOS transistors. These n-channel and p-channel MOS transistors have a structure in which a thin gate oxide film is formed on a SiC epitaxic layer and a drain current flows through a SiC / SiO2 interface.

[0006] This SiC / SiO2 interface, for example, is annealed with NO (“Nitrogen Oxide” - nitrogen oxide) to reduce interface defects.

[0007] However, annealing with NO can degrade the NBTI (Negative Bias Temperature Instability) properties of a p-channel MOS transistor, as nitrogen induces defects on the valence band side. This deterioration of the NBTI properties further increases the offset drift of the SiC amplifier.

[0008] The inventors of the present invention, however, have confirmed that a p-channel MOS transistor that is not subjected to NO-based annealing hardly works.

[0009] Therefore, it is impossible to manufacture products that use a SiC amplifier without annealing a p-channel MOS transistor with NO.

[0010] With regard to the elimination of the above-mentioned problem, the present invention provides a semiconductor device capable of reducing the offset drift of an amplifier caused by the NBTI of a p-channel MOS transistor, and an integrated circuit provided with the semiconductor device.

[0011] The above-mentioned subject matter, a further subject matter and novel features of the present invention are further clarified by the description contained herein and the accompanying drawings.

[0012] The semiconductor device of the present invention comprises: an n-channel MOS transistor formed on a main surface of a substrate using silicon carbide, and a p-channel MOS transistor formed on a main surface of a substrate using silicon carbide. Both the n-channel MOS transistor and the p-channel MOS transistor further have a gate electrode on the main surface of the substrate via a gate oxide film, and a hanging bond at an interface between the substrate and the gate oxide film is passivated by an added element. Furthermore, in the semiconductor device of the present invention, the concentration of the element with which the hanging bond is passivated in the p-channel MOS transistor is lower than that with which the hanging bond is passivated in the n-channel MOS transistor.

[0013] The integrated circuit of the present invention is furthermore equipped with a semiconductor device comprising a plurality of n-channel MOS transistors formed on the main surface of a substrate using silicon carbide and a plurality of p-channel MOS transistors formed on the main surface of a substrate using silicon carbide.

[0014] The integrated circuit of the present invention comprises a plurality of n-channel MOS transistors and a plurality of p-channel MOS transistors. These n-channel and p-channel MOS transistors also have a gate electrode on the main surface of the substrate via a gate oxide film. Simultaneously, the bond is passivated by adding an element at the interface between the substrate and the gate oxide film.

[0015] Furthermore, in the semiconductor device of the present invention, the concentration of the element with which the hanging bond in the p-channel MOS transistors is passivated is smaller than the concentration of the element with which the hanging bond in the n-channel MOS transistors is passivated.

[0016] According to the above-mentioned semiconductor device of the present invention and the integrated circuit of the present invention, the concentration of the element with which the hanging bond in the p-channel MOS transistors is passivated is smaller than the concentration of the element with which the hanging bond in the n-channel MOS transistors is passivated.

[0017] This makes it possible, in particular, to reduce interfacial defects caused by an element (nitrogen or the like) with which the hanging bond is passivated, and thereby to suppress NBTI. Accordingly, if NBTI can be suppressed, the offset drift of a SiC amplifier can also be reduced.

[0018] Other items, configurations and effects compared to those mentioned above will also become apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic block diagram (cross-sectional view) of a semiconductor device of the first embodiment of the present invention. Fig. Figure 2 is a cross-sectional view to describe a method for manufacturing the semiconductor device of Fig. 1. Fig. Figure 3 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 4 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 5 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 6 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 7 is a cross-sectional view t to describe the method for manufacturing the semiconductor device of Fig. 1. Fig. Figure 8 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 9 is a cross-sectional view to describe the process for manufacturing the semiconductor device of Fig. 1. Fig. Figure 10 shows an example of the nitrogen concentration distribution in the depth direction of the n-channel MOS transistor and the p-channel MOS transistor according to the first embodiment of the present invention. Fig. Figure 11 shows another example of the nitrogen concentration distribution in the depth direction of the n-channel MOS transistor and the p-channel MOS transistor according to the first embodiment of the present invention. Fig. Figure 12 is a schematic block diagram (cross-sectional view) of a semiconductor device of the second embodiment of the present invention. Fig. Figure 13 is a schematic block diagram (cross-sectional view) of a semiconductor device of the third embodiment of the present invention. Fig. Figure 14 is a view to describe the effect of the present invention in a p-channel MOS transistor. Fig. Figure 15 is a schematic block diagram (top view) of an integrated circuit of the fourth embodiment of the present invention. Fig. Figure 16 is a schematic block diagram (circuit diagram) of an integrated circuit of the fifth embodiment of the present invention. Fig. Figure 17 is a schematic block diagram (top view) of an integrated circuit of the sixth embodiment of the present invention. DETAILED DESCRIPTION

[0019] The embodiments and examples according to the present invention are described below with reference to sentences or drawings. The structures, materials, and other specific configurations shown in the present invention are not limited to or by the embodiments and examples described herein and can also be combined or improved as needed without altering the core of the invention. Elements that are not directly related to the present invention have been omitted from the drawings.

[0020] The semiconductor device of the present invention comprises an n-channel MOS transistor formed on the main surface of a substrate using silicon carbide, and p-channel MOS transistors formed on the main surface of a substrate using silicon carbide. Both the n-channel MOS transistor and the p-channel MOS transistor have a gate electrode on the main surface of the substrate via a gate oxide film, and the hanging bond is passivated by adding an element at the interface between the substrate and the gate oxide film.

[0021] Furthermore, in the semiconductor device of the present invention, the concentration of an element with which a hanging bond in the p-channel MOS transistor is passivated is smaller than the concentration of an element with which a hanging bond in the n-channel MOS transistor is passivated.

[0022] The integrated circuit of the present invention is furthermore equipped with a semiconductor device comprising a plurality of n-channel MOS transistors formed on the main surface of a substrate using silicon carbide and a plurality of p-channel MOS transistors formed on the main surface of a substrate using silicon carbide.

[0023] The integrated circuit of the present invention comprises a plurality of n-channel MOS transistors and a plurality of p-channel MOS transistors. These n-channel and p-channel MOS transistors also have a gate electrode on the main surface of the substrate via a gate oxide film. Simultaneously, the bond is passivated by adding an element at the interface between the substrate and the gate oxide film.

[0024] Furthermore, in the semiconductor device of the present invention, the concentration of the element with which the hanging bond in the p-channel MOS transistors is passivated is smaller than the concentration of the element with which the hanging bond in the n-channel MOS transistors is passivated.

[0025] In short, the integrated circuit of the present invention is an integrated circuit provided with a semiconductor device comprising a plurality of n-channel MOS transistors formed on the main surface of a substrate using silicon carbide and a plurality of p-channel MOS transistors formed on the main surface of a substrate using silicon carbide, and employing as the semiconductor device the above-mentioned semiconductor device of the present invention.

[0026] According to the semiconductor device and the integrated circuit of the present invention, the concentration of an element with which the hanging bond in the p-channel MOS transistor is passivated is correspondingly smaller than the concentration of an element with which the hanging bond in the n-channel MOS transistor is passivated.

[0027] This makes it possible, in particular, to reduce interfacial defects caused by an element (nitrogen or the like) with which the hanging bond is passivated, and thereby to suppress the NBTI. Consequently, if the NBTI can be suppressed, the offset drift of a SiC amplifier can also be reduced.

[0028] Furthermore, the reduction of interface defects is also effective in reducing low-frequency noise, and this makes it possible in particular to reduce the discontinuity of the amplifier output at DC (direct current).

[0029] The semiconductor device mentioned above can have a structure in which the p-channel MOS transistor is smaller than the n-channel MOS transistor in the maximum concentration in the concentration distribution of an element with which the hanging bond is passivated.

[0030] According to the setup described above, since the maximum concentration in the concentration distribution of an element in the p-channel MOS transistor is small, the concentration of the element can be reduced.

[0031] The above-mentioned semiconductor device can have a structure in which the p-channel MOS transistor is smaller than the n-channel MOS transistor in the integration value of the concentration in the concentration distribution of an element with which the hanging bond is passivated.

[0032] Since the integration value of the concentration in the concentration distribution of an element is proportional to the initial quantity of the element, it can be estimated from the initial quantity of the element. This means that a reduction in the integration value of the concentration in the concentration distribution of the element can be achieved by reducing the initial quantity of the element.

[0033] The integration value of the concentration in the concentration distribution of the element in the above-mentioned setup in the p-channel MOS transistor is small, which makes it possible to further reduce the concentration of the element.

[0034] The above-mentioned semiconductor device can furthermore have a structure in which the gate oxide film of the p-channel MOS transistor has a smaller thickness than the n-channel MOS transistor.

[0035] Since the gate oxide film of the p-channel MOS transistor is thinner than that of the n-channel MOS transistor in the above-mentioned setup, this setup can improve the effect of suppressing NBTI, reducing the offset drift of the SiC amplifier, and reducing the discontinuity of the amplifier output at DC (direct current).

[0036] The semiconductor device mentioned above can also have a structure in which the substrate used to form the n-channel MOS transistor and the substrate used to form the p-channel MOS transistor are the same.

[0037] Such a setup can particularly reduce the number of substrates, since only one substrate is needed.

[0038] The above-mentioned semiconductor device can further have a structure in which the substrate used to form the n-channel MOS transistor and the substrate used to form the p-channel MOS transistor are each different substrates.

[0039] Since in this setup the substrate used to form the n-channel MOS transistor and the substrate used to form the p-channel MOS transistor are different substrates, it is possible to reduce the number of formation times of a resist or the like, which is used as a mask when manufacturing a semiconductor device with such a setup, and thereby simplify the manufacturing steps.

[0040] The integrated circuit mentioned above can further have a structure in which a plurality of n-channel MOS transistors are formed on a first substrate and a plurality of p-channel MOS transistors are formed on a second substrate that differs from the first substrate.

[0041] In this setup, the first substrate, used to form the n-channel MOS transistors, and the second substrate, used to form the p-channel MOS transistors, are different substrates. When fabricating an integrated circuit with such a setup, it is therefore possible to reduce the number of formation steps for a resist or similar component used as a mask, thereby simplifying the fabrication process.

[0042] The above-mentioned integrated circuit can furthermore have a structure in which it also includes a differential circuit and the differential circuit or a section of the differential circuit is formed on the same substrate as that of a plurality of n-channel MOS transistors and / or a plurality of p-channel MOS transistors.

[0043] Since, in this setup, the multitude of n-channel MOS transistors and / or the multitude of p-channel MOS transistors and the differential circuit are implemented on the same substrate, the n-channel MOS transistors and / or the p-channel MOS transistors implemented on the same substrate as that of the differential circuit can be made to exhibit similar characteristics. Consequently, the offset drift of the differential circuit can be suppressed by the aforementioned setup.

[0044] The integrated circuit mentioned above can furthermore have a structure in which a large number of n-channel MOS transistors and a large number of p-channel MOS transistors are formed on the same substrate.

[0045] According to this design, since the n-channel MOS transistors and the p-channel MOS transistors are formed on the same substrate, a structure for connecting between substrates can be eliminated, the number of parts, such as electrode pads and metal wire, can be reduced, and consequently the degree of freedom in designing the layout of the integrated circuit can be improved.

[0046] The semiconductor device and the integrated circuit according to the present invention can also be applied to different products using a semiconductor device.

[0047] In particular, nuclear instrumentation devices, such as pressure transmitters, to which the above-mentioned semiconductor device or integrated circuit is applied, can exhibit excellent radiation resistance and improved safety because the semiconductor device and the integrated circuit each comprise a silicon carbide-based substrate.

[0048] Furthermore, the application of the semiconductor device or integrated circuit according to the present invention makes it possible to suppress the NBTI and thereby further reduce the offset drift of a SiC amplifier. This also reduces low-frequency noise and thus decreases the discontinuity of the amplifier's output at DC (direct current).

[0049] The nuclear implementation devices can also be applied to various devices in a nuclear power plant, such as decommissioning robots or radiation-utilizing devices.

[0050] In semiconductor devices and integrated circuits, examples of an element used to passivate a hanging bond at the interface between the substrate and the gate oxide film of n-channel MOS transistors and p-channel MOS transistors include nitrogen (N), hydrogen (H), and phosphorus (P).

[0051] Examples of a gas to be supplied to terminate a hanging bond with nitrogen include, for example, NO, N2O and NH3.

[0052] Examples of a gas to be supplied to passivate a hanging bond with hydrogen include, for example, H2 (hydrogen gas).

[0053] Examples of a gas to be supplied to passivate a hanging bond with phosphorus also include, for example, POCl (phosphoryl chloride).

[0054] In this process, particularly when a hanging bond is passivated with nitrogen, manufacturing costs can be further reduced by using a nitrogen compound that is available at relatively low cost.

[0055] In the above-mentioned semiconductor device and integrated circuit, the concentration of an element with which a hanging bond is passivated is smaller in the p-channel MOS transistors than in the n-channel MOS transistors.

[0056] Such a setup can be produced by setting a lower temperature and / or a shorter implantation time when the p-channel MOS transistors are implanted with an element (nitrogen, hydrogen, phosphorus or the like) that passivates a hanging bond, compared to when the n-channel MOS transistors are implanted.

[0057] A specific amount, at which a temperature is lowered or an implantation time is shortened, is to be considered, in particular, as an amount that causes at least a significant difference in the concentration of the element used. If a desired concentration of the element used in the p-channel MOS transistors is present, the amount is set to correspond to this concentration.

[0058] The effect according to the invention is described in more detail below.

[0059] One view for describing the effect according to the invention is particularly illustrated by the p-channel MOS transistors in Fig. 14 shown.

[0060] Fig. Figure 14 shows, with reference to a conventional setup and the setup according to the invention, a change in the absolute value |I d | of a drain current, i.e. the I d -V gs -Properties when a gate-source voltage V gs from 0 V to V stress and then from V stress is switched to 0 V.

[0061] In the Fig. 14 shown I d -V gs -Properties refer in particular to measurement results obtained under the conditions of room temperature and a drain-source voltage |V ds | of 50 mV were obtained. The corresponding results of the setup according to the invention are further described in Fig. 14 is represented by a solid line and the results of the conventional setup by a dashed line.

[0062] In the conventional setup, the nitrogen concentration at the interface of a channel segment of the p-channel MOS transistors is adjusted to optimize the properties of the n-channel MOS transistors. This means that, in the conventional setup, the nitrogen concentration at the interface of a channel segment of the p-channel MOS transistors is equal to the nitrogen concentration at the interface of a channel segment of the n-channel MOS transistors.

[0063] Furthermore, how from Fig. As can be seen in section 14, the displacement amount ΔV is determined by the conventional setup. t a threshold voltage is large.

[0064] In the setup of the present invention, however, the nitrogen concentration at the interface of a channel section of the p-channel MOS transistors is set lower than the nitrogen concentration at the interface of a channel section of the n-channel MOS transistors.

[0065] Accordingly, as from Fig. As can be seen in section 14, the displacement amount ΔV t The threshold voltage is greatly reduced in the inventive setup.

[0066] Therefore, by using the setup according to the invention, the displacement amount ΔV t a threshold voltage is greatly reduced, as shown by Fig. As can be seen in section 14. This makes it possible to reduce the offset drift of a SiC amplifier, so that the semiconductor device or integrated circuit can exhibit improved stability.

[0067] The specific embodiments of the semiconductor device and the integrated circuit according to the present invention are described below with reference to some drawings. First embodiment

[0068] First, a semiconductor device according to a first embodiment of the present invention is described.

[0069] A schematic block diagram (cross-sectional view) of the semiconductor device of the first embodiment of the present invention is shown in the following. Fig. 1 shown.

[0070] The in Fig. The semiconductor device shown is formed using an n-type SiC substrate 1, which is a semiconductor substrate made of SiC (silicon carbide).

[0071] More precisely described, the in Fig. 1 Semiconductor device shown includes an n-channel MOS transistor 101 and a p-channel MOS transistor 102 on an n-type SiC epitaxy layer 2 formed on an n-type SiC substrate 1.

[0072] In the n-channel MOS transistor 101, an n-type high-concentration layer 5 is formed on the surface section of a p-type well 4, which in turn is formed on the n-type SiC epitaxial layer 2. In the n-channel MOS transistor 101, a gate electrode 6 made of polysilicon is also formed on the p-type well layer 4 via a gate oxide film 7.

[0073] In the p-channel MOS transistor 102, a p-type high-concentration layer 3 is formed on the surface section of the n-type SiC epitaxic layer 2. Furthermore, in the p-channel MOS transistor 102, a gate electrode 6 made of polysilicon is formed on the n-type SiC epitaxic layer 2 via a gate oxide film 7.

[0074] The n-channel MOS transistor 101 and the p-channel MOS transistor 102 are insulated by a thick oxide film layer 8 formed on the n-type SiC epitaxy layer 2 and a passivation layer 9 formed to cover the entire surface.

[0075] A region 10a, comprising a section intended to be a channel of the n-channel MOS transistor 101 and located near an interface between the p-well layer 4 and the gate oxide film 7, is implanted with nitrogen and therefore passivated to passivate a hanging bond.

[0076] Likewise, a region 10b, which includes a section intended to be a channel of the p-channel MOS transistor 102 and is located near an interface between the n-type SiC epitaxy layer 2 and the gate oxide film 7, is implanted with nitrogen and therefore passivated to passivate a hanging bond.

[0077] In the semiconductor device of the present embodiment, the concentration of nitrogen with which the interface between the gate oxide film 7 and a SiC layer is implanted to passivate a hanging bond is different, in particular between the region 10a of the n-channel MOS transistor 101 and the region 10b of the p-channel MOS transistor 102.

[0078] In other words, the concentration of nitrogen with which the interface between the gate oxide film 7 and a SiC layer is implanted in region 10b of the p-channel MOS transistor 102 is smaller than that in region 10a of the n-channel MOS transistor 101.

[0079] According to the semiconductor device of the present embodiment, the nitrogen concentration in region 10b of the p-channel MOS transistor 102 is smaller than that in region 10a of the n-channel MOS transistor 101.

[0080] This makes it possible to reduce nitrogen-induced interface defects and suppress the NBTI in the p-channel MOS transistor. Similarly, if the NBTI can be suppressed, the offset drift of a SiC amplifier can also be reduced.

[0081] Furthermore, the reduction of interface defects can also be used to reduce low-frequency noise, which makes it possible to reduce the discontinuity of the output of an amplifier at DC (direct current).

[0082] The method for manufacturing the semiconductor device according to the present embodiment is further described with reference to the cross-sectional views in the Fig. 2 to Fig. 9 described.

[0083] First, an n-type SiC epitaxic layer 2 is formed by inducing epitaxial growth of a SiC layer on an n-type SiC substrate 1. The n-type SiC epitaxic layer 2, which has a desired impurity concentration, can be formed by inducing epitaxial growth while an n-type impurity (for example, N) is introduced, if required.

[0084] Subsequently, a resist 21 is formed on the n-type SiC epitaxy layer 2. The resist 21 is then structured to remove a section of the resist 21 corresponding to the p-type well layer 4 of the n-type SiC epitaxy layer 2.

[0085] Furthermore, as in Fig. 2 shown, with the resulting resist 21 as a mask, an ion implantation of a p-type impurity (for example, Al) is carried out on the n-type SiC epitaxy layer 2, which is formed on the n-type SiC substrate 1, to form a p-type well layer 4.

[0086] Subsequently, resist 21 is removed and a resist 22 is formed on the n-type SiC epitaxy layer 2. The resist 22 is then structured to remove it from a section of the n-type SiC epitaxy layer 2 and to form an n-type high-concentration layer 5.

[0087] Furthermore, as in Fig. Figure 3 shows that, with the resulting resist 22 acting as a mask, an ion implantation of a p-type impurity (for example, Al) is carried out into a surface section of the n-type SiC epitaxy layer 2 to form a p-type high concentration layer 3.

[0088] The p-type high-concentration layer 3 is designed such that it has a contamination concentration that is higher than that of the p-type trough layer 4.

[0089] Subsequently, resist 22 is removed and a resist 23 is formed on the n-type SiC epitaxy layer 2. Simultaneously, resist 23 is structured to remove a section of resist 23 from a section of the p-type well layer 4 and to form an n-type high-concentration layer 5.

[0090] Then, as in Fig. 4 shown, with the resulting resist 23 as a mask, an ion implantation of an n-type impurity (for example N) into a surface section of the p-type trough layer 4 is carried out to form an n-type high concentration layer 5.

[0091] Subsequently, the resist 23 is removed and, after the formation of an oxide film layer 8 on the n-type SiC epitaxy layer 2, a resist 24 is formed. This resist 24 is then also structured.

[0092] Then, as in Fig. 5 shown, with the resulting resist 24 acting as a mask, an etching was performed and a thick oxide film layer 8 was removed on a region that includes a section which will be a channel, between the n-type high concentration layers 5 to form an opening.

[0093] The Resist 24 is then removed and, as described in Fig. Figure 6 shows a gate oxide film 7a formed to cover the surface.

[0094] Furthermore, as in Fig. Figure 6 shows that region 10a, which includes a section that is to be a channel of the n-channel MOS transistor 101 and is located near the interface between the p-type well layer 4 and the gate oxide film 7, was subjected to passivation by NO annealing.

[0095] Subsequently, a polysilicon layer is formed on the gate oxide film 7a, followed by structuring of the polysilicon layer to form a gate electrode 6 of the n-channel MOS transistor 101.

[0096] The surface is then covered to form a resist 25, and the resulting resist 25 is also textured.

[0097] As in Fig. As shown in Figure 7, an etching is then carried out using the resist 25 as a mask to remove the gate oxide film 7a and the oxide film layer 8 on a region that includes a section intended to be a channel between the p-type high concentration layers 3, thereby forming an opening.

[0098] The Resist 25 is then removed and, as described in Fig. 8 shown, covering the surface to form a gate oxide film 7b.

[0099] Furthermore, as in Fig. Figure 8 shows a region 10b comprising a section that is intended to be a channel of the p-channel MOS transistor 102 and is located near the interface between the n-type SiC epitaxy layer 2 and the gate oxide film 7b, subjected to passivation by NO annealing.

[0100] The nitrogen concentration of the NO annealing process is set lower at this point than the nitrogen concentration of the NO annealing process subjected to the section that serves as a channel of the [unclear text]. Fig. The 6 n-channel MOS transistors 101 are to be formed.

[0101] The surface is then coated to form a polysilicon layer, followed by structuring of the polysilicon layer to form a gate electrode 6 of the p-channel MOS transistor 102. Using this gate electrode 6 of the p-channel MOS transistor 102 as a mask, etching is also performed to remove the gate oxide film 7b and the gate oxide film 7a.

[0102] As a result, a gate oxide film 7, consisting of gate oxide film 7b and gate oxide film 7a, remains under the gate electrode 6 of the p-channel MOS transistor 102, as shown in Fig. 9 shown.

[0103] Subsequently, a passivation layer 9 is formed so that it covers the entire surface. In this way, the Fig. 1 Semiconductor device of the present embodiment shown can be manufactured.

[0104] In the present embodiment, the nitrogen concentration of a section comprising the channel of the p-channel MOS transistor 102 is set lower than that of a section comprising the channel of the n-channel MOS transistor 101. It is assumed that several different configurations with respect to nitrogen concentration are possible. Examples of configurations with different nitrogen concentrations are further described below.

[0105] An example of the nitrogen concentration distribution in the depth direction of the n-channel MOS transistor 101 and the p-channel MOS transistor 102 in the present embodiment is shown in Fig. 10.

[0106] At the in Fig. In the nitrogen concentration distribution shown in Figure 10, the maximum nitrogen concentration (peak in the distribution in the depth direction) in the p-channel MOS transistor 102 is set lower than in the n-channel MOS transistor 101.

[0107] Furthermore, another example of the nitrogen concentration distribution in the depth direction of the n-channel MOS transistor 101 and the p-channel MOS transistor 102 in the present embodiment is shown in Fig. 11 shown.

[0108] At the in Fig. In the nitrogen concentration distribution shown in Figure 11, the integration value of the nitrogen concentration (width in the distribution in the depth direction) in the p-channel MOS transistor 102 is set lower than in the n-channel MOS transistor 101.

[0109] The integration value of the nitrogen concentration is difficult to measure directly, but can be considered proportional to the amount of nitrogen introduced.

[0110] Therefore, the integration value of the nitrogen concentration can be set lower by setting the nitrogen input quantity of the p-channel MOS transistor 102 lower than that of the n-channel MOS transistor 101.

[0111] Examples of a specific step to reduce the nitrogen concentration, as described above, may include reducing the nitration temperature, reducing the nitration time, and using them in combination. Second embodiment

[0112] Next, a semiconductor device according to a second embodiment of the present invention will be described.

[0113] The schematic block view (cross-sectional view) of the semiconductor device of the second embodiment of the present invention is shown in Fig. 12 shown.

[0114] At the in Fig. In the semiconductor device shown in Figure 12, the n-channel MOS transistor 101 and the p-channel MOS transistor 102 are represented on the respective different Sie substrates 1.

[0115] Furthermore, the in Fig. Figure 12 shows a semiconductor device in which the nitrogen concentration of region 10b of the p-channel MOS transistor 102 is smaller than that of region 10a of the n-channel MOS transistor 101.

[0116] With regard to its further structure, the semiconductor device of the present embodiment is also similar to that described in Fig. 1 embodiment shown, so that an overlapping description is omitted.

[0117] Even if a semiconductor device has a structure in which the n-channel MOS transistor 101 and the p-channel MOS transistor 102 are represented on the respective different SiC substrates 1, as in Fig. As shown in 12, an effect similar to that caused by the in Fig. The semiconductor device shown in 1 can be obtained by applying the present invention to it.

[0118] In other words, by adopting a setup in which the nitrogen concentration of region 10b of the p-channel MOS transistor 102 is reduced compared to region 10a of the n-channel MOS transistor 101, the NBTI can be suppressed and thus the offset drift of the SiC amplifier can be reduced.

[0119] Furthermore, the discontinuity of the amplifier's output can be reduced at DC (direct current).

[0120] In particular, the following are in Fig. Figure 12 shows the semiconductor device of the present embodiment, which comprises the n-channel MOS transistor 101 and the p-channel MOS transistor 102, each on a different SiC substrate 1. Therefore, if the Fig. In addition to the semiconductor device shown in Figure 12, it is also possible to fabricate the n-channel MOS transistor 101 and the p-channel MOS transistor 102 separately in advance by connecting them together, thereby creating the Fig. The semiconductor device shown in Figure 12 is completed. By using such a method, the number of formation times of a resist or the like, used as a mask, can be reduced accordingly. In other words, in the Fig. 2 to Fig. Figure 7, which shows the manufacturing process of the first embodiment, shows five resists 21 to 25. However, when the semiconductor device of the present embodiment is manufactured, some (21, 23 and 24 or 22 and 25) of the five resists 21 to 25 can also be formed in each of the transistors 101 and 102. Third embodiment

[0121] Next, the semiconductor device according to a third embodiment of the present invention will be described.

[0122] The schematic block diagram (cross-sectional view) of the third embodiment of the present invention is shown in the following. Fig. 13 shown.

[0123] At the in Fig. In the semiconductor device shown in Figure 13, the thickness of a gate oxide film 7d of the p-channel MOS transistor 102 is smaller than that of a gate oxide film 7c of the n-channel MOS transistor 101.

[0124] With regard to its further structure, the semiconductor device of the present embodiment is also similar to that described in Fig. 1 embodiment shown, so that an overlapping description is omitted.

[0125] At the in Fig. In the semiconductor device shown in Figure 13, the thickness of the gate oxide film 7d of the p-channel MOS transistor 102 is smaller than that of the gate oxide film 7c of the n-channel MOS transistor 101. This design can also suppress the NBTI and thus reduce the offset drift of the SiC amplifier. Furthermore, it can also reduce the discontinuity of the amplifier's output at DC (direct current).

[0126] By combining the setup in which the nitrogen concentration of region 10b of the p-channel MOS transistor 102 is smaller than that of region 10a of the n-channel MOS transistor 101, and the setup specific to the present embodiment in which the thickness of the gate oxide film 7d of the p-channel MOS transistor 102 is smaller than that of the gate oxide film 7c of the n-channel MOS transistor 101, it is possible to improve the effects of suppressing NBTI, reducing the offset drift of the SiC amplifier, and reducing the discontinuity of the amplifier output at DC (direct current). Fourth embodiment

[0127] The following describes an integrated circuit according to the fourth embodiment of the present invention.

[0128] The schematic block diagram (top view) of the integrated circuit of the fourth embodiment of the present invention is shown in Fig. 15 shown.

[0129] The integrated circuit of the present embodiment, which in Fig. The embodiment shown in 15 is similar to that of the second embodiment, which is shown in Fig. Figure 12 shows that the n-channel MOS transistor 101 and the p-channel MOS transistor 102 are represented on different substrates.

[0130] The integrated circuit of the present embodiment further comprises three n-channel MOS transistors 101 and three p-channel MOS transistors 102.

[0131] The three n-channel MOS transistors 101 are formed on a first chip 201 and the three p-channel MOS transistors 102 are formed on a second chip 202.

[0132] The first chip 201 and the second chip 202 are also formed on a die pad 204.

[0133] The first chip 201 and the second chip 202 each have seven electrode pads 203. Of these seven electrode pads 203, four, located at the right end section or the left end section, are connected via a metal wire 206 to a terminal 205 located outside the chip. Additionally, two of the seven electrode pads 203 located at an end section on the side of the adjacent chip are connected via a metal wire 206 to the electrode pad 203 of the adjacent chip.

[0134] Although not shown in the diagram, the three n-channel MOS transistors 101 and the three p-channel MOS transistors 102 each have a gate electrode on the main surface of the substrate of chips 201 and 202 via a gate oxide film and simultaneously a hanging bond which is passivated by adding nitrogen to the interface between the substrate and the gate oxide film.

[0135] Furthermore, the integrated circuit of the present embodiment has a structure in which the concentration of nitrogen with which a hanging bond in the three p-channel MOS transistors 102 is passivated is smaller than that of nitrogen with which a hanging bond in the three n-channel MOS transistors is passivated.

[0136] According to the integrated circuit of the present embodiment, the concentration of nitrogen with which a hanging bond in the three p-channel MOS transistors 102 is passivated is correspondingly smaller than that of nitrogen with which a hanging bond in the three n-channel MOS transistors is passivated.

[0137] Similar to the ones in Fig. 1 Semiconductor device of the first embodiment shown or the one shown in Fig. The semiconductor device of the second embodiment shown in Figure 12 can suppress the NBTI accordingly, thus reducing the offset drift of the SiC amplifier. Furthermore, the discontinuity of the amplifier's output at DC (direct current) can be reduced.

[0138] Furthermore, according to the integrated circuit of the present embodiment, the three n-channel MOS transistors 101 are formed on the first chip 201 and the three p-channel MOS transistors 102 are formed on the second chip 202.

[0139] Since three n-channel MOS transistors 101 are formed on the same first chip 201, these three n-channel MOS transistors 101 can be manufactured similarly in properties, such as threshold voltage.

[0140] Since three p-channel MOS transistors 102 are also formed on the same second chip 202, these three p-channel MOS transistors 102 can also be manufactured similarly in properties, such as the threshold voltage.

[0141] The properties of the integrated circuit can thus be stabilized, since the properties of the three n-channel MOS transistors 101 or those of the three p-channel MOS transistors 102 can be manufactured similarly, as described above.

[0142] This includes in the Fig. Although seven electrode pads 203 and three MOS transistors 101 or 102 are formed on the first chip 201 or the second chip 202 in the integrated circuit shown in Figure 15, the number of electrode pads or MOS transistors to be provided on each chip is not limited to the number mentioned above, so that it can also be changed to another number. Fifth embodiment

[0143] Next, an integrated circuit of the fifth embodiment of the present invention will be described.

[0144] The schematic block diagram (circuit view) of the integrated circuit of the fifth embodiment of the present invention is shown here in Fig. 16 shown.

[0145] The in Fig. The integrated circuit of the present embodiment shown in Figure 16 comprises input terminals 301a and 301b, an output terminal 302, a power supply line 303 on a high-voltage side, a power supply line 304 on a low-voltage side, a phase compensation capacitor Cc, n-channel MOS transistors M1 and M2, p-channel MOS transistors M3 and M4, a resistor R and MOS transistors M5, M6, M7 and M8.

[0146] The input terminal 301a is connected to the gate of the n-channel MOS transistor M1.

[0147] The input terminal 301b is also connected to the gate of the n-channel MOS transistor M2.

[0148] The output terminal 302 is also connected to the source or drain of the n-channel MOS transistor M2 via the phase compensation capacitor Cc.

[0149] The source or drain of the n-channel MOS transistors M1 and M2 is also connected to the MOS transistor M7. Furthermore, the source or drain of the n-channel MOS transistors M1 and M2 is also connected to the source or drain of the p-channel MOS transistors M3 and M4, which are adjacent to each other.

[0150] The source or drain of the p-channel MOS transistors M3 and M4 is also connected to the power supply line 303 on a high-voltage side.

[0151] The source or drain of the n-channel MOS transistor M1 and the source or drain of the p-channel MOS transistor M3 are further connected to the gates of the p-channel MOS transistors M3 and M4.

[0152] The source or drain of the n-channel MOS transistor M2 and the source or drain of the p-channel MOS transistor M4 are further connected to the gate of the MOS transistor M6 and one of the electrodes of the phase compensation capacitor Cc.

[0153] Furthermore, the other electrode of the phase compensation capacitor Cc is connected to the output terminal 302, the source or drain of the MOS transistor M5 and the source or drain of the MOS transistor M6.

[0154] The source or drain of each of the MOS transistors M5, M7 and M8 is also connected to the power supply line 304 on the low voltage side.

[0155] Furthermore, the source or drain of the MOS transistor M6 is also connected to the power supply line 303 on the high-voltage side.

[0156] The source or drain of the MOS transistor M8 is also connected to the power supply line 303 on the high-voltage side via resistor R. Furthermore, the source or drain of the MOS transistor M8 is also connected to the gate of the MOS transistor M8.

[0157] At the in Fig. The integrated circuit shown in Figure 16 consists of a differential circuit (SiC amplifier) ​​consisting of the input terminals 301a and 301b, the output terminal 302, the n-channel MOS transistors M1 and M2, the power supply line 303 on the high-voltage side, the power supply line 304 on the low-voltage side, the phase compensation capacitor Cc, and the like.

[0158] This differential circuit can amplify a difference between a signal to be input into input terminal 301a and a signal to be input into input terminal 301b and output it from output terminal 302.

[0159] The integrated circuit of the present embodiment also has a structure in which the concentration of nitrogen with which a hanging bond in the two p-channel MOS transistors M3 and M4 is passivated is smaller than the concentration of nitrogen with which a hanging bond in the two n-channel MOS transistors M1 and M2 is passivated.

[0160] This makes it possible to suppress the NBTI and thus reduce the offset drift of the SiC amplifier. Furthermore, the discontinuity of the amplifier's output at DC (direct current) can be reduced.

[0161] In particular, in the integrated circuit of the present embodiment, two n-channel MOS transistors M1 and M2 are formed in a region 305 on at least the same chip. Furthermore, two p-channel MOS transistors M3 and M4 are also formed in a region 306 on at least the same chip.

[0162] The chip formed in region 305 (n-channel MOS transistors M1 and M2) and the chip formed in region 306 (p-channel MOS transistors M3 and M4) can be the same or different chips.

[0163] Especially in the Fig. The differential circuit shown in Figure 16 is formed on the same chip as the one on which region 305 (two n-channel MOS transistors M1 and M2) is formed.

[0164] In addition to the above-mentioned setup where the nitrogen concentration is low, this setup can also suppress the offset drift of the differential circuit (SiC amplifier).

[0165] By placing the two p-channel MOS transistors M3 and M4 on the same chip in region 306, the two p-channel MOS transistors M3 and M4 can have similar properties.

[0166] This makes it possible to greatly reduce the difference in the threshold voltage between two p-channel MOS transistors M3 and M4 compared to a setup where the two transistors are formed on separate chips, thus enabling the integrated circuit to exhibit stable characteristics.

[0167] At the in Fig. In the setup shown in Figure 16, the differential circuit is formed on the same chip as the one on which the n-channel MOS transistors M1 and M2 are formed; however, the setup of the integrated circuit of the present invention is not limited to such a chip.

[0168] The structure can also be designed in such a way that it has a differential circuit on a chip which in turn has a p-channel MOS transistor, or in such a way that it has a differential circuit on a chip which in turn has both the n-channel MOS transistor and the p-channel MOS transistor.

[0169] The design is not limited to those that have a differential circuit on the same chip as the one on which the MOS transistor is located, but can also be designed in such a way that it has a section of a differential circuit on the same chip as the one on which the MOS transistor is located. Sixth embodiment

[0170] Next, an integrated circuit of the sixth embodiment of the present invention will be described.

[0171] The schematic block diagram (top view) of the integrated circuit of the sixth embodiment of the present invention is shown here in Fig. 17 shown.

[0172] The integrated circuit of the present embodiment, which in Fig. 17 is similar to the semiconductor device of the first embodiment shown in Fig. Figure 1 shows that the n-channel MOS transistor 101 and the p-channel MOS transistor 102 are represented on the same substrate.

[0173] The integrated circuit of the present embodiment further comprises three n-channel MOS transistors 101 and three p-channel MOS transistors 102, wherein these three n-channel MOS transistors 101 and three p-channel MOS transistors 102 are all located on a single chip 207. The chip 207 is also located on a die pad 204.

[0174] The chip 207 has eight electrode pads 203. Of these eight electrode pads 203, four pads are provided at the right end section or the left end section of the chip 207 and are connected via a metal wire 206 to a terminal 205, which is provided outside the chip.

[0175] Although not shown in the diagram, the three n-channel MOS transistors 101 and the three p-channel MOS transistors 102 each have a gate electrode on the main surface of the substrate of the chip 207 via a gate oxide film and simultaneously a hanging bond that is passivated by adding nitrogen to the interface between the substrate and the gate oxide film.

[0176] Furthermore, the integrated circuit of the present embodiment has a structure in which the concentration of nitrogen with which a hanging bond in the three p-channel MOS transistors 102 is passivated is smaller than that of nitrogen with which a hanging bond in the three n-channel MOS transistors is passivated.

[0177] Another structure is also similar to that of the one in Fig. 15 integrated circuits shown, so that an overlapping description is omitted.

[0178] According to the integrated circuit of the present embodiment, the concentration of nitrogen with which a hanging bond in the three p-channel MOS transistors 102 is passivated is correspondingly smaller than that of nitrogen with which a hanging bond in the three n-channel MOS transistors is passivated.

[0179] Similar to the ones in Fig. 1 Semiconductor device of the first embodiment shown or the one shown in Fig. The semiconductor device of the second embodiment shown in Figure 12 can suppress the NBTI accordingly, thus reducing the offset drift of the SiC amplifier. Furthermore, the discontinuity of the amplifier's output at DC (direct current) can be reduced.

[0180] According to the integrated circuit of the present embodiment, the three n-channel MOS transistors 101 and the three p-channel MOS transistors 102 are formed on the same chip 207.

[0181] Since the three n-channel MOS transistors 101 are formed on the same chip 207, these three n-channel MOS transistors 101 can be manufactured similarly in properties, such as the threshold voltage.

[0182] Since the three p-channel MOS transistors 102 are also formed on the same chip 207, these three p-channel MOS transistors 102 can also be manufactured in a similar way in terms of properties such as threshold voltage.

[0183] The properties of the integrated circuit can thus be stabilized, since the properties of the three n-channel MOS transistors 101 or those of the three p-channel MOS transistors 102 can be manufactured similarly, as described above.

[0184] In the integrated circuit of the present embodiment, three n-channel MOS transistors 101 and three p-channel MOS transistors 102 are each represented on a chip 207.

[0185] In this integrated circuit, the manufacturing steps for chip 207 are more complicated than those of the one in Fig. 15 shown integrated circuit, however, the setup for connecting between substrates becomes unnecessary, making it possible to reduce the number of electrode pads 203 and metal wires 206 and thereby increase the degree of freedom in designing the layout of the integrated circuit.

[0186] The Die-Pad 204 in Fig. 17 has the same area as the one in Fig. 15, however, due to the increased degree of freedom in designing the layout, the distance between the n-channel MOS transistor 101 and the p-channel MOS transistor 102 can be narrower than that shown in Fig. Figure 17 shows the configuration. By narrowing the distance as described above, the respective areas of the chip 207 and the die pad 204 can be reduced, and thus an integrated circuit with a smaller size can be produced.

[0187] The in Fig.The integrated circuit shown in Figure 17 also features eight electrode pads 203, three n-channel MOS transistors 101 and three p-channel MOS transistors 102 on the chip 207.

[0188] However, the number of electrode pads and the number of MOS transistors provided on the chip are not limited to these numbers, and any other number is possible. (Modification example)

[0189] In the description of each of the above-mentioned embodiments, an element with which a hanging bond at the interface between the substrate of the MOS transistors 101 and 102 and the gate oxide film is passivated is nitrogen.

[0190] However, the element used to passivate a hanging bond is not limited to nitrogen; other elements, such as hydrogen or phosphorus, can also be used.

[0191] Furthermore, the present invention is not limited to the structures described above in the embodiments and examples, and various modifications can be made without deviating from the technical scope of protection of the present invention. Some or all of the structures described above in the examples can also be combined. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2019-12780

[0003]

Claims

[1] A semiconductor device comprising: an n-channel MOS transistor formed on a main surface of a substrate using silicon carbide, and a p-channel MOS transistor formed on a main surface of a substrate using silicon carbide, wherein: Both the n-channel MOS transistor and the p-channel MOS transistor have a gate electrode on the main surface of the substrate via a gate oxide film, and a hanging bond at an interface between the substrate and the gate oxide film is passivated by an added element, and a concentration of the element with which the hanging bond in the p-channel MOS transistor is passivated is smaller than that with which the hanging bond in the n-channel MOS transistor is passivated. [2] The semiconductor device according to claim 1, wherein the element nitrogen, and The concentration of nitrogen in the p-channel MOS transistor is smaller than that in the n-channel MOS transistor. [3] The semiconductor device according to claim 1, wherein a maximum concentration in a concentration distribution of the element in the p-channel MOS transistor is smaller than in the n-channel MOS transistor. [4] The semiconductor device according to claim 1, wherein an integration value of a concentration in a concentration distribution of the element in the p-channel MOS transistor is smaller than in the n-channel MOS transistor. [5] The semiconductor device according to claim 1, wherein the gate oxide film of the p-channel MOS transistor is thinner than the gate oxide film of the n-channel MOS transistor. [6] The semiconductor device according to claim 1, wherein the n-channel MOS transistor and the p-channel MOS transistor are on the same substrate. [7] The semiconductor device according to claim 1, wherein the n-channel MOS transistor and the p-channel MOS transistor are on different substrates. [8] An integrated circuit provided with a semiconductor device comprising: a plurality of n-channel MOS transistors formed on a major surface of a substrate using silicon carbide; and a plurality of p-channel MOS transistors formed on a major surface of a substrate using silicon carbide, wherein the integrated circuit features a multitude of n-channel MOS transistors and a multitude of p-channel MOS transistors, the multitude of n-channel MOS transistors and the multitude of p-channel MOS transistors each have a gate electrode on the main surface of the substrate via a gate oxide film, and at the same time a hanging bond with added nitrogen is passivated at the interface between the substrate and the gate oxide film, and a concentration of the element with which the hanging bond is passivated in the plurality of p-channel MOS transistors is smaller than that of the element with which the hanging bond is passivated in the plurality of n-channel MOS transistors. [9] The integrated circuit according to claim 8, wherein the plurality of n-channel MOS transistors are formed on a first substrate, and the plurality of p-channel MOS transistors are formed on a second substrate which differs from the first substrate. [10] The integrated circuit according to claim 8, further comprising a differential circuit, wherein the differential circuit or a section of the differential circuit is formed on the same substrate as that of the plurality of n-channel MOS transistors and / or the plurality of p-channel MOS transistors. [11] The integrated circuit according to claim 8, wherein the plurality of n-channel MOS transistors and the plurality of p-channel MOS transistors are formed on the same substrate.

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