Capacitor manufacturing process
The integrated circuit manufacturing process for capacitors addresses existing drawbacks by employing a multi-step engraving and cleaning process using plasma, which reduces short-circuit risks and lowers production costs.
Patent Information
- Application Number
- FR2022011799
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-11-14
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2042-11-14
AI Technical Summary
Existing integrated circuit manufacturing processes with capacitors have several drawbacks, necessitating an improvement to overcome these disadvantages.
A manufacturing process for a capacitor involving successive steps: forming a stack with conductive layers and electrodes, applying a masking layer, engraving the stack using chlorinated and fluorinated plasma, and removing the masking layer followed by cleaning.
The process effectively reduces the risk of short-circuits by introducing horizontal distances between the conductive layers and electrodes, while also reducing manufacturing costs by minimizing the number of photolithography steps.
Smart Images

Figure 00000015_0000 
Figure 00000015_0001 
Figure 00000015_0002
Abstract
Description
Title of the invention: Method of manufacturing a capacitor Technical field
[0001] The present description relates generally to the manufacture of an integrated circuit and more particularly aims at the manufacture of an integrated circuit comprising a capacitor, for example a passive integrated circuit, for example an RC filter (comprising a resistor and a capacitor), an LC filter (comprising an inductor and a capacitor) or an RLC filter (comprising a resistor, an inductor and a capacitor). Prior art
[0002] Many methods for manufacturing integrated circuits comprising capacitors have been proposed. These methods have various drawbacks. There is therefore a need to improve the methods for manufacturing an integrated circuit comprising a capacitor to overcome all or part of the drawbacks of the known methods. Summary of the invention
[0003] One embodiment provides a method of manufacturing a capacitor, comprising the following successive steps: a) forming a stack comprising, in order from the upper face of a first conductive layer, a first electrode, a dielectric layer, a second electrode and a second conductive layer; b) forming, by photolithography, a masking layer on one face of the second conductive layer opposite the second electrode; c) etching, by chlorinated physicochemical plasma etching, through said masking layer, an upper part of the stack, said chlorinated physicochemical plasma etching being interrupted in the dielectric layer; d) etching, by fluorinated physicochemical plasma etching, through said masking layer, a lower part of the stack, said fluorinated physicochemical plasma etching being interrupted on the upper face of the first conductive layer; and e) remove the masking layer by a stripping process, then clean the etched flanks by a cleaning process.
[0004] According to one embodiment, the first conductive layer is based on aluminum.
[0005] According to one embodiment, the second conductive layer is based of aluminum.
[0006] According to one embodiment, during step c), dichlorine and boron trichloride are injected into the plasma source.
[0007] According to one embodiment, during step c), the dichlorine is injected with a flow rate between 50 sccm and 120 sccm, for example of the order of 80 sccm and the boron trichloride is injected with a flow rate between 20 sccm and 100 sccm, for example of the order of 50 sccm.
[0008] According to one embodiment, during step c), the plasma pressure is between 1.33 Pa and 6.67 Pa, for example of the order of 2 Pa, the source power is between 150 W and 800 W, for example of the order of 400 W and the polarization power is between 50 W and 500 W, for example between 150 W and 300 W.
[0009] According to one embodiment, during step d), sulfur hexafluoride and argon are injected into the plasma source.
[0010] According to one embodiment, during step d), the sulfur hexafluoride is injected with a flow rate of between 20 sccm and 80 sccm, for example of the order of 50 sccm, and the argon is injected with a flow rate of between 10 sccm and 100 sccm, for example of the order of 20 sccm.
[0011] According to one embodiment, during step c), the plasma pressure is between 0.67 Pa and 6.67 Pa, for example of the order of 1.33 Pa, the source power is between 150 W and 800 W, for example of the order of 500 W and the polarization power is between 20 W and 500 W, for example of the order of 50 W.
[0012] According to one embodiment, in step e), the cleaning step comprises cleaning the upper face and the sides of the second conductive layer, the sides of the second electrode, the dielectric layer, the first electrode and the upper face of the first conductive layer.
[0013] According to one embodiment, the stripping step is carried out by plasma physicochemical etching.
[0014] According to one embodiment, during the stripping step, dioxygen and water vapor are injected into the plasma source.
[0015] According to one embodiment, during the stripping step, the dioxygen is injected with a flow rate of between 700 sccm and 1000 sccm, for example of the order of 810 sccm and water vapor is injected with a flow rate of between 50 sccm and 700 sccm, for example of the order of 90 sccm or of the order of 630 sccm.
[0016] According to one embodiment, during the stripping step, the plasma pressure is between 80 Pa and 133.32 Pa, for example between 100 Pa and 120 Pa, and the RF power is between 800 W and 1500 W, for example of the order of 1100 W.
[0017] According to one embodiment, the cleaning step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol and hydroxylamine.
[0018] According to one embodiment, the proportion of 2-(2-aminoethoxy)ethanol in the solvent is between 55% and 65% and the proportion of hydroxylamine is between 10% and 20%. Brief description of the drawings
[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0020] [Fig.l] is a partial and schematic sectional view of an example of a capacitor; and
[0021] [Fig.2], [Fig.3], [Fig.4] and [Fig.5] illustrate successive steps of an example of a method of forming a capacitor according to another embodiment. Description of the embodiments
[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the main focus here is on the formation of a portion of integrated circuit forming the capacitor. More particularly, the main focus here is on an etching step making it possible to uncover a metal layer in order to resume electrical contact on a lower electrode of a capacitor of the integrated circuit. The other steps of the method for manufacturing the capacitor and the integrated circuit are within the scope of the person skilled in the art and will not be described below.
[0024] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0026] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0027] [Fig.l] is a partial and schematic sectional view of an example of a capacitor 11.
[0028] The capacitor 11 comprises, in order, from the upper face of a substrate or support 21: a first electrically conductive layer 13, also called redistribution layer (RDL); a first electrode 15 also called lower electrode; a layer 17 of a dielectric material; a second electrode 19 also called upper electrode; and a second electrically conductive layer 23.
[0029] By way of example, the lower electrode 15 is in contact, by its lower face, with the upper face of the layer 13. The dielectric layer 17 is, for example, in contact, by its lower face, with the upper face of the lower electrode 15. The upper electrode 19 is, for example, in contact, by its lower face, with the upper face of the dielectric layer 17. The conductive layer 23 is, for example, in contact, by its lower face, with the upper face of the upper electrode 19.
[0030] By way of example, the conductive layer 13 is made of a metallic material. The conductive layer 13 is, for example, made of aluminum or an alloy comprising aluminum. The conductive layer 13 is, for example, made of an alloy of aluminum and copper (AlCu) or an alloy of aluminum, copper and silicon (AlSiCu). By way of example, the layer 13 has a thickness of between 0.5 μm and 3 μm, for example of the order of 1.5 μm.
[0031] The electrode 15 is, for example, made of tantalum nitride (TaN). For example, the electrode 15 has a thickness of between 20 nm and 200 nm, for example of the order of 65 nm. The electrode 19 is, for example, made of tantalum nitride (TaN). For example, the electrode 19 has a thickness of between 20 nm and 200 nm, for example of the order of 65 nm. The electrodes 15 and 19 are, for example, made of the same material.
[0032] The dielectric layer 17 is for example made of silicon nitride. For example, the dielectric layer 17 has a thickness of between 20 nm and 600 nm, for example between 100 nm and 450 nm.
[0033] The support 21 is, for example, made of silicon, preferably highly resistive. The support 21 and the layer 13 may be separated from each other by a dielectric layer, not shown, for example an oxide layer, for example undoped silicon glass (USG, Undoped Silicon Glass) or any other silicon oxide. As a variant, the lower conductive layer 13 is in contact, by its lower face, with the upper face of the substrate 21. The support 21 carries for example one or more other elements, not shown, such as inductors or resistors formed near the capacitor and electrically connected to the capacitor.
[0034] For example, the conductive layer 23 is made of a metallic material. The conductive layer 23 is, for example, made of a metallic material that can be etched by plasma, for example by chlorinated plasma. For example, the conductive layer 23 is made of aluminum or an aluminum-based alloy. The conductive layer 23 has, for example, a thickness of between 100 nm and 1 μm, for example, of the order of 350 nm. The layer 23 makes it possible in particular to increase the electrical conductivity of the upper electrode 19 that it covers.
[0035] In the example of [Fig.l], the conductive layer 23, the electrode 19 and the upper part of the dielectric layer 17 have their flanks set back relative to those of the electrode 15 and the lower part of the dielectric layer 17. In other words, a portion of the lower part of the dielectric layer 17 is not covered by the upper part of the dielectric layer 17, the upper electrode 19 and the conductive layer 23. Thus, in [Fig.l], there is a first step between the upper face of the upper conductive layer 23 and the upper face of the dielectric layer 17. This step makes it possible to introduce a horizontal distance el between the flank of the layers 23 and 19 and the upper part of the layer 17 on the one hand, and the flank of the lower part of the layer 17 and the electrode 15 on the other hand, thus reducing the risks of short-circuiting.
[0036] For example, the conductive layer 23, the electrode 19 and an upper part of the dielectric layer 17 are, in [Fig.l], aligned vertically, that is to say they have their sides aligned. Similarly, the electrode 15 and a lower part of the dielectric layer 17 are, for example, aligned vertically.
[0037] In the example of [Fig.l], the electrodes 15 and 19 and the layers 23 and 17 are set back relative to the conductive layer 13. In other words, a portion of the upper face of the conductive layer 13 is not covered by the electrodes 15 and 19 and the layers 23 and 17. Thus, in [Fig.l], there is a second step between the upper face of the dielectric layer 17 and the upper face of the lower conductive layer 13. This allows, during a non-detailed manufacturing step, the resumption of an electrical contact on the lower electrode 15 of the capacitor, via the conductive layer 13, for example, by means of a metal wire welded to the upper face of the exposed portion of the layer 13.
[0038] As an example, to form the structure illustrated in [Fig.l], layer 13, electrode 15, layer 17, electrode 19 and layer 23 are first successively deposited on substrate 21. At this stage, layer 13, electrode 15, layer 17, electrode 19 and layer 23 each extend continuously and with a substantially uniform thickness on the upper face of substrate 21. During a first photolithography and etching step, layer 23, electrode 19 and the upper part of dielectric layer 17 are then locally removed, so as to form the first step. During a second photolithography and etching step, the lower part of the dielectric layer 17 and the lower electrode 15 are then locally removed, opposite a part of the surface of the dielectric layer 17 exposed at the end of the first step, so as to form the second step.
[0039] By way of example, the two etching steps are physicochemical plasma etchings carried out using plasmas of different compositions.
[0040] The etching of the stack in two stages allows the etching of the layers 23 and 17 and the electrodes 15 and 19 without the layer 13 being etched. Since the layers 23 and 13 are both, for example, based on aluminum, the upper part of the stack (for example at least the layer 23) is etched using an etching that is non-selective with respect to aluminum and the lower part of the stack (for example at least the electrode 15) is etched using an etching that is selective with respect to aluminum. The conductive layer 23, the electrode 19 and the upper part of the dielectric layer 17 are, for example, etched by a physicochemical etching with chlorine plasma. The electrode 15 and the lower part of the dielectric layer 17 are, for example, etched by a physicochemical etching with fluorine plasma.
[0041] However, during the etching of layer 23, physicochemical etching with chlorine plasma causes the creation of aluminum-based residues which are deposited on the sides of the etched area. These residues are, for example, conductive and can cause a risk of short circuit or breakdown of the capacitor. The first and second steps formed respectively between the upper face of layer 23 and the upper face of layer 17 and between the upper face of layer 17 and the upper face of layer 13 aim to reduce this risk. Indeed, these steps make it possible to introduce a horizontal distance el between the side of layers 23 and 19 and the upper part of layer 17 on the one hand, and the side of the lower part of layer 17 and electrode 15 on the other hand, reducing the risks of malfunction, such as a short circuit, linked to the presence of the residues generated during the first etching step.
[0042] A limitation of the structure of [Fig.l] is that its fabrication involves two photolithography steps to form the first and second steps respectively. This results in a relatively high manufacturing cost.
[0043] [Fig.2], [Fig.3], [Fig.4] and [Fig.5] illustrate successive steps of an example of a method of forming a capacitor according to another embodiment.
[0044] [Fig. 2] illustrates a starting stack comprising, successively, from an upper face of the substrate 21, the first conductive layer 13, the first electrode 15, the dielectric layer 17, the second electrode 19 and the second conductive layer 23.
[0045] Layers 13, 17 and 23 and electrodes 15 and 19 are similar to layers 13, 17 and 23 and electrodes 15 and 19 described in relation to [Fig.l]. In addition, these layers and electrodes are arranged similarly to what has been described in relation to [Fig.l] except that layers 13, 17 and 23 and electrodes 15 and 19 are, at this stage, aligned. In particular, electrodes 15 and 19 and layers 13, 17, 23 each extend above the entire upper surface of substrate 21.
[0046] [Fig. 3] illustrates a structure obtained at the end of a step of forming a masking layer 25 on the upper face of the structure illustrated in [Fig. 2]. By way of example, the masking layer 25 is formed by photolithography.
[0047] For this, the masking layer 25 is, for example, initially formed as a full plate on the upper face of the layer 23, and for example in contact with the latter. The masking layer 25 is, in a second step, for example, exposed locally to light radiation, for example ultraviolet (UV) radiation, through a photolithography mask. After development and rinsing, the layer 25 is kept facing a part of the stack where the capacitor will be formed and removed all around.
[0048] The masking layer 25 is for example made of a resin, for example a photosensitive resin.
[0049] [Fig.4] illustrates a structure obtained at the end of a first step of etching an upper part of the stack of the structure illustrated in [Fig.3].
[0050] During this step, more precisely, an upper part of the stack of layers 23, 19, 17 and 15 is etched through the masking layer 25 by physicochemical etching with chlorine plasma. Even more precisely, during this step, the conductive layer 23, the electrode 19 and an upper part of the dielectric layer 17 are etched through the masking layer 25. For example, during this step, the conductive layer 23, the electrode 19 and an upper part of the layer 17 are removed from the opposite side of the masking layer 25.
[0051] During this step, the physicochemical etching with chlorine plasma is interrupted in the dielectric layer 17.
[0052] Chlorine plasma physicochemical etching is, for example, a vertical anisotropic etching. That is to say, it is directive and is carried out mainly in a single preferred direction, here the vertical direction in the orientation of [Fig.4] (that is to say a direction perpendicular to the upper face of the substrate 21).
[0053] By way of example, the etching step is carried out using a plasma whose pressure is, for example, between 5 mTorr (i.e. 0.67 Pa) and 100 mTorr (i.e. 13.33 Pa), for example between 10 mTorr (i.e. 1.33 Pa) and 50 mTorr (i.e. 6.67 Pa), for example of the order of 15 mTorr (i.e. 2 Pa). During this step, the source power is for example between 100 W and 1800 W, for example between 150 W and 800 W, for example of the order of 400 W. During this step, the polarization power is for example between 20 W and 1000 W, for example between 50 W and 500 W, for example between 150 W and 300 W. During this step, chlorine (Cl2) is for example injected into the plasma source. The flow rate of chlorine is for example between 10 sccm (or cm3.min 1 at 0 °C and under atmospheric pressure) and 500 sccm, for example between 50 sccm and 120 sccm, for example of the order of 80 sccm. During this step, boron trichloride (BC13) is for example injected into the plasma source. For example, during this step, the flow rate of boron trichloride is between 10 sccm and 500 sccm, for example between 20 sccm and 100 sccm, for example of the order of 50 sccm.In this step, boron trichloride and chlorine are, for example, injected into the plasma source. In this step, boron trichloride and chlorine are, for example, injected into the plasma source, for example at the aforementioned flow rates. For example, in this step, the temperature of the lower electrode is between 20°C and 100°C, for example between 30°C and 70°C, for example of the order of 50°C. For example, in this step, the temperature of the upper electrode is between 20°C and 100°C, for example between 50°C and 90°C, for example of the order of 70°C.
[0054] [Fig.5] illustrates a structure obtained at the end of a second etching step of a lower part of the stack of the structure illustrated in [Fig.4].
[0055] The masking layer 25 is not removed at the end of the chlorinated plasma physicochemical etching step described in relation to [Fig. 4], it is in fact retained during the fluorinated plasma physicochemical etching step described in relation to [Fig. 5]. The two physicochemical etching steps are therefore carried out through the same masking layer 25.
[0056] During this step, more precisely, a lower part of the stack of layers 23, 19, 17 and 15 is etched through the masking layer 25 by physicochemical etching with fluorine plasma. Even more precisely, during this step, a lower part of the dielectric layer 17 and the electrode 15 are etched through the masking layer 25. For example, during this step, the lower part of the dielectric layer 17 and the electrode 15 are removed from the face of the masking layer 25.
[0057] The physicochemical etching with fluorine plasma has the advantage of etching the lower part of the dielectric layer 17 and the electrode 15 selectively with respect to the layer 13, containing for example aluminum. During this step, the physicochemical etching with fluorine plasma is therefore interrupted on the upper face of the layer 13 without the latter being etched.
[0058] Physicochemical etching with fluorine plasma is, for example, a vertical anisotropic etching. That is to say, it is directive and is carried out mainly in a single preferred direction, here the vertical direction in the orientation of [Fig.5].
[0059] By way of example, the etching step is carried out using a plasma whose pressure is, for example, between 5 mTorr (i.e. 0.67 Pa) and 100 mTorr (i.e. 13.33 Pa), for example between 5 mTorr (i.e. 0.67 Pa) and 50 mTorr (i.e. 6.67 Pa), for example of the order of 10 mTorr (i.e. 1.33 Pa). During this step, the source power is for example between 100 W and 1800 W, for example between 150 W and 800 W, for example of the order of 500 W. During this step, the polarization power is for example between 20 W and 1000 W, for example between 20 W and 500 W, for example of the order of 50 W. During this step, sulfur hexafluoride (SF6) is for example injected into the plasma source. The flow rate of sulfur hexafluoride is for example between 10 sccm (or cm3.min 1 at 0 °C and under atmospheric pressure) and 500 sccm, for example between 20 sccm and 80 sccm, for example of the order of 50 sccm. During this step, argon (Ar) is for example injected into the plasma source. For example, during this step, the flow rate of argon is between 10 sccm and 500 sccm, for example between 10 sccm and 100 sccm, for example of the order of 20 sccm. During this step, sulfur hexafluoride and argon are for example injected into the plasma source. For example, during this step, sulfur hexafluoride and argon are for example injected into the plasma source at the above-mentioned flow rates. For example, during this step, the temperature of the lower electrode is between 20°C and 100°C, for example between 30°C and 70°C, for example of the order of 50°C.For example, during this step, the temperature of the upper electrode is between 20°C and 100°C, for example between 50°C and 90°C, for example around 70°C.
[0060] As an example, the two physicochemical etching steps using chlorine and fluorine plasma are implemented in two etching devices of the same type.
[0061] The masking layer 25 is removed at the end of the step of etching the lower part of the dielectric layer 17 and the electrode 15 by fluorine plasma.
[0062] The masking layer 25 is, for example, removed during a stripping step. This step corresponds, for example, to a post-discharge plasma physicochemical etching (downstream). For example, this step is carried out in the same etching equipment as the chlorinated plasma physicochemical etching step ([Fig. 4]) and / or the fluorinated plasma etching step ([Fig. 5]). For example, the step of stripping the masking layer 25 is carried out under a pressure, for example, between 300 mTorr (i.e. 40 Pa) and 1200 mTorr. (i.e. 160 Pa), for example between 600 mTorr (i.e. 80 Pa) and 1000 mTorr (i.e. 133.32 Pa), for example between 750 mTorr (i.e. 100 Pa) and 900 mTorr (i.e. 120 Pa). During this step, the RF power is for example between 600 W and 1800 W, for example between 800 W and 1500 W, for example of the order of 1100 W. During this step, oxygen (O2) is for example injected into the plasma source. The oxygen flow rate is, for example, between 500 sccm and 1200 sccm, for example between 700 sccm and 1000 sccm, for example of the order of 810 sccm. During this step, water vapor (H2O) is, for example, injected into the plasma source. The water vapor flow rate is, for example, between 10 sccm and 1000 sccm, for example between 50 sccm and 700 sccm, for example of the order of 90 sccm or of the order of 630 sccm.For example, during this step water vapor and dioxygen are injected into the plasma source. For example, during this step water vapor and dioxygen are injected into the plasma source at the aforementioned flow rates. For example, the stripping step has a duration of between 1 sec and 150 sec, for example between 2 seconds and 120 seconds, for example between 5 seconds and 90 seconds.
[0063] The upper face of the conductive layer 23, the upper face of the layer 13 and the flanks of the layers 23, 17 and 13 and of the electrodes 19 and 15 are, for example, following the stripping step, cleaned. This step makes it possible, for example, to remove the residues, for example polymeric, originating from the masking layer 25 and present on the surface of the conductive layer 23. By way of example, this step also makes it possible to remove the etching residues of the layers 23 and 17 and of the electrodes 19 and 15 formed on the flanks of these same layers and electrodes. This step is for example carried out using a solvent.
[0064] For example, this step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol and hydroxylamine. For example, this step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol, hydroxylamine, pyrocatechol and hydroquinone.
[0065] By way of example, this step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol in a proportion for example of between 35% and 80%, for example of between 55% and 65% and hydroxylamine in a proportion for example of between 2% and 35%, for example of between 10% and 20%. By way of example, this step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol in a proportion for example of between 35% and 80%, for example of between 55% and 65%, of hydroxylamine in a proportion for example of between 2% and 35%, for example of between 10% and 20%, of pyrocatechol in a proportion for example of between 1% and 20%, ... for example between 3% and 10% and hydroquinone in a proportion for example between 0.001% and 1%, for example between 0.01% and 0.1%.
[0066] By way of example, this step is carried out using a solvent of the type marketed under the reference EKC265 by the company Dupont.
[0067] At the end of the method described in relation to FIGS. 3 to 5, the layers 17 and 23 and the electrodes 15 and 19 have their sides substantially aligned vertically.
[0068] It will be noted, however, that, depending on the materials used, the etching speed of the electrodes 15 and 19 may be slightly higher than that of the layers 17 and 23. In this case, at the end of the etching steps, the sides of the electrodes 15 and 19 may have a shrinkage relative to the side of the layers 17 and 23.
[0069] At the end of the method described in relation to figures 2 to 5, a metal pad, not shown, for example made of copper, is for example placed on and in contact with the upper face of the conductive layer 23.
[0070] An advantage of the present embodiment is linked to the choice of etching recipes, the stripping method and the choice of cleaning which make it possible to limit the formation of conductive residues on the sides of the etched area.
[0071] It is thus possible to do without the formation of the steps (guard distance el) described in relation to [Fig.l].
[0072] An advantage is that this makes it possible to reduce the number of steps and thus the manufacturing cost of a capacitor in comparison with a method of the type described in relation to [Fig.l]. In particular, the method described in relation to Figures 2 to 5 comprises a single photolithography step (a single photolithography mask), compared to two in the method described in relation to [Fig.l].
[0073] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, although the chlorinated plasma physicochemical etching has been described as interrupting in layer 17, the physicochemical etching may be interrupted on the upper side of the dielectric layer 17.
[0074] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. A method of manufacturing a capacitor, comprising the following successive steps: a) forming a stack comprising, in order from the upper face of a first conductive layer (13), a first electrode (15), a dielectric layer (17), a second electrode (19) and a second conductive layer (23); b) forming, by photolithography, a masking layer (25) on one face of the second conductive layer (23) opposite the second electrode (19); c) etching, by chlorinated physicochemical plasma etching, through said masking layer, an upper part of the stack, said chlorinated physicochemical plasma etching being interrupted in the dielectric layer (17);d) etching, by fluorinated physicochemical plasma etching, through said masking layer, a lower part of the stack, said fluorinated physicochemical plasma etching being interrupted on the upper face of the first conductive layer (13); and e) removing the masking layer (25) by a stripping process, then cleaning the etched sides by a cleaning process.;
2. The method of claim 1, wherein the first conductive layer (13) is aluminum-based.
3. A method according to claim 1 or 2, wherein the second conductive layer (23) is based on aluminum.
4. Method according to any one of claims 1 to 3, in which during step c), dichlorine and boron trichloride are injected into the plasma source.
5. Method according to claim 4, in which during step c), the dichlorine is injected with a flow rate between 50 sccm and 120 sccm, for example of the order of 80 sccm and the boron trichloride is injected with a flow rate between 20 sccm and 100 sccm, for example of the order of 50 sccm.
6. Method according to any one of claims 1 to 5, in which, during step c), the plasma pressure is between 1.33 Pa and 6.67 Pa, for example of the order of 2 Pa, the source power is between 150 W and 800 W, for example of the order of 400 W and the polarization power is between 50 W and 500 W, for example between 150 W and 300 W.
7. A method according to any one of claims 1 to 6, wherein in step d), sulfur hexafluoride and argon are injected into the plasma source.
8. Method according to claim 7, in which during step d), the sulfur hexafluoride is injected with a flow rate of between 20 sccm and 80 sccm, for example of the order of 50 sccm and the argon is injected with a flow rate of between 10 sccm and 100 sccm, for example of the order of 20 sccm.
9. Method according to any one of claims 1 to 8, in which, during step c), the plasma pressure is between 0.67 Pa and 6.67 Pa, for example of the order of 1.33 Pa, the source power is between 150 W and 800 W, for example of the order of 500 W and the polarization power is between 20 W and 500 W, for example of the order of 50 W.
10. A method according to any one of claims 1 to 9, wherein in step e), the cleaning step comprises cleaning the upper face and flanks of the second conductive layer (23), the flanks of the second electrode (19), the dielectric layer (17), the first electrode (15) and the upper face of the first conductive layer (13).
11. Method according to claim 10, in which the stripping step is carried out by plasma physicochemical etching.
12. The method of claim 11, wherein during the etching step, oxygen and water vapor are injected into the plasma source.
13. Method according to claim 12, in which during the stripping step, the dioxygen is injected with a flow rate of between 700 sccm and 1000 sccm, for example of the order of 810 sccm and water vapor is injected with a flow rate of between 50 sccm and 700 sccm, for example of the order of 90 sccm or of the order of 630 sccm.
14. Method according to any one of claims 11 to 13, wherein during the etching step, the plasma pressure is between 80 Pa and 133.32 Pa, for example between 100 Pa and 120 Pa and the RF power is between 800 W and 1500 W, for example of the order of 1100 W.
15. A method according to any one of claims 10 to 14, wherein the cleaning step is carried out using a solvent based on 2-(2-aminoethoxy)ethanol and hydroxylamine.
16. A method according to claim 15, wherein the proportion of 2-(2-aminoethoxy)ethanol in the solvent is between 55% and 65% and the proportion of hydroxylamine is between 10% and 20%.