Transistor manufacturing process

Abstract

Method for manufacturing a transistor. This description relates to a method for manufacturing a bipolar transistor (12) comprising: a. manufacturing a collector region; b. forming a first layer (54) of a base region material and a second insulating layer (58); c. forming a cavity (62) extending to the collector region; d. forming a portion (24) of the collector region and a portion (66) of the base region within the cavity (62); e. forming a fourth layer (68) of the same material as the second layer (58), having the same thickness as the second layer (58) in the periphery of the bottom of the cavity (62); f. forming an emitter region; g. simultaneously removing the second (58) and fourth (68) layers. Figure for the abstract: Fig. 2D

Description

Description Title of the invention: Method of manufacturing a transistor Technical field

[0001] — This description relates generally to electronic devices and more particularly devices comprising a transistor and methods of making them brication. Prior art

[0002] = A bipolar transistor is a semiconductor-based electronic device of the family of transistors. Its operating principle is based on two PN junctions, one usually direct and the other usually reverse.

[0003] — The operation of bipolar transistors depends on a large number of charac- characteristics of bipolar transistors. One such characteristic of bipolar transistors is their maximum oscillation frequency. Summary of the invention

[0004] There is a need for bipolar transistors having a maximum frequency upper oscillation.

[0005] — An embodiment overcomes all or part of the disadvantages of the electronic devices- known tronics.

[0006] — One embodiment provides a method of manufacturing a bipolar transistor including: a. fabricating a first portion of a collector region in a substrate; b. forming a stack of layers comprising a first layer in a material of a base region and a second insulating layer of a first material c. the formation of a cavity passing through the stack and the substrate so as to reach the first part of the collector region; d. the formation of a second part of the collector region and a first part of the base region in the cavity; e. the formation of a fourth layer of the same material as the second layer, having the same thickness as the second layer in the periphery of the bottom of the cavity; f. the formation of an emitter region opposite the first part of the region of base, the fourth layer being partially uncovered; g. simultaneous removal of the second and fourth layers.

[0007] — According to one embodiment, step a. comprises the formation of an insulating region covering a part of the first part of the collector region, the cavity crossing the insulating region. According to one embodiment, the stack of layers comprises a fifth insulating layer, the first layer, and the second layer located between two sixth insulating layers, the sixth layers being made of materials different from the material of the second layer. According to one embodiment, the second portion of the collector region and the first portion of the base region are formed by epitaxial growth in the cavity. According to one embodiment, step e. comprises forming the fourth layer over the entire structure, forming spacers on the fourth layer against the side walls of the cavity, a central portion of the bottom of the cavity not being covered by the spacers, and etching the portions of the fourth layer not being covered by the spacers. According to one embodiment, the method comprises, between steps f. and g., a step fl. of removing the spacers and the sixth layer covering the second layer. According to one embodiment, step f. comprises forming a seventh layer of the emitter region material and etching the seventh layer so as to partially uncover the fourth layer around the emitter region. According to one embodiment, the method comprises, after step g., a step h. of epitaxial growth of the first layer. According to one embodiment, the method comprises, after step h., a step i. of etching the first layer and the fifth layer, so as to partially uncover the first part of the collector region. According to one embodiment, the method comprises, after step i., forming contact layers on the base, collector and emitter regions. According to one embodiment, the thickness of the second and fourth layers is between 5 nm and 30 nm. Another embodiment provides a device comprising a bipolar transistor in which a contact layer of a base region of the transistor is separated from an emitter region by a portion of the base region and a portion of an insulating layer covered by the emitter region. According to one embodiment, the base region rests on a portion of a collector region of the transistor 12, the horizontal dimensions of the emitter region being less than the horizontal dimensions of the portion of the collector region. According to one embodiment, the horizontal dimensions of the emitter region are less than 180 nm of the horizontal dimensions of the portion of the collector region. Brief description of the drawings These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: [Fig. 1] represents an embodiment of an electronic device; and [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2F], [Fig.2F], [Fig.2G], [Fig.2H], [Fig.21], [Fig.27] represent devices resulting from steps of a manufacturing method of the embodiment of [Fig.1]. Description of the embodiments The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed. Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements. In the following description, when reference is made to absolute position qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative position qualifiers, such as the terms “above”, “below”, “upper”, “lower”, etc., or to orientation qualifiers, such as the terms “horizontal”, “vertical”, etc., reference is made unless otherwise specified to the orientation of the figures. Unless otherwise specified, the expressions 'about', 'approximately', 'substantially', and 'of the order of' mean to within 10%, preferably to within 5%. Unless otherwise specified, the expressions 'insulator' or 'conductor' mean 'electrically insulating' or 'electrically conducting'. [Fig. 1] represents an embodiment of an electronic device 10. More specifically, [Fig. 1] represents an embodiment of an electronic device 10 comprising a bipolar transistor 12. The bipolar transistor 12 is formed in a substrate 14. More specifically, the transistor 12 is formed in the substrate and on an upper face of the substrate 14. The substrate is made of a semiconductor material, for example silicon. The transistor 12 comprises a region 16 of the substrate 14. The region 16 is a buried region of the substrate 14. In other words, the region 16 does not extend to the upper region of the substrate 14. Region 16 is preferably not doped. The transistor 12 further comprises an insulating wall 18. The wall 16 is made of an electrically insulating material, for example silicon oxide. The wall 16 extends into the substrate 14, for example from the upper face. For example, the wall 18 laterally surrounds the region 16. Alternatively, the transistor may comprise several walls 18, the walls 18 laterally delimiting the region 16 on at least some sides. The transistor 12 further comprises regions 20 of substrate 14. The regions 20 are made of a material identical to the region 16. Preferably, the regions 20 have the same doping as the region 16. For example, the regions 20 are not doped. The regions 20 are partially separated from the region 16 by the wall(s) 18. The regions 20 are physically and electrically connected to the region 16 under the wall 18. Thus, the polarization of the region 20 causes the polarization of the region 16. The transistor 12 comprises a conductive layer 21. The layer 21 covers, preferably entirely, preferably only, the upper face of the region 20. The layer 21 is made of an electrically conductive material, for example a metal. The layer 21 corresponds to the contact of the substrate of the transistor 12. The transistor 12 further comprises a region 22 in the substrate 14. The region 22 is located inside the wall 18. The region 22 extends from the upper face of the substrate 14 to the region 16. The region 22 preferably extends along the inner lateral face of the wall 18. The region 22 is therefore preferably in contact with the wall 18. Region 22 is made of the semiconductor material of the substrate 14, for example silicon. Region 22 is doped with a first conductivity type, preferably n-type doped. Region 22 corresponds to a part of the collector of the transistor 12. The transistor 12 comprises a conductive layer 23. The layer 23 covers, preferably entirely, preferably only, the upper face of the region 22. The layer 23 is made of an electrically conductive material, for example a metal. The layer 23 corresponds to the collector contact of the transistor 12. Region 22 laterally surrounds a portion of a region 24 of the transistor 12. Region 24 is located inside the wall 18 and region 22. Region 24 extends from the upper face of region 16 and toward the upper face of the substrate 14. Region 24 preferably extends along the inner lateral face of region 22. Region 22 is therefore preferably in contact with region 24. Region 24 preferably comprises a first portion extending in a plane parallel to the upper face of region 16. The first portion extends throughout the area surrounded by region 22. The first portion extends over region 16. The first portion is therefore in contact with region 16 and with region 22. Region 24 comprises a second portion extending from the upper face of the first portion and extends toward the upper face of the substrate 14. The second part extends for example from the center of the first part. Region 24 is made of the semiconductor material of substrate 14 and region 22, for example silicon. Region 24 is doped with the same conductivity type as region 22, for example the first conductivity type, preferably n-type doped. Region 24 corresponds to another part of the collector of transistor 12. Thus, the collector of transistor 12 comprises regions 22 and 24. Preferably, region 24 has a doping level, i.e. a concentration of dopants of the first type, lower than the doping level, i.e. the concentration of dopants, of region 22. A region 26 laterally surrounds the second part of the region 24. The region 26 is made of an electrically insulating material, for example silicon oxide. The region 26 extends over the first part of the region 24, around the second part of the region 24. The region 26 extends from the upper face of the first part of the region 24 at least to the level of the upper face of the second part of the region 24. Thus, the region 26 extends over the entire height of the second part of the region 24. Preferably, the second part of the region 24 and the region 26 extend to a level higher than the level of the upper face of the region 22. The upper face of the first part of the region 24 is preferably entirely covered by the second part of the region 24 and by the region 26. The region 26 extends, on the external side, that is to say the side furthest from the second part of the region 24, over a greater height than on the internal side. The region 26 thus forms, at its upper face, a step. The assembly comprising the region 26 and the second part of the region 24 therefore comprises a cavity 28, delimited laterally by the region 26, and more precisely by the part of the region 26 having a height greater than the rest of the region 26. The bottom of the cavity 28 is formed by the region 26, and more precisely by the part of the region 26 having the lowest height, and by the upper face of the second part of the region 24. The transistor 12 further comprises a region 30. The region 30 is located in the cavity 28. In other words, the region 30 is located on a part of the region 26 and on the second part of the region 24 and is located inside the wall formed by the part of the region 26 having a greater height. The region 30 preferably comprises a first part corresponding to a layer and a second part 33 extending from the first part so as to form a cavity 31 in the region 30. The bottom of the cavity 31 is formed by the first part of the region 30 and the side walls of the cavity 31 are formed by the second part 33 of the region 30. Preferably, the second part 33 is located in such a way that the region 30 comprises a rim around the part 33. The region 30 preferably completely covers the upper face of the second part of the region 24. The region 30 for example partially covers the upper face of the region 26 located in the cavity 28. The region 30 is preferably located in the center of the cavity 28. The part of the bottom of the cavity 28 covered by the region 30 is surrounded by a part of the bottom of the cavity 28 not being covered by the region 30. Region 30 is for example made of the semiconductor material of substrate 14, for example silicon. Region 30 is doped with a second type of conductivity, i.e. the type of conductivity opposite to the first type of conductivity, preferably doped with p-type. Region 30 corresponds to a part of the base of transistor 12. The transistor 12 comprises a region 32 located in the cavity 28. The region 32 covers the bottom of the cavity 28 not being covered by the region 30. Thus, the region 28 laterally surrounds the first part of the region 30. The bottom of the cavity 38 is thus preferably entirely covered by the regions 30 and 32. The region 32 preferably does not cover the upper face of the region 24. The region 32 has for example the same height as the first part of the region 30. Region 32 is for example made of polycrystalline silicon. Region 32 is doped with the same conductivity type as region 30, i.e. the second conductivity type, i.e. the conductivity type opposite to the first conductivity type, preferably p-type doped. Region 32 corresponds to a part of the base of transistor 12. Regions 30 and 32 thus form the base of transistor 12. Preferably, region 30 has a doping level, i.e. a concentration of dopants of the second type, lower than the doping level, i.e. the concentration of dopants, of region 32. The transistor 12 comprises a conductive layer 34. The layer 34 preferably completely covers the upper face of the region 32. The layer 34 partially covers, for example, the region 30. Thus, the layer 34 rests on the edge of the region 30. The layer 24 is made of an electrically conductive material, for example a metal. The layer 34 corresponds to the contact of the base of the transistor 12. The transistor 12 further comprises a layer 36 located in the cavity 31. In other words, the layer 36 preferably covers entirely the bottom of the cavity 31. In other words, the layer 36 extends over the first part of the region 30, surrounded laterally by the second part 33 of the region 30. The height of the layer 36 is preferably less than the height of the part 33. The layer 36 is for example made of the same material as the substrate 14, for example silicon. The material of the layer 36 is preferably not doped. The transistor 12 comprises an insulating layer 38. The layer 38 is for example made of silicon oxide. Layer 38 extends over a portion of layer 36. Layer 38 extends over the periphery of layer 36. Layer 38 is preferably in contact with portion 33 over the entire contour of cavity 31 and extends towards the center of layer 36. Layer 38 does not entirely cover layer 36. A central portion of layer 36 is not covered by layer 38. Transistor 12 further comprises a region 40. Region 40 covers layer 38 and the central portion of layer 36, i.e. the portion not covered by layer 38. Region 40 is thus in contact with layer 36. The side walls of region 40 are coplanar with the side walls of layers 36 and 38. Thus, the side walls of region 40 are coplanar with the internal side walls of portion 33, i.e. the side walls of portion 33 closest to layer 38. Region 40 is made of polycrystalline silicon. Region 40 is doped with the same conductivity type as regions 22 and 24. Region 40 is, for example, doped with n-type. Region 40 constitutes the emitter of transistor 12. The horizontal dimensions of the emitter region are less than the horizontal dimensions of the portion of the collector region. The horizontal dimensions of the emitter region are less than 180 nm of the horizontal dimensions of the second portion of the collector region. The transistor 12 comprises a conductive layer 42. The layer 42 covers, preferably entirely, preferably only, the upper face of the region 40. The layer 42 is made of an electrically conductive material, for example a metal. The layer 42 corresponds to the contact of the emitter of the transistor 12. The transistor 12 further comprises spacers 44. The spacers 44 extend over the side walls of the region 40, preferably over the entire side walls of the region 40. The spacers 44 preferably extend vertically from the portion 33 to the upper level of the region 40. The spacers preferably extend horizontally from the side walls of the region 40 to the level of the interface between the portion 33 and the layer 34. The extrinsic base resistance is a characteristic of bipolar transistors. The extrinsic base resistance is equal to the multiplication of a resistivity value with the distance between layer 34 and region 40. Thus, in the embodiment of [Fig. 1], the extrinsic base resistance is therefore equal to the multiplication of a resistivity value with the sum of the width of portion 33 and the width of layer 38. The maximum oscillation frequency is such that the higher the extrinsic base resistance, the lower the said frequency and vice versa. Thus, the maximum oscillation frequency of the transistor in [Fig.1] is higher than that of a transistor bipolar comprising regions of additional materials between layer 34 and region 40. [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G], [Fig.2H], [Fig.21], [Fig.27] represent steps, preferably successive, of a method of manufacturing the embodiment of [Fig.1]. [Fig.2A] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, the insulating walls 18 are formed in the substrate 14. The insulating walls 18 thus delimit an area in which the base, the collector and the emitter of the transistor 12 will be formed. The height of the walls 18 is less than the height of the substrate 14. Thus, a portion of the substrate 14 not shown extends under the walls 18. The step of [Fig.2A] further comprises the formation of region 22 and a region 24a corresponding to the first part of region 24 of [Fig.1]. Regions 22 and 24a are for example formed by doping regions of substrate 14. Regions 22 and 24a are preferably doped so as to have the doping levels described in relation to [Fig.1]. The step of [Fig.2A] comprises forming an insulating region 46 in the substrate 14. The region 46 is made of the material of the region 26, for example silicon oxide. The region 46 covers, preferably entirely, preferably only, the region 24a. Thus, the region 46 preferably extends from the upper face of region 24a to the upper level of the substrate 14. The height of the region 46 is such that the region 24a has the height of the first part of the region 24. [Fig.2B] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, elements 48 are formed. The elements 48 preferably completely cover the locations of the layers 20. In other words, the elements 48 cover the upper face of the substrate 14 directly around the walls 18. The elements 48 for example at least partially cover the walls 18. The elements 48 preferably do not cover the regions 22 and the region 46. The elements 48 are for example made of a semiconductor material. The elements 48 are for example made of polycrystalline silicon. The elements 48 are for example made of an undoped material. The step of [Fig.2B] further comprises the formation of a stack 50 of layers. The stack 50 for example completely covers the structure resulting from the formation of the elements 48. In particular, the stack 50 preferably completely covers the elements 48, the portions of the walls 18 not covered by the elements 48, the regions 22 and the region 24a. The stack 50 comprises a lower layer 52. The layer 52 is thus the layer of the stack closest to the substrate 14. The layer 52 conformally covers the structure resulting from the formation of the elements 48. The layer 52 is made of an insulating material, for example the same material as the region 46, for example the same material as the region 26 of [Fig. 1]. The layer 52 is for example made of silicon oxide. The stack 50 comprises a layer 54 covering the layer 52. The layer 54 covers, preferably entirely, preferably conformally, the layer 52. The layer 54 is preferably made of the material of the region 32. The layer 54 is preferably made of polycrystalline silicon. The layer 54 is preferably p-doped. Thus, the layer 54 is preferably made of p-doped polycrystalline silicon. The stack 50 comprises a layer 56 covering the layer 54. The layer 56 covers, preferably entirely, preferably conformally, the layer 54. The layer 56 is made of an insulating material. The layer 56 is made of an insulating material different from the material of the layer 52. The layer 56 is for example made of silicon nitride. The stack 50 comprises a layer 58 covering the layer 56. The layer 58 covers, preferably entirely, preferably conformally, the layer 56. The layer 58 is made of an insulating material. The layer 56 is for example made of the same material as the layer 52. The layer 56 is made of a material different from the material of the layer 56. The layer 56 is for example made of silicon oxide. The layer 58 has a thickness d. The thickness of the layer 58 is for example substantially constant, for example constant. In particular, the thickness of the layer 58 is for example substantially constant, for example constant, at least in the area located opposite the region 46. The stack 50 comprises a layer 60 covering the layer 58. The layer 60 covers, preferably entirely, preferably conformally, the layer 58. The layer 60 is made of an insulating material. The layer 60 is made of an insulating material different from the material of the layer 58. The layer 60 is for example made of the same material as the layer 56. The layer 60 is for example made of silicon nitride. [Fig.2C] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, a cavity 62 is formed. The cavity 62 extends from the upper face of the layer 60 to the upper face of the layer 24a. In other words, the cavity passes through the layers of the stack 50, i.e., the layers 60, 58, 56, 54, 52, as well as the region 46. The cavity 62 is located at the location of the second part of the region 24. Thus, the side walls of the cavity 62 partially correspond to the side walls of the second part of region 24. The step of [Fig.2C] further comprises the formation of the second part of the region 24. In other words, the second part of the region 24 is formed at the bottom of the cavity 62. More precisely, the step of [Fig.2C] comprises the epitaxial growth of the second part of the region 24 from the layer 24a. The epitaxial growth is preferably maintained until the second part of the region 24, that is to say the part formed during this epitaxial growth step, extends to the level of the upper face of the layer 52. The epitaxial growth step results in the consumption of the material of the layer 54 accessible from the cavity 62. Thus, the layer 54 is partially etched from the side walls of the cavity 62. Cavities 64 are thus formed around the cavity 62, at the locations of a part of the layer 54. The height of the cavities 64, corresponding for example to the height of the layer 54, is for example between 5 nm and 20 nm. The depth of the cavities 54, that is to say the distance between the lateral face of the layer 54 forming the bottom of the cavity 54 and the opening of the cavity 54, is between 5 nm and 50 nm. [Fig.2D] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, a region 66 is formed in the cavity 62. The region 66 corresponds to a part of the region 30 of [Fig. 1]. The region 66 is for example formed by epitaxial growth, from the region 24. The region 66 preferably covers entirely the upper face of the part of the region 24 in the cavity 62. The region 66 therefore fills the bottom of the cavity 62 after the formation of the part of the region 24. The region 66 preferably extends from the upper face of the region 24 to the level of the upper face of the layer 54. The region 66 preferably does not extend into the cavities 64. Region 66 is made of the material of region 30 of [Fig. 1]. Thus, region 66 is preferably made of p-type doped silicon. The doping level of region 66 is, for example, substantially equal to the doping level of region 30 of [Fig. 1]. The step of [Fig.2D] further comprises the formation of layer 36. Layer 36 is formed on the upper face of region 66. Layer 36 covers, preferably entirely, preferably only, the upper face of region 66. Layer 36 is for example formed by epitaxial growth. The height of layer 36 is for example less than the thickness of layer 54. Alternatively, region 66 and layer 36 are for example such that the upper face of layer 36 is substantially coplanar with the upper face of layer 56. The step of [Fig.2D] comprises the formation of an insulating layer 68. The layer 68 conformably covers the structure resulting from the formation of the layer 36. Thus, the layer 68 covers the upper face of the layer 60, the side walls of the cavity 62, that is to say the side faces of the layers 60, 58 and 56 located in the cavity 62, and the upper face of the layer 36. The layer 68 is therefore in contact with the side faces of the layers 60, 58 and 56. Layer 68 is made of the same material as layer 58, for example silicon oxide. The material of layer 68 is different from the material of layer 60. The thickness of layer 68 is substantially identical, preferably identical, to the thickness of layer 58. The thickness of layers 58 and 68 is between 5 nm and 30 nm. The step of [Fig.2D] comprises the formation of an insulating layer 70. The layer 70 conformally covers the structure resulting from the formation of the layer 68. Thus, the layer 68 covers, preferably entirely, preferably only, the upper face of the layer 68. Layer 70 is made of a material different from the material of layer 68. Layer 70 is for example made of the same material as layer 60, for example silicon nitride. [Fig.2E] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. The step of [Fig.2E] comprises a step of anisotropic etching of the layer 70. This etching step is preferably configured to etch only the layer 70. This etching step is for example configured not to etch the layer 68. The layer 70 is entirely etched during this etching step, with the exception of spacers 72. The spacers 72 are located at the side walls of the cavity 62. The spacers cover portions 74 of the layer 68 having, in sectional view, an L shape. The spacers 72 do not entirely fill the cavity 62. Thus, a central part of the cavity 62 is not covered by the spacers 72. The step of [Fig.2E] then comprises a step of etching the layer 68. The layer 68 is preferably entirely etched with the exception of the portions 74 covered by the spacers 72. The portions 74 comprise a horizontal part extending, under the spacers 72, on the upper face of the layer 36, from the lateral faces of the cavity 62 towards the center of the cavity 62. The horizontal parts of the portions 74 are such that a part, for example a substantially central part, of the upper face of the layer 36 is not covered by the portions 74. The portions 74 further comprise a vertical part extending on the lateral walls of the cavity 62, for example from the upper face of the layer 36 to the upper face of the layer 60. [Fig.2F] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. The step of [Fig.2F] comprises a step of etching the layer 60 and the spacers 72. The spacers 72 are made of the same material as the layer 60. The spacers 72 and the layer 60 can therefore be etched by the same etching. The etching is for example a wet etching. During this etching step, the vertical part of the portions 74 is at least partially etched. For example, the vertical part of the portions 74 is etched up to the level of the upper face of the layer 68. The layer 58 and the rest of the portions 74 therefore form a layer of constant thickness. The step of [Fig.2F] further comprises the formation of a layer 76 on the structure resulting from the etching of the layer 60 and the portions 74. The layer 76 thus covers, preferably entirely, preferably only, the layer 58, the portions 74 and the portion of the layer 36 not being covered by the portions 74. The layer 76 is made of the material of region 40 of [Fig. 1], that is to say for example n-type doped polycrystalline silicon. The doping of the layer 76 is for example substantially equal, for example equal, to the doping of region 40 of [Fig. 1]. The step of [Fig.2F] further comprises the formation of an insulating layer 78. The layer 78 covers, preferably entirely, preferably only, the layer 76. The layer 78 is made of an insulating material, preferably the same material as the layer 58, for example silicon oxide. [Fig.2G] represents a device resulting from a step of the manufacturing process of the embodiment of |Fig.1]. During this step, layers 76 and 78 are etched so as to form region 40 covered with a portion of layer 78. Layers 76 and 78 are for example etched simultaneously. Layers 76 and 78 are etched in such a way that the side walls of region 40 and the remaining layer 78 are coplanar. Furthermore, layers 76 and 78 are etched in such a way that the side walls of region 40 and remaining layer 78 are located opposite cavity 62, i.e. opposite the second part of region 24, region 66 and layer 36. More precisely, layers 76 and 78 are etched in such a way that the side walls of region 40 and remaining layer 78 are located opposite portions 74. Thus, the portions of layers 76 and 78 located opposite layer 58 are removed. The portions of layers 76 and 78 located opposite the periphery of layer 36, that is to say located opposite the parts of portions 74 closest to layer 58, are etched during this etching step. The portions of layers 76 and 78 located opposite the part of layer 36 not covered by portions 74 and the parts of portions 74 furthest from layer 58 are not etched. during this etching step. Thus, region 40 and the remainder of layer 78 completely cover the part of layer 36 not covered by portions 74 and partially cover portions 74. For example, region 40 and the remainder of layer 78 cover a central part of the assembly comprising portions 74 and layer 36. [Fig.2H] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, the layer 58 and the portions 74 are etched. More precisely, the step of [Fig.2H] comprises a step of etching the material of the layer 58 and the portions 74. This etching step is for example a wet etching. This etching simultaneously removes the layer 58 and the parts of the portions 74 not being located under the region 40. The etching is stopped so as to remove the layer 58 and the portions 74 but not to reach the layer 56 and the layer 36. Layer 58 and portions 74 form a layer of constant thickness. Thus, the etching removes the material from layer 58 and portions 74 at substantially the same rate. The etching of the entire layer 58 and all portions 74 therefore ends at substantially the same time. The material of layer 36 is therefore not etched during the etching of layer 58 and portions 74. It is therefore not necessary to protect layer 36 with region 40. It is possible to reduce the dimensions of region 40 without causing damage to layer 36. [Fig.21] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. During this step, region 40 is encapsulated in a layer 80 of insulating material, preferably the material of layer 78, for example silicon oxide. The layer 80 encapsulating the region 40 comprises the layer 78, the portions 74 and layers 82 covering the side walls of the region 40. The encapsulation layer 80 is preferably located only opposite the layer 36. Thus, the layer 56 is preferably not covered even partially by the layer 80. The step of [Fig.21] further comprises removing layer 56, for example by wet etching. Layer 56 is preferably completely removed. Layer 54 is thus exposed. [Fig.2J] represents a device resulting from a step of the manufacturing process of the embodiment of [Fig.1]. The step of [Fig.2J] comprises a step of epitaxial growth of the layer 54. The epitaxial growth is maintained so that the cavities 64 are filled and the layer 54 reaches at least the location of the region 32 of [Fig.1]. Layer 54 and layer 52 are then etched so as to retain only the portions of layers 52 and 54 located directly around the assembly comprising the region 24, region 66, layer 36, layer 80 and region 40. Layers 52 and 54 are preferably etched so as to retain the portion of layer 54 located at the location of region 32 of [Fig. 1] and the portion of layer 52 located below said portion. The method further comprises additional steps so as to obtain the device of [Fig. 1]. In particular, the method comprises: - removal of the encapsulation layer 80; - the formation of spacers 44 on the side walls of region 40; - the growth of region 66 and the diffusion of charges so as to form region 30; - the formation of conductive layers 21, 23, 34 and 42. An advantage of the described embodiments is that the extrinsic base resistance is lower than that of a known bipolar transistor. The maximum oscillation frequency is therefore higher. Another advantage of the described embodiments is that it is possible to form a smaller emitter region than in a known bipolar transistor. Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing a bipolar transistor (12) comprising: a. the manufacture of a first part (22, 24a) of a region of collector in a substrate (14); b. forming a stack (50) of layers comprising a first layer (54) of a material of a base region and a second insulating layer (58) made of a first material; c. the formation of a cavity (62) passing through the stack (50) and the substrate (14) so ​​as to reach the first part (22, 24a) of the collector region; d. the formation of a second part (24) of the region of collector and a first part (66) of the base region in the cavity (62); and the formation of a fourth layer (68) in the same material than the second layer (58), having the same thickness as the second layer (58) in the periphery of the bottom of the cavity (62); f. the formation of an emitter region (40) opposite the first part (66) of the base region, the fourth layer (58) being partially uncovered; g the simultaneous withdrawal of the second (58) and fourth (68) layers.

2. The method of claim |, wherein step a. comprises the formation of an insulating region (46) covering a portion (24a) of the first part of the collector region, the cavity (62) passing through the insulating region (46).

3. A method according to claim | or 2, wherein the stack of layers comprises a fifth insulating layer (52), the first layer (54), and the second layer (58) located between two sixths insulating layers (6, 60), the sixth layers (56, 60) being in materials different from the material of the second layer (58).

4. A method according to any one of claims 1 to 3, wherein the second part (24) of the collector region and the first part (66) of the base region are formed by epitaxial growth in the cavity (62).

5. A method according to any one of claims 1 to 4, wherein step e. comprises the formation of the fourth layer (68) on the whole structure, the formation of spacers (72) on the fourth layer {68) against the side walls of the cavity (62), a part central part of the bottom of the cavity (62) not being covered by the spacers, and the etching of the portions of the fourth layer (68) not being not covered by the spacers (72).

6. A method according to claim 5 as it relates to the resale- indication 3, comprising, between steps f. and g., a withdrawal step fl. spacers (72) and the sixth layer (60) covering the second layer.

7. A method according to any one of claims 1 to 6, wherein step f. includes the formation of a seventh layer in the material of the emitter region and etching the seventh layer so as to partially uncover the fourth layer (68) around the region transmitter (40).

8. A method according to any one of claims 1 to 7, comprising, after step g., a step h. of epitaxial growth of the first layer (54).

9. A method according to claims 3 and 8, comprising, after step h., a step 1. etching of the first layer (54) and the fifth layer (52), so as to partially uncover the first part (22, 24a) of the collector region.

10. A method according to claim 9, comprising, after step i., the formation of contact layers (23, 34, 42) on the base regions, collector and emitter.

11. A method according to any one of claims 1 to 10, wherein the thickness of the second and fourth layers (58, 68) is included between 5 nm and 30 nm.

12. Device obtained by a method according to any one of the claims- indications 1 to 11, comprising a bipolar transistor (12) in which a contact layer (34) of a base region of the transistor (12) is separated from an emitter region by a portion (33) of the base region and a portion (38) of insulating layer covered by the region transmitter (40).

13. A device according to claim 12, wherein the base region (30) rests on a part of a collector region of transistor 12, the di- horizontal dimensions of the emitter region being less than the di- horizontal dimensions of the portion of the collector region.

14. The device of claim 13, wherein the horizontal dimensions zontals of the emitter region are less than 180 nm from the di- horizontal dimensions of the part of the collector region.