Electronic device

Abstract

Electronic Device This description relates to an interposer (12) comprising capacitors (32) having a density greater than 700 nF / mm², advantageously greater than 1 µF / mm², the interposer being adapted to be attached to a chip (14) by hybrid bonding. Figure for the abstract: Fig. 1

Description

Title of the invention: Electronic device technical field

[0001] This description relates generally to electronic devices and more particularly to devices comprising a chip and an interposer. Prior art

[0002] Electronic devices often include interposers, allowing electrical connections to be formed between a main chip, fixed on one side of the interposer, and one or more secondary chips, fixed on a second side of the interposer.

[0003] The main chip is, for example, an integrated circuit. The secondary chips include, for example, discrete components or circuits associated with the integrated circuit, for example to allow the integrated circuit to perform functions that cannot be performed by the main chip.

[0004] Interposers generally consist of a layer, for example, of an electrically insulating material, conductive vias, and one or more conductive traces for forming routing levels for interconnections. The interposer includes, for example, contact pads on its first and second sides, the contact pads being connected to contact pads on the primary and secondary chips, for example, by solder balls. Such a connection also allows the chips to be fixed to the interposer.

[0005] There is a need to place capacitors in the interposers in order to optimize the power supply to the various secondary chips. In particular, there is a need to significantly reduce the parasitic equivalent inductances (ESR) and equivalent resistances (ESR) in order to greatly increase the efficiency of the capacitors. Conventionally, capacitors, for example discrete capacitors, are connected to an active chip by wire connections or by metal balls with dimensions on the order of micrometers. These connections themselves generate parasitic inductances (5 to 100 pF) and / or resistances (20-100 mOhms). These parasitic inductances or resistances are equivalent to, or even exceed, the parasitic inductances or resistances of very high-performance capacitors (1 pF / mm²). Summary of the invention

[0006] There is a need to connect very high performance capacitors with others without degrading their intrinsic performance with connection interference.

[0007] One embodiment provides an interposer comprising capacitors having a density greater than 700 nF / mmA2, advantageously greater than 1 pF / mmA2, the interposer being adapted to be fixed to a chip by hybrid bonding.

[0008] According to one embodiment, the interposer comprises: a substrate through which first conductive vias pass; a first layer, covering the substrate, in which the capacitors are located; and an interconnection network comprising contact pads adapted for molecular bonding.

[0009] According to one embodiment, the first vias have a diameter between 5 pm and 20 pm, advantageously substantially equal to 10 pm, and a height between 50 pm and 200 pm, advantageously substantially equal to 100 pm.

[0010] According to one embodiment, the first layer comprises first conductive regions, each first region being in contact with an end of a first via, and being connected to a contact pad by conductive vias and conductive tracks of the interconnection network.

[0011] According to one embodiment, the first regions are surrounded laterally by second insulating regions.

[0012] According to one embodiment, the interposer comprises: third regions in which the capacitors are located, fourth insulating regions, each capacitor being surrounded laterally by a fourth insulating region, fifth conductive regions, each fifth region being separated from a third region by a fourth region, and sixth conductive regions, each sixth region connecting a terminal of a capacitor to a fifth region, each fifth region being connected to a contact pad by second conductive vias and conductive tracks of the interconnection network, another terminal of each capacitor being connected to a contact pad by second conductive vias and conductive tracks of the interconnection network.

[0013] According to one embodiment, each insulating region of the first layer is made of an anodized metal.

[0014] According to one embodiment, the capacitors comprise a stack of a second conductive layer, a third insulating layer, a fourth conductive layer, each third region being in an anodized metal comprising a plurality of cavities through said metal, the stack covering the walls of said cavities.

[0015] According to one embodiment, the interposer comprises, in at least one zone, a density of studs greater than 10A3 studs per mmA2.

[0016] Another embodiment provides a device comprising an interposer as described above and at least one first chip fixed to a first face of the interposer, at least one first chip being fixed to the first face by molecular bonding.

[0017] According to one embodiment, the formation of the capacitor comprises: - the formation of a fifth layer in a conductive material; - the formation of cavities at the location of the capacitor in the fifth layer by an anodic etching process; and - the conformal formation of a stack of a conductive layer, an insulating layer and a conductive layer at the location of the capacitor.

[0018] According to one embodiment, the formation of the insulating regions of the first layer is obtained by an anodic etching process of a part of the fifth layer.

[0019] According to one embodiment, the method comprises: - the formation of the first vias in the substrate; - the formation of a seventh conductive region extending from the location of each third region to the location of the corresponding fifth region; - the formation of the capacitor, such that one terminal of the capacitor is in contact with the seventh region.

[0020] According to one embodiment, the fifth layer is made of aluminum. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1] schematically represents an embodiment of an electronic device;

[0023] [Fig.2] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig.1];

[0024] [Fig.3] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig.1];

[0025] [Fig.4] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig.1];

[0026] [Fig. 5] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig. 1]; and

[0027] [Fig.6] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig.1]. Description of the implementation methods

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the Different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0033] Unless otherwise specified, the terms "insulating" and "conducting" mean "electrically insulating" and "electrically conducting".

[0034] Fig. 1 schematically represents an embodiment of an electronic device 10.

[0035] The device 10 includes an interposer 12. The device 10 further includes a chip 14 fixed to an upper face 16 of the interposer 12. Although, in [Fig. 1], only one chip 14 is shown, the device 10 can include a plurality of chips 14 fixed to the face 16 of the interposer 12. The interposer 12 includes a lower face 18, opposite the face 16. The face 18 is fixed to a chip, for example a single chip (not shown) or to a ball grid array (BGA) substrate. The face 18 and the chip (not shown) are, for example, fixed to each other by solder balls (not shown).

[0036] The interposer comprises a layer 20 made of an insulating material. The layer 20 is, for example, made of a resin. The layer 20 is, for example, made of silicon oxide. The layer 20 is, for example, made of a semiconductor material, for example, silicon. The layer 20 is traversed by through-vias 22. The vias 22 are conductive vias. The vias 22 are made of a conductive material, for example, metal. The vias 22 extend from an upper face 23 of the layer 20 to the lower face of the layer 20, corresponding, for example, to the face 18 of the interposer. In other words, the vias 22 extend over the entire height of the layer 20. The vias 22 have, for example, a diameter between 5 pm and 20 pm, advantageously substantially equal to 10 pm, and a height for example between 50 pm and 200 pm, advantageously substantially equal to 100 pm.

[0037] Each via 22 corresponds, for example, to a connection between the interposer 12 and the unshown chip to which the interposer is connected. The interposer 12 includes, for example, at least as many vias 22 as there are desired connections between the interposer and the unshown chip. The interposer 12 includes, for example, at least as many vias 22 as there are desired connections between the chips 14 and the unshown chip.

[0038] The interposer 12 comprises a layer 24 made of an anodizable conductive material, preferably a metal. The layer 24 is, for example, made of aluminum, magnesium, or tantalum.

[0039] Layer 24 comprises regions 26. The regions 26 are conductive regions. The regions 26 are located opposite the vias 22. The regions 26 extend over the entire height of layer 24. The regions 26 therefore extend from the upper face of layer 20 to the upper face of layer 24. Each region 26 is in contact with an upper end of a via 22, that is, in contact with the end of a via 22 that is flush with the upper face of layer 20. Each region 26 allows the electrical connection of the via 22 with which the region 26 is in contact to continue.

[0040] Regions 26 are surrounded by regions 28 of layer 24. Regions 28 are insulating regions. Regions 28 are made of the material of layer 24, for example aluminum, having been anodized, for example alumina. Regions 28 are thus porous regions. In other words, regions 28 comprise a plurality of cavities, or nanopores, not shown, extending, for example, over the entire height of region 28.

[0041] The layer 24 further comprises regions 30, in which capacitors 32 are located. Each region 30 comprises, for example, a single capacitor 32. The capacitors 32 are high-density capacitors, that is to say, capacitors having a density greater than 700 nF / mmA2, for example greater than 1 pF / mmA2.

[0042] Regions 30, like regions 28, are made of the same material as layer 24, for example, anodized aluminum, for example, alumina. Regions 30 thus comprise a plurality of cavities (not shown), extending, for example, over the entire height of region 30. The cavity density in region 30 is, for example, greater than 40 cavities / pmA2.

[0043] The capacitors 32 are Metal-insulator-metal or MIM capacitors. Each capacitor 32 comprises a stack of layers not shown in [Fig.1], of an insulating layer located between two conductive layers, preferably made of metal. The stacking of layers of a capacitor 32 is located conformally on the porous structure of the region 30.

[0044] A lower layer of the capacitor stack 32, that is, one of the conductive layers, preferably a metallic layer, conforms to the porous structure, and in particular within the cavities of region 30. The lower layer of a capacitor 32 preferably completely covers the upper surface of layer 24 in region 30, the lateral walls of the cavities, and the bottom of the cavities. The lower layer of a capacitor 32 is thus flush with the lower surface of layer 24.

[0045] An intermediate layer of the capacitor stack 32, i.e. the insulating layer, extends conformally over the lower layer. The intermediate layer extends into the cavities. The intermediate layer preferably completely covers the lower layer.

[0046] An upper layer of the capacitor stack 32, i.e., the other conductive layer, for example made of metal, extends conformally over the intermediate layer. The upper layer extends into the cavities. The upper layer fills the cavities, for example. The upper layer preferably completely covers the intermediate layer. The upper layer includes, for example, a flat upper surface extending over the upper surface of the porous structure.

[0047] The layer 24 further comprises insulating regions 34 delimiting the regions 30. Each region 30 is surrounded by regions 34. Each region 30 is thus laterally isolated from the rest of the layer 24. Each region 30 is preferably in direct lateral contact with the regions 34. Thus, the regions 30 are preferably not separated from the regions 34 by other regions of the layer 24. In particular, the regions 30 are preferably not separated from the regions 34 by regions of the material of the layer 24 that have not been anodized and are not porous.

[0048] Regions 34 are insulating regions. Regions 34 are made of the same material as layer 24, for example, anodized aluminum, for example, alumina. Regions 34 are thus porous regions. In other words, regions 34 comprise a plurality of cavities (not shown), extending, for example, over the entire height of region 34.

[0049] The layer 24 further comprises conductive regions 36. The regions 36 are regions of the material of the layer 24 that have not been anodized and are not porous. Each region 36 extends over the entire height of the layer 24. Thus, each region 36 extends from the lower face of the layer 24 to the upper face of the layer 24. Each region 36 is laterally surrounded by regions 28 and / or 34. Preferably, the layer 24 comprises at least as many regions 36 as capacitors 32. Preferably, a region 36 is adjacent to each region 30, the regions 30 and The 36s are preferably separated only by a region 34. The lower face of each region 30, that is, the lower layer of each capacitor 32, is electrically connected to a region 36, preferably the adjacent region 36. Thus, one terminal of the capacitor 32 in each region 30 is connected, via the layer 36, to the upper face of the layer 24.

[0050] In the schematic example of [Fig. 1], the lower face of each region 30 is connected to the region 36 by a conductive region 37 located in the layer 20. Alternatively, the lower face of each region 30 can be connected to the region 36 by a conductive region 37, different from the region 37 shown in [Fig. 1], extending, in the layer 24, under the regions 30, 34, and 36, so as to be in contact with the lower layer of the capacitor 32 of the region 30 and with a lower end of the adjacent region 36. Such a layer 37 is, for example, at least partially, for example entirely, made of the same material as the regions 26. Such a structure will be described in more detail with reference to Figures 2 to 6.

[0051] The interposer 12 further comprises an interconnection network 35. In other words, the interposer 12 comprises a stack 35 of insulating layers 38, in which conductive tracks 40 and conductive vias 42 are located. The network 35 is located on the upper face of the layer 24. In other words, the network 35 is separated from the layer 20 by the layer 24.

[0052] The upper layer of the stack 35, i.e., the layer furthest from layer 24, comprises studs 44 for enabling molecular bonding of the interposer 12 to the chip 14. The studs 44 are flush with the upper face of the stack 35. The studs 44 also enable electrical connection between the interposer 12 and the chip 14, and thus electrical connection between the chip 14 and a chip (not shown) attached to the face 18 of the interposer. The studs 44 further enable connection between two adjacent chips 14. Preferably, the upper face of the interposer comprises, over at least a portion of its surface, a stud density 44 greater than 10³ / mm².

[0053] Each region 26 is connected to a pad 44 by one or more tracks 40 and one or more vias. Thus, connections are made between the upper face 16 of the interposer and the lower face 18 of the interposer, via a via 22, a region 26, tracks 40 and vias 42, and a pad 44.

[0054] Similarly, each terminal of each capacitor 32, that is, each of the two conductive layers surrounding the insulating layer of each capacitor 32, is connected to a pad 44. Thus, the upper layer of each capacitor 32 is connected to a pad 44 via tracks 40 and vias 42. The lower layer of each capacitor 32 is connected to a pad 44 via a region 37, a region 36, tracks 40 and vias 42.

[0055] The chip 14 includes a main part 46, for example a semiconductor substrate in which electronic components are formed, for example transistors, for example insulated gate field effect transistors (MOSFET or Metal Oxide Semiconductor Field Effect Transistor).

[0056] The chip 14 further includes an interconnection network 48. In other words, the chip 14 includes a stack 48 of insulating layers 50, in which are located conductive tracks, not shown, and conductive vias 54. The network 48 is located on a lower face 56 of the part 46.

[0057] The lower layer of the stack 48, i.e. the layer furthest from the part 46, includes pads 58 intended to allow the molecular bonding of the interposer 12 to the chip 14. The pads 58 are flush with the lower face of the stack 48. The pads 58 also allow the electrical connection between the interposer 12 and the chip 14, and therefore the electrical connection between the chip 14 and a chip not shown attached to the face 18 of the interposer.

[0058] The interposer 12 and the chip 14 are fixed to each other by molecular bonding. More specifically, face 56 of the chip 14 is fixed by molecular bonding to face 16 of the interposer 12.

[0059] Figures 2 to 6 represent steps, preferably successive, of a method for manufacturing an embodiment of an electronic device of the type of the device in [Fig. 1]. More specifically, Figures 2 to 6 represent the formation of a part of an embodiment of an electronic device of the type of the device in [Fig. 1] comprising a via 22, a region 26, a region 28, a region 36, a region 24, two regions 34, a part of the network 35 and a part of the chip 14.

[0060] Fig. 2 represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in Fig. 1.

[0061] During this step, an insulating layer 60 is formed on the layer 20. More precisely, the layer 60 is formed on the face 23 of the layer 20. The layer 60 covers, for example, the entire face 23 of the layer 20. The layer 20 is, for example, made of silicon. The layer 60 is, for example, made of silicon oxide.

[0062] The step in [Fig. 2] further includes the formation of the vias 22. The vias 22 pass through layer 60 and layer 20. More precisely, the vias extend from the lower face 18 of layer 20 to the upper layer of layer 60, i.e., the face of layer 60 furthest from layer 20. For example, the formation of the vias includes etching cavities through layer 60 and partially through layer 20, filling the cavities with the conductive material of the vias 22, and thinning layer 20 through the lower face 18 so as to expose the lower faces of the vias 22.

[0063] [Fig.3] represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in [Fig.1].

[0064] During this step, a layer 62 of a conductive material is formed. The layer 62 is, for example, made of a metal, for example, the material of layer 24, more specifically the material of region 26, for example, aluminum. The layer 62 comprises first portions 62a and second portions 62b.

[0065] Each portion 62a, only one of which is shown in [Fig.3], is located opposite a via 22, and in contact with said via 22. Each portion 62a thus covers the upper face of a via 22 and the upper face of the layer 62 located around the upper face of said via 22.

[0066] Each portion 62b, only one of which is shown in [Fig.3], is located opposite the location of a capacitor 32 and a region 36. Each portion 62b covers, preferably only, and is in contact with the layer 60. Each portion 62b corresponds to a region 37, that is to say a conductive region in contact with the terminal of the capacitor closest to the layer 20.

[0067] Each portion 62a, 62b of the layer 62 is covered by a conductive layer 64. The layer 64 is, for example, made of metal, for example, a stack of titanium nitride, titanium and aluminum layers, or tungsten. The upper and lateral faces of each portion 62a, 62b are covered by a layer 64. For example, each layer 64 partially covers the upper face of the layer 60 located between the different portions 62a, 62b. At least a portion of the upper face of the layer 60 located between the different portions 62a, 62b is not covered by a layer 64. The layers 64 covering different portions 62a, 62b are therefore not in contact with each other.

[0068] The portions 62a, 62b are separated from each other by insulating portions 66, for example made of silicon oxide. Each region 66 is located opposite the location of a region 28.

[0069] The portions 66 preferably completely fill cavities located between portions 62a, 62b and between layers 64. The portions 66 thus cover the parts of layers 64 covering the lateral walls of portions 62a, 62b and the parts of layers 64 covering the upper face of layer 60. The portions 66 also cover the parts of layer 60 located between layers 64, that is to say, the parts of layer 60 not covered by portions 62a, 62b or by layers 64. The portions 62a, 62b are thus electrically insulated from each other.

[0070] Preferably, the upper face of the structure resulting from the step in [Fig. 3] is planar. In other words, the upper faces of the regions 66 and the upper faces of the parts of the layers 64 located on the upper faces of the portions 62a, 62b are substantially coplanar.

[0071] Fig. 4 represents a step in a manufacturing process for an embodiment of an electronic device of the type of the device in Fig. 1.

[0072] During this step, layer 24 is formed. More precisely, a layer 68 made of the material of region 26 is formed on the structure resulting from step [Fig. 3]. In other words, layer 68 preferably covers entirely the upper faces of regions 66 and the upper faces of the parts of layers 64 located on the upper faces of portions 62a, 62b.

[0073] Layer 68 is made of a conductive material. Layer 68 is a complete and continuous layer. Preferably, layer 68 does not contain any cavities during its deposition. Preferably, the lower and upper faces of layer 68, i.e., the layer closest to layer 20 and the layer furthest from layer 20, are flat and parallel. Layer 68 is, for example, made of aluminum.

[0074] The step in [Fig. 4] further includes the formation of nanopores in the regions 28, 30 and 34 of layer 68. For clarity, the nanopores of regions 28 and 34 are not shown in figures 4, 5 and 6, and only four nanopores are shown in region 30 of figures 4, 5 and 6.

[0075] The nanopores are formed in regions 28, 30, and 34. The portions of layer 68 corresponding to regions 28, 30, and 34 undergo an anodic etching process, resulting in a nanostructured metal layer. The anodic etching process is, for example, preceded by mask formation on layer 68 outside the locations of regions 28, 30, and 34.

[0076] Anodizing, or the anodic etching process, is an electrolytic process carried out in a wet environment. The principle is based on the application of an imposed potential difference between two conductive electrodes immersed in an electrolytic solution, which may, for example, be acidic. In the example of the process shown in Figures 2 to 6, one of the conductive electrodes, for example the anode, is layer 68. Applying a potential to an electrode induces the growth of alumina on its surface if the electrode is made of aluminum. The dissolution of the aluminum electrode in the acid bath causes the formation of nanopores or cavities on the electrode surface.

[0077] The nanopores advantageously have, for example, a diameter of approximately 80 nm and are spaced 50 nm apart. The nanopore density is, for example, approximately 40 cavities / pm². Furthermore, the anodizing process used allows for the production of nanopores opening onto layer 64. In other words, the nanopores can be considered as nano-cylinders, one end of which opens onto layer 64.

[0078] The process of [Fig. 4] further comprises the formation of the stack of layers of the capacitor 32. More specifically, the capacitor 32 comprises a stack of a conductive layer 70, an insulating layer 72 and a conductive layer 74 formed in a conformal manner in region 30, as described in relation to [Fig.1].

[0079] Thus, layer 70, corresponding to the bottom layer of the capacitor stack 32, preferably a metallic layer, conforms to the nanopore structure, and in particular within the nanopores of region 30. The bottom layer of capacitor 32 preferably completely covers the upper face of layer 24 in region 30, the lateral walls of the nanopores, and the bottom of the nanopores. The bottom layer of capacitor 32 is therefore flush with the lower face of layer 24. The bottom layer of capacitor 32 is thus electrically connected, preferably in contact, with layer 64 located beneath capacitor 32.

[0080] Layer 72, corresponding to the intermediate layer of the capacitor stack 32, extends conformally over layer 70. Layer 72 extends into the nanopores. The intermediate layer preferably completely covers layer 70.

[0081] Layer 74, corresponding to the top layer of the capacitor stack 32, for example made of metal, extends conformally over layer 72. Layer 74 extends into the nanopores. Layer 74 fills the nanopores, for example. Layer 74 preferably completely covers layer 72. Layer 74 comprises, for example, a flat upper surface extending over the upper surface of the nanopore structure.

[0082] The step in [Fig. 4] preferably comprises the formation of a conductive region 76 covering the layer 74. The region 76 is, for example, made of metal. The region 76 preferably completely covers the upper surface of the layer 74. The region 76, for example, partially covers the regions 34 surrounding the region 30. The region 76 is not in contact with the neighboring regions 36. At this stage, the region 76 is electrically connected only to the layer 74.

[0083] The step in [Fig. 4] includes, for example, the formation of regions 78, each preferably located exclusively on regions 26 and 36. The regions 78 are preferably made of the same material as regions 26 and 36, for example, aluminum. The regions 78 are in contact with regions 26 and 36, on which they rest.

[0084] The step in [Fig. 4] includes, for example, the formation of an insulating layer 80. The layer 80 preferably covers the entire structure. The layer 80 thus covers the upper face of region 28, the upper and lateral faces of regions 76 and 78, and the portions of the upper faces of regions 26, 34, and 36 not covered by regions 76 and 78.

[0085] The process for forming capacitor 32 is described in more detail in documents WO2015 / 063420 and EP3680931.

[0086] Figure 5 represents a step in a manufacturing process of an embodiment of an electronic device of the type of the device in [Fig.1].

[0087] During this step, the interconnection network 35 is formed on the upper face of the interposer, i.e. the face opposite to the face 18. The formation of the interconnection network is for example preceded by the thinning of the layer 80 so as to expose the upper faces of the regions 76 and 78.

[0088] The interconnection network 35 is for example formed by a Damascus process. In other words, the formation of the interconnection network 35 includes, for each layer of the stack, the formation of the insulating layer, the etching of the insulating layer at the locations of the vias 42, the tracks 40 and the studs 44, the formation of a conductive layer on the insulating layer so as to fill the etched locations, and the removal of the portions of the conductive layer located outside the etched locations.

[0089] Figure 6 represents a step in a manufacturing process of an embodiment of an electronic device of the type of the device in [Fig.1].

[0090] During this step, the interposer 12 is attached to a chip 14. The chip 14 is, for example, formed in parallel with the fabrication of the interposer. The formation of the chip 14 includes the formation of electronic components in a semiconductor substrate 46. The formation of the chip 14 further includes the formation of the interconnect network 48, i.e., the formation of the insulating layers 50, the conductive traces, the vias 54, and the pads 58.

[0091] The pads 58 are positioned so as to be in contact with the pads 44 of the interposer 12 when the chip 14 and the interposer are attached to each other. The contact between the pads 58 and 44 enables the electrical connection between the chip 14 and the interposer 12 and allows molecular bonding between the chip 14 and the interposer 12.

[0092] The manufacturing process of the device 10 of [Fig.1] further includes manufacturing the main chip not shown, or the BGA substrate not shown, and attaching it to the face 18 of the interposer so as to be electrically connected to the interposer, and more particularly to the lower ends of the vias 22.

[0093] Electrical connections can thus be made between the lower face 18 of the interposer and the upper face 16 of the interposer, i.e. between the main chip not shown and the chip 14, each connection being made via a via 22, a portion 62a, a layer 64, a region 26, a region 78, tracks 40, vias 42 and a pad 44.

[0094] Chip 14 is further connected to the terminals of capacitor 32. One terminal of capacitor 32, corresponding to layer 70, is connected to chip 14 via layer 64, portion 62b, region 36, region 78, vias 42, traces 40, and pad 44. Another terminal of capacitor 32, corresponding to layer 74, is connected to chip 14 via a region 76, vias 42, tracks 40, a pad 44, and possibly a routing level at the bottom face of the interposer.

[0095] One advantage of the described embodiments is the possibility of obtaining high density capacities in an interposer, which allows for optimization of power transfer.

[0096] Another advantage of the described embodiments is that the capacitors are particularly close to the electronic components of the chips fixed to the top face of the interposer.

[0097] Another advantage of the described embodiments is the high interconnection density between the interposer and the chips attached to the top face of the interposer. Indeed, using the pads of an interconnection network to form connections with the chips and to fix the chips and the interposer by molecular bonding allows the addition of the bonds corresponding to the capacitors without increasing the size of the interposer.

[0098] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0099] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Interposer (12) comprising capacitors (32) having a density greater than 700 nF / mmA2, advantageously greater than 1 pF / mmA2, the interposer being adapted to be attached to a chip (14) by hybrid bonding, the interposer comprising: a substrate (20) traversed by first conductive vias (22); a first layer (24), covering the substrate (20), in which the capacitors (32) are located; and an interconnection network (35) comprising contact pads (44) adapted for molecular bonding, the first layer (24) comprising first conductive regions (26), each first region (26) being in contact with an end of a first via (22), and being connected to a contact pad (44) by conductive vias (42) and conductive tracks (40) of the interconnection network (35).

2. Interposer according to claim 1, wherein the first vias (22) have a diameter between 5 pm and 20 pm, advantageously substantially equal to 10 pm, and a height between 50 pm and 200 pm, advantageously substantially equal to 100 pm.

3. Interposer according to claim 1 or 2, wherein the first regions (26) are laterally surrounded by second insulating regions (28).

4. An interposer according to any one of claims 1 to 3, wherein the interposer comprises: third regions (30) in which the capacitors (32) are located; fourth insulating regions (34), each capacitor (32) being laterally surrounded by a fourth insulating region (34); fifth conductive regions (26), each fifth region (26) being separated from one of the third regions (30) by one of the fourth regions (34); and sixth conductive regions (37), each sixth region (37) connecting a terminal of one of the capacitors (32) to a fifth region (26), each fifth region (26) being connected to a contact pad (44) by second conductive vias (42) and conductive tracks (40) of the interconnection network, another terminal of each capacitor (32) being connected to a contact pad (44) by of the second conductive vias (42) and conductive tracks (40) of the interconnection network.

5. Interposer according to claim 3 or 4, wherein each insulating region (28, 34) of the first layer is made of an anodized metal.

6. Interposer according to claim 4, wherein the capacitors (32) comprise a stack of a second conductive layer (70), a third insulating layer (72), a fourth conductive layer (74), each third region (30) being of an anodized metal comprising a plurality of cavities through said metal, the stack (70, 72, 74) covering the walls of said cavities.

7. Interposer according to any one of claims 1 to 6, wherein the interposer (12) comprises, in at least one area, a stud density (44) greater than 10A3 studs per mmA2.

8. Device comprising an interposer (12) as described according to any one of claims 1 to 7 and at least a first chip (14) attached to a first face (16) of the interposer, the at least a first chip (14) being attached to the first face (16) by molecular bonding.

9. A method for manufacturing an interposer according to any one of claims 1 to 7, wherein the formation of each capacitor (32) comprises: - the formation of a fifth layer (68) in a conductive material; - the formation of cavities at the location of the capacitor (32) in the fifth layer (68) by an anodic etching process; and - the conforming formation of a stack of a conductive layer (70), an insulating layer (72) and a conductive layer (74) at the location of the capacitor (32).

10. A method according to claim 9, wherein the formation of the insulating regions of the first layer is obtained by an anodic etching process of a part of the fifth layer.

11. A method according to claim 9 or 10 in relation to claims 2 and 6, wherein the method comprises: - the formation of the first vias (22) in the substrate (20); - the formation of a seventh conductive region (37) extending from the location of each third region (30) to the location of the corresponding fifth region (36); 16 - the formation of each capacitor (32), in such a way that one terminal of each capacitor is in contact with the seventh region (37).

12. A method according to any one of claims 9 to 11, wherein the fifth layer (68) is made of aluminum.