COMPUTER SYSTEM AND METHOD FOR TRANSMITTING DATA BETWEEN A MEMORY AND A PERIPHERAL

Abstract

According to one aspect, a computer system is proposed comprising: - a central processing unit (CPU), - a peripheral (PRPH) configured to process data in a first format, - a memory (MEM) configured to store data intended for the peripheral, the data in a second format distinct from the first format, - a direct memory access (DMA) controller configured to, during a data transmission from the memory (MEM) to the peripheral (PRPH): ○ retrieve data intended for the peripheral (PRPH) and stored in memory (MEM), then ○ modify the format of the retrieved data to obtain data in said first format, then ○ transmit the data in said first format to the peripheral (PRPH),The central processing unit (CPU) is configured to initiate a data transmission from memory (MEM) to the peripheral (PRPH) via the direct memory access (DMA) controller. Figure for the abbreviation: Figure 1,

Description

Title of the invention: COMPUTER SYSTEM AND METHOD FOR TRANSMITTING DATA BETWEEN A MEMORY AND A PERIPHERAL

[0001] Embodiments and implementation methods relate to computer systems, in particular systems on a chip.

[0002] A computer system may include a central processing unit, a memory and at least one peripheral device.

[0003] For example, the computer system may include an encryption / decryption circuit as a peripheral device. The encryption / decryption circuit may, in particular, be configured to perform encryption / decryption according to the "AES" standard (acronym for "Advanced Encryption Standard"). Such an encryption / decryption circuit may, in particular, use the "AES-CCM" mode (in English, "Counter with Cipher Block Chaining-Message Authentication Code").

[0004] The "AES-CCM" encryption / decryption method allows for the encryption / decryption of a digital message and uses an authentication tag calculated from a prefix and header data associated with that digital message. The authentication tag authenticates the integrity of the encrypted message to which it is associated. The header data includes user-defined information. The prefix includes information about the header length, specifically encrypted according to NIST Special Publication 800-38C. The prefix size can vary depending on the header length. For example, the prefix can be encoded in two, six, or ten bytes.

[0005] The computer system device may require receiving data in a defined format. This format may differ from the format of the data stored in memory. Thus, the data stored in memory cannot be directly transmitted to the device.

[0006] In particular, when the device is an "AES-CCM" type encryption-decryption circuit, the device requires receiving the prefix and header data in a given format. This format is generally different from the one used to store this prefix and header data in memory.

[0007] More specifically, the encryption-decryption circuit may require concatenating the prefix with the header data, whereas the memory may be configured to store the prefix and the header data separately.

[0008] In addition, the device may require receiving data by means of bare words mericals having a number of bytes that may be different from the number of bytes of the numeric words used to store data in memory.

[0009] Typically, the central processing unit is configured to duplicate the data stored in memory intended for the peripheral device in order to then modify its format to adapt it to that required by the peripheral. The data format modification is then performed in software. The reformatted data is then transmitted to the peripheral device directly or via a direct memory access controller.

[0010] For example, the central processing unit is used to concatenate the prefix and header data associated with a message to be encrypted / decrypted in order to obtain a reformatted header.

[0011] Data duplication by the central processing unit results in significant memory usage and processing time.

[0012] There is therefore a need to propose a solution enabling the transmission of data stored in memory to a peripheral in a simplified manner in order to limit the memory occupancy and the processing time required for this data transmission.

[0013] According to one aspect, a computer system is proposed comprising: - a central processing unit, - a device configured to process data in a first format, - a memory configured to store data intended for the device, the data being in a second format distinct from the first format, - a direct memory access controller configured to, during data transmission from memory to the peripheral: To retrieve data intended for the device and stored in memory, then To modify the format of the retrieved data to obtain data with the aforementioned first format, then To transmit the data according to said first format to the device, the central processing unit being configured to initiate a data transmission from memory to the device via the direct memory access controller.

[0014] Such a direct memory access controller therefore makes it possible to reformat the data stored in memory during its transmission to the peripheral. The modification of the data format is thus performed directly by the direct memory access controller, and not via software by the central processing unit.

[0015] Such a modification of the data format does not require duplication of the data retrieved from memory. Such a direct memory access controller therefore allows data to be transmitted to the peripheral in a simplified manner. limiting the memory space required for transmitting this data. The direct memory access controller allows for rapid data transfer from memory to the peripheral.

[0016] The computer system may in particular be a system on a chip.

[0017] In an advantageous embodiment, the data intended for the device includes multi-byte coded numeric words, the bytes of the numeric words being ordered in memory according to said second format, the direct memory access controller is configured to retrieve the bytes of the numeric words from memory and to order them according to said first format before transmitting them to the device.

[0018] Advantageously, the bytes of said digital words are stored at given memory addresses, the central processing unit being configured to program the direct memory access controller to enable the latter to determine the addresses of the bytes of the digital words to be accessed in memory according to said second format.

[0019] Preferably, the memory is configured to store N-byte digital words, N being an integer, the device being configured to receive and then process M-byte digital words, M being an integer multiple of N, the direct memory access controller being configured to assemble M / N N-byte digital words stored in memory so as to obtain an M-byte digital word, and then to transmit this M-byte digital word to the device.

[0020] In an advantageous embodiment, N is equal to two and M is equal to four.

[0021] Preferably, the device is a configured encryption / decryption circuit to encrypt / decrypt a digital message stored in said memory and to calculate an authentication signature from a prefix and header data associated with said digital message, the memory being configured to store the header data and said prefix separately.

[0022] Advantageously, the direct memory access controller is configured to concatenate the prefix and header data so as to obtain a reformatted header, and then to pass the reformatted header to the encryption / decryption circuit.

[0023] Advantageously, the stored header data includes multi-byte coded numeric words, the bytes of these numeric words being ordered in memory according to said second format, the direct memory access controller is configured to retrieve the bytes of these numeric words from the header data in memory and to order them according to said first format before transmitting them to the device.

[0024] According to another aspect, a method for transmitting data to a peripheral of a computer system configured to process data in a first format from memory configured to store data for the peripheral, the data stored in memory having a second format distinct from the first format, the computer system further comprising a central processing unit and a direct memory access controller, the method comprising: - an initialization, by the central processing unit, of the transmission of data from memory to the peripheral via the direct memory access controller, then - a retrieval, by the direct memory access controller, of the data intended for the device and stored in memory, then - a modification, by the direct memory access controller, of the format of the retrieved data to obtain data exhibiting said first format, then - a transmission, by the direct memory access controller, of the data according to said first format to the device.

[0025] Such a process presents the same advantages as those mentioned above for the computer system.

[0026] In an advantageous embodiment, the data intended for the device comprises multi-byte coded digital words, the bytes of the digital words being ordered in memory according to said second format, the method comprising a retrieval, by the direct memory access controller, of the bytes of the digital words in memory and then an ordering of these bytes of the digital words according to said first format by the direct memory access controller and then a transmission by the direct memory access controller of these bytes of the digital words ordered according to said first format to the device.

[0027] Advantageously, the bytes of said digital words are stored at given addresses of memory, the retrieval of the bytes of the digital words in memory comprising a determination, by the direct memory access controller, of the addresses of the bytes of the digital words to be accessed in memory according to said second format.

[0028] Preferably, the memory is configured to store N-byte digital words, N being an integer, the device being configured to receive and then process M-byte digital words, M being an integer multiple of N, the method comprising an assembly, by the direct memory access controller, of M / N N-byte digital words stored in memory so as to obtain an M-byte digital word, and then a transmission of this M-byte digital word to the device.

[0029] In an advantageous embodiment, N is equal to two and M is equal to four.

[0030] Preferably, the device is an encryption / decryption circuit configured to encrypt / decrypt a digital message stored in said memory and to calculate an authentication signature from a prefix and header data associated with said digital message, the memory being configured to store the header data and said prefix separately.

[0031] Advantageously, the data format modification by the direct memory access controller includes a concatenation of the prefix and header data so as to obtain a reformatted header, this reformatted header then being passed to the encryption / decryption circuit by the direct memory access controller.

[0032] In an advantageous embodiment, the stored header data comprises multi-byte coded numeric words, the bytes of these numeric words being ordered in memory according to said second format, the method comprising a retrieval, by the direct memory access controller, of the bytes of the numeric words of the header in memory and then an ordering of these bytes of the numeric words of the header according to said first format by the direct memory access controller and then a transmission by the direct memory access controller of these bytes of the numeric words of the header ordered according to said first format to the device.

[0033] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which:

[0034] [Fig.1]

[0035] [Fig.2]

[0036] [Fig.3] illustrate embodiments and implementations of the invention.

[0037] Figure 1 illustrates one embodiment of a computer system SYS. A system-on-chip (SYS) computer system can be a system-on-chip (SoC). The SYS computer system includes a central processing unit (CPU), memory (MEM), at least one PRPH device, and a direct memory access controller (DMA).

[0038] Figure 1 illustrates a single PRPH device. However, it is possible to provide several PRPH devices.

[0039] In this embodiment, the PRPH device is an encryption / decryption circuit configured to be able to encrypt / decrypt a digital message.

[0040] The PRPH encryption / decryption circuit can in particular be configured to perform encryption / decryption according to the "AES" standard (acronym for the English "Advanced Encryption Standard").

[0041] Such a PRPH encryption / decryption circuit may in particular use the mode "AES-CCM" (in English "Counter with Cipher Block Chaining-Message Authentication Code"). Such an encryption / decryption circuit is well known to those skilled in the art.

[0042] The "AES-CCM" encryption / decryption method encrypts / decrypts a digital message and uses an authentication tag calculated from a prefix and header data associated with that digital message. The authentication tag authenticates the integrity of the encrypted message to which it is associated. The header data includes user-defined information. The prefix includes information about the header length, specifically encrypted according to NIST Special Publication 800-38C. The prefix size varies depending on the header length. For example, the prefix can be encoded in two, six, or ten bytes.

[0043] The SYS computer system further includes a BS computer bus which is shared between the central processing unit CPU, the MEM memory, and the DMA direct memory access controller.

[0044] Furthermore, the DMA direct memory access controller is also electrically connected to the PRPH device.

[0045] The DMA direct memory access controller is configured to allow the PRPH device to retrieve data stored in MEM memory, without intervention from the central processing unit CPU.

[0046] In particular, the CPU is simply configured to initialize data transmission from MEM to the PRPH device. Specifically, the CPU is configured to start an internal clock of the DMA direct memory access controller. Then, the CPU is configured to initialize this DMA direct memory access controller by specifying the addresses of the data to be read (those of the prefix and those of the header) and by specifying the data format in memory and the data format required by the PRPH device. Next, the CPU activates the DMA direct memory access controller and then the PRPH device. The PRPH device then sends a signal to the DMA direct memory access controller to indicate that it is ready to receive data in order to start the transmission.

[0047] MEM memory is non-volatile memory. MEM memory is configured to store data in a given format.

[0048] This format depends, for example, on how the data is stored in this MEM memory. In particular, this format may depend on an endianness method implemented for storing the data in MEM memory.

[0049] More specifically, each data item is stored in MEM memory in at least one digital word of at least one byte. Entism defines the order in which the bytes of the digital words are stored in MEM memory.

[0050] The MEM memory can, for example, be configured to store data in two-byte (16-bit) digital words.

[0051] Some data stored in the MEM memory may be intended for the PRPH device. For example, when the PRPH device is an encryption / decryption circuit, the MEM memory may be configured to store the digital message to be encrypted / decrypted, header data, and a prefix associated with the digital message. The header data and the prefix are stored separately in the MEM memory.

[0052] The header data and the prefix are then recorded in MEM memory in a given format.

[0053] Figure 2 illustrates an example of a PRFX prefix and HDR header data stored in MEM memory. The values ​​of the data stored in MEM memory are shown here in hexadecimal. MEM memory is configured here to store data in two-byte numeric words.

[0054] For example, the PRFX prefix is ​​represented on a single two-byte numeric word with the value "0020". This numeric word is stored at ADDR address 0x20000468 in MEM memory. The HDR header data is represented on sixteen two-byte numeric words. These numeric words are stored from ADDR address 0x200004c8 to address 0x200004e7.

[0055] The PRPH device is configured to process data stored in the MEM memory intended for it. However, the device may require receiving data in a data format different from the format of the data stored in the MEM memory.

[0056] In particular, when the PRPH device is an encryption / decryption circuit, the PRPH device may require receiving the header data and prefix in a given format. For example, the PRPH device may require concatenating the prefix with the header data. The PRPH device may require receiving bytes of the numeric words of the data in a data order that may be different from the order used to store the bytes of the numeric words in MEM memory.

[0057] In order to provide the PRPH device with data conforming to the format it requires, the DMA direct memory access controller is configured to modify the format of the data stored in MEM memory and intended for the PRPH device before transmitting it to the latter.

[0058] More specifically, the DMA direct memory access controller has an input configured to receive IDAT data from MEM memory via the BS computer bus.

[0059] The DMA direct memory access controller is configured, in particular, to receive IDAT data as input in the MEM memory data format. The direct memory access controller is, for example, configured to receive two-byte (16-bit) numeric words as input from the MEM memory.

[0060] The DMA direct memory access controller is configured to modify the format of the data it receives as input to make it conform to the format required by the PRPH device.

[0061] The DMA direct memory access controller also includes an output configured to deliver to the PRPH device RD AT reformatted data in the format required by the PRPH device. In particular, the DMA direct memory access controller is configured to output two-byte (32-bit) digital words resulting from the assembly of two two-byte (16-bit) digital words received as input.

[0062] The DMA direct memory access controller includes, in particular, a circuit (not shown) having a file-type structure (also known by the acronym "FIFO," from the English "First In, First Out"). This circuit is configured to receive two-byte digital words and to reorder and assemble them so as to deliver four-byte digital words at the output of the DMA direct memory access controller.

[0063] In particular, the DMA direct memory access controller is configured to access digital words to be assembled located at two different memory addresses, knowing the spacing between these two addresses. Such a direct memory access controller then uses a two-dimensional addressing ("2D DMA") well known to those skilled in the art.

[0064] More specifically, when the PRPH device is an "AES-CCM" type encryption / decryption circuit, the DMA direct memory access controller is configured to concatenate a prefix to the header data associated with a ciphertext message, so as to obtain a header reformatted in the format required by the device. This reformatted header is then delivered to the PRPH device.

[0065] For example, [Fig.2] illustrates a reformatted MHDR header by the DMA direct memory access controller. This reformatted MHRDR header has the PRFX prefix "0020" concatenated to the HDR header data stored in MEM memory.

[0066] The two-byte numeric words stored in the MEM memory were rearranged and assembled to obtain four-byte numeric words in the reformatted MHDR header. For example, the numeric word "cbc8" and the word The numeric "1124" from the HDR header data was assembled by the DMA direct memory access controller to obtain the numeric word "cbc81124".

[0067] The DMA direct memory access controller can also add padding bytes to the end of the reformatted MHDR header. For example, in [Fig.2], the reformatted header includes two PAD padding bytes with the value "0000".

[0068] The DMA direct memory access controller can be programmed by the central processing unit CPU via the BS computer bus.

[0069] Programming the DMA direct memory access controller allows it to be instructed how to modify the format of the data stored in MEM memory and intended for the PRPH device. In particular, the DMA direct memory access controller is programmed to know in what order to read the data from MEM memory so as to reorder it at the output.

[0070] Such a direct memory access controller allows the format of data stored in memory to be modified directly, without intervention from the central processing unit. In particular, the direct memory access controller allows the header format to be modified by adding the prefix before transmitting it to the peripheral.

[0071] Such a computer system is thus configured to avoid duplicating data stored in memory to modify its format before transmitting it to the peripheral. Indeed, using the direct memory access controller to modify the format of the data stored in memory does not require duplicating this data. This limits the memory space required for data transmission to the peripheral. This, in turn, allows for the use of a smaller memory size.

[0072] Figure 3 illustrates a method of transmitting data from a MEM memory to a PRPH peripheral of a SYS computer system as described above.

[0073] The method includes an initialization 30 of the transmission of data stored in the MEM memory to the PRPH device. This initialization is performed by the central processing unit (CPU).

[0074] The method then includes retrieving 31 by the DMA direct memory access controller said data stored in the MEM memory. The format of the retrieved data conforms to the format used for storing the data in the MEM memory.

[0075] Then, the method includes a modification 32 of the retrieved data format. In this step, the DMA direct memory access controller converts the retrieved data format to conform to the format required by the PRPH device.

[0076] In particular, when the PRPH device is an encryption / decryption circuit, the direct memory access controller concatenates the prefix and header data stored in MEM memory.

[0077] The direct memory access controller can also modify the order of the digital words of the retrieved data and assemble the digital words to obtain new digital words with a larger number of bytes. In particular, the direct memory access controller can assemble two two-byte (16-bit) digital words to obtain four-byte (32-bit) digital words.

[0078] These operations make it possible to obtain a reformatted header in which the prefix and the header data retrieved from MEM memory are concatenated.

[0079] The method then includes transmitting the reformatted data to the PRPH device. For example, the method includes transmitting the reformatted header to the PRPH device.

[0080] Of course, the present invention is susceptible to various variations and modifications that will become apparent to those skilled in the art. For example, the device could be a video data processing circuit. In particular, each pixel could be encrypted using three primary color components (e.g., red, green, blue), each component being encoded by a numeric number stored in memory according to a predetermined format. For compression and memory efficiency reasons, it is possible to modify the order in which the components are stored in their initial format to reorder them into a different format, or more simply, to decimate and reorder the pixels in order to reduce the amount of information in the video stream. The direct memory access controller is then configured to adapt the pixel format between the memory and the video data processing circuit.

Claims

Claims

1. Computer system comprising: - a central processing unit (CPU), - a peripheral (PRPH) configured to process data having a first format, - a memory (MEM) configured to store data intended for the peripheral, the data having a second format distinct from the first format, - a direct memory access (DMA) controller configured to, during data transmission from the memory (MEM) to the peripheral (PRPH): O retrieve data intended for the device (PRPH) and stored in memory (MEM), then O modify the format of the retrieved data to obtain data having said first format, then O transmitting the data according to said first format to the peripheral (PRPH), the central processing unit (CPU) being configured to initialize a transmission of data from the memory (MEM) to the peripheral (PRPH) via the direct memory access controller (DMA), wherein the peripheral (PRPH) is an encryption / decryption circuit configured to encrypt / decrypt a digital message stored in said memory (MEM) and to calculate an authentication signature from a prefix and data of a header associated with said digital message, the memory being configured to separately store the data of the header and said prefix, and wherein the direct memory access controller (DMA) is configured to concatenate the prefix and the data of the header so as to obtain a reformatted header, then to transmit the reformatted header to the encryption / decryption circuit.

2. A computer system according to claim 1, wherein the data intended for the peripheral (PRPH) comprises digital words coded on several bytes, the bytes of the digital words being ordered in the memory (MEM) according to said second format, the direct memory access controller (DMA) is configured to retrieve the bytes of the digital words in the memory (MEM) and to order them according to said first format before transmitting them to the peripheral (PRPH).

3. Computer system according to claim 2, in which the bytes of said digital words are stored at given addresses of the memory (MEM), the central processing unit (CPU) being configured to program the direct memory access controller (DMA) to enable the latter to determine the addresses of the bytes of the digital words to be accessed in memory (MEM) according to said second format.

4. Computer system according to any one of claims 2 or 3, in which the memory (MEM) is configured to store digital words of N bytes, N being an integer, the peripheral (PRPH) being configured to receive and then process digital words of M bytes, M being an integer multiple of N, the direct memory access controller (DMA) being configured to assemble M / N digital words of N bytes stored in memory (MEM) so as to obtain a digital word of M bytes, then to transmit this digital word of M bytes to the peripheral (PRPH).

5. The computer system of claim 4, wherein N is equal to two and M is equal to four.

6. A computer system according to claim 1, wherein the stored header data comprises digital words encoded over several bytes, the bytes of these digital words being ordered in the memory according to said second format, the direct memory access (DMA) controller is configured to retrieve the bytes of these digital words from the header data in the memory and to order them according to said first format before transmitting them to the peripheral (PRPH).

7. Method for transmitting data to a peripheral (PRPH) of a computer system (SYS) configured to process data having a first format from a memory (MEM) configured to store data intended for the peripheral, the data stored in memory having a second format distinct from the first format, the computer system (SYS) further comprising a central processing unit (CPU) and a direct memory access controller (DMA), the method comprising: - an initialization (30), by the central processing unit (CPU), of the transmission of data from the memory (MEM) to the peripheral (PRPH) via the direct memory access controller (DMA), then - a recovery (31), by the direct memory access controller (DMA), of the data intended for the peripheral (PRPH) and stored in memory (MEM), then - a modification (32), by the direct memory access controller (DMA), of the format of the recovered data to obtain data having said first format, then - a transmission (33), by the direct memory access controller (DMA), of the data according to said first format to the peripheral (PRPH), in which the peripheral (PRPH) is an encryption / decryption circuit configured to encrypt / decrypt a digital message stored in said memory (MEM) and to calculate an authentication signature from a prefix and data of a header associated with said digital message, the memory being configured to separately store the data of the header and said prefix,and wherein the data format modification by the direct memory access (DMA) controller comprises a concatenation of the prefix and the header data so as to obtain a reformatted header, this reformatted header then being transmitted to the encryption / decryption circuit by the direct memory access (DMA) controller.,

8. Method according to claim 7, in which the data intended for the peripheral (PRPH) comprise digital words coded on several bytes, the bytes of the digital words being ordered in the memory (MEM) according to said second format, the method comprising a recovery, by the direct memory access controller (DMA), of the bytes of the digital words in the memory (MEM) then an ordering of these bytes of the digital words according to said first format by the direct memory access controller (DMA), then a transmission by the direct memory access controller (DMA) of these bytes of the digital words ordered according to said first format to the peripheral (PRPH).

9. Method according to claim 8, in which the bytes of said digital words are stored at given addresses of the memory (MEM), the retrieval of the bytes of the digital words in the memory (MEM) comprising a determination, by the direct memory access controller (DMA), of the addresses of the bytes of the digital words to be accessed in memory (MEM) according to said second format.

10. A method according to any one of claims 8 or 9 wherein the memory (MEM) is configured to store digital words of N bytes, N being an integer, the peripheral (PRPH) being configured to receive and then process digital words of M bytes, M being an integer multiple of N, the method comprising an assembly, by the direct memory access controller (DMA), of M / N digital words of N bytes stored in memory (MEM) so as to obtain a digital word of M bytes, then a transmission of this digital word of M bytes to the peripheral (PRPH).

11. The method of claim 10, wherein N is two and M is four.

12. Method according to claim 7, in which the stored header data comprises digital words coded on several bytes, the bytes of these digital words being ordered in the memory according to said second format, the method comprising a recovery, by the direct memory access controller (DMA), of the bytes of the digital words of the header in the memory (MEM) then an ordering of these bytes of the digital words of the header according to said first format by the direct memory access controller (DMA), then a transmission by the direct memory access controller (DMA) of these bytes of the digital words of the header ordered according to said first format to the peripheral (PRPH).

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