Differential amplification readout circuit
The differential amplification readout circuit addresses the reliability and control issues of existing p-bit readout circuits by differentially amplifying currents in the readout circuit, improving the accuracy and control of state reading for probabilistic p-bits.
Patent Information
- Application Number
- FR2022013447
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-15
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2042-12-15
AI Technical Summary
Existing readout circuits for probabilistic p-bits face challenges in reliability and control due to the small signal variations at the output, which affect the operating point and reliability of the read circuit.
A differential amplification readout circuit is designed with a resistive component, a reading block for comparing resistance values, and a control block for differentially amplifying currents applied to the resistive and reference components, independently of the reading current.
The proposed circuit enhances the reliability and simplicity of controlling the readout process, allowing for more accurate state reading of resistive components and influencing the stochasticity or switching rate of p-bits.
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Abstract
Description
Title of the invention: Differential amplification readout circuit
[0001] The present invention relates to a differential amplification readout circuit.
[0002] Unlike conventional electronic devices that encode information in the form of a deterministic 0 and 1 bit, a probabilistic p-bit constantly fluctuates between 0 and 1. These probabilistic devices could be used for unconventional computing and stochastic computing, but they can also be considered as low-quality quantum bits.
[0003] In the article KY Camsari, BM Sutton, and S. Datta, “p-bits for probabilistic spin logic,” Applied Physics Reviews, vol. 6, no. 1, p. 011305, Mar. 2019, publisher: American Institute of Physics - https: / / aip.scitation.org / doi / 10.1063 / L5055860, it is proposed to implement p-bits using low-barrier magnetic memory.
[0004] In the classical approach to magnetic memory (MRAM), a magnetic tunnel junction (MTJ) encodes deterministic values that are a function of the magnetic orientation of two ferromagnetic layers. The two states of the MTJ, illustrated in Figure 1 (P for parallel, and AP for antiparallel) are separated by an energy barrier AE. In traditional MRAMs, this barrier is designed high enough to avoid thermal noise, typically ...Æ.... > 6Q, with T la ( W) temperature and kB the Boltzmann constant, and guarantee memorization of at least 10 years.
[0005] However, some authors have also proposed a low energy barrier JTM as a true random number generator (TRNG). The rate of transition from one state to another of the JTM or the immobilization time is expressed by the following equation: r _ j. with r° a predetermined time constant finished.
[0006] A p-bit is an entity generally composed of a continuously oscillating JTM and a comparator. However, in this approach, the comparison remains difficult in view of the small variation of the signal observed at the output. Indeed, the reference voltage used for the comparison must follow the bias voltage of the p-bit in the traditional architecture, since the operation of the p-bit requires varying the bias current through the JTM. This affects the operating point of the read circuit, which affects its reliability. Indeed, the read current through the JTM is the same as the amplification current of the read amplifier.
[0007] There is therefore a need for a circuit for reading the state of a resistive component which is more reliable while being simple to control.
[0008] For this purpose, the present description relates to a differential amplification reading circuit comprising: a. a resistive component having distinct states corresponding to different resistance values of the resistive component, b. a block for reading the state of the resistive component by comparing the resistance value of the resistive component with the resistance value of a reference component, the reading block being traversed by a reading current, and c. a control block capable of differentially amplifying the current applied to the resistive component and to the reference component, independently of the reading current.
[0009] According to particular embodiments, the circuit comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:
[0010] - the reading circuit is a variable random bit generator, the component resistive having two distinct states corresponding to different resistance values of the resistive component, the probability of the resistive component being in each of the states depending on the energy applied to the resistive component, the control block being capable of controlling the probability of the resistive component being in each of the states by controlling the energy applied to the resistive component;
[0011] - the resistance value of the reference component is substantially equal to half of the sum of the two resistance values of the two states of the resistive component;
[0012] - the reading block has two operating modes among a reset mode initialization during which the reading block is reset and a reading mode during which the resistance state of the resistive component is read by the reading block, the reading block comprising: a. a switching unit capable of switching the reading block between the two operating modes as a function of a switching signal applied to the switching unit, b. the reference component, and c. a comparator of the resistance value of the resistive component to the resistance value of the reference component;
[0013] - the comparator is a circuit whose outputs are the voltages at two nodes of comparator reference;
[0014] - the reading block further comprises an RS lock whose inputs are the voltages of the two reference nodes of the comparator;
[0015] - the switching unit comprises two transistors of the same polarity and one transistor of opposite polarity;
[0016] - the control block is controlled by a control signal so that the current applied to the resistive component depends on the amplitude of the control signal;
[0017] - the switching signal and the control signal are synchronous;
[0018] - the control signal is a voltage having a non-zero minimum value, of preferably greater than or equal to 0.3 Volts;
[0019] - the control block comprises two transistors controlled by the control signal, one of the transistors being connected to the resistive component, and the other transistor being connected to the reference component;
[0020] - the resistive component is a magnetic tunnel junction comprising an assembly of layers, the two states corresponding, on the one hand, to a parallel magnetization of the layers of the junction and, on the other hand, to an antiparallel magnetization of the layers of the junction.
[0021] Other characteristics and advantages of the invention will appear on reading the following description of embodiments of the invention, given by way of example only and with reference to the drawings which are:
[0022] [Fig.l], [Fig.l], a schematic representation of an example of a resistive component of the magnetic tunnel junction type,
[0023] [Fig.2], [Fig.2], a schematic representation of an example of a bit generator random,
[0024] [Fig.3], [Fig.3], a schematic representation of an example implementation of the random bit generator of [Fig.2], and
[0025] [Fig.4], [Fig.4], a graph illustrating experimental results obtained in implementing the random bit generator of [Fig.3].
[0026] In the following, the present description is described, in the particular case of a differential amplification reading circuit used as a variable random bit generator. Such a reading circuit is however not limited to a random bit generator as indicated at the end of the description.
[0027] A random bit generator 10 is illustrated by [Fig.2], and by [Fig.3] in a specific embodiment. A random bit generator 10 is a device capable of generating a value 0 or 1, corresponding to a bit value, in a random (i.e. non-deterministic) manner.
[0028] The generator 10 comprises a resistive component 12, a reading block 14 and a control block 16.
[0029] The resistive component 12 is capable of taking at least two distinct states. Each state corresponds to a specific resistance value. The probability of the resistive component 12 being in each of the states depends on the energy applied to the resistive component 12. The applied energy includes the energy coming from the ambient environment (in particular relating to the temperature) and any additional energy supplied to the resistive component 12. In particular, the supply of additional energy allows to influence the probability of the resistive component 12 being in one or the other of the states.
[0030] In one example, the resistive component 12 is a magnetic tunnel junction (MTJ). In this case, as illustrated by [Fig.l], the resistive component 12 is capable of taking two distinct states corresponding to a different magnetization of the ferromagnetic layers forming the resistive component 12. In particular, a first state corresponding to a first resistance value is obtained for a magnetization, called parallel, of the layers of the resistive component 12. A second state corresponding to a second resistance value is obtained for a magnetization, called antiparallel, of the layers of the resistive component 12.
[0031] The reading block 14 is capable of reading the state of the resistive component 12. For this, the reading block 14 is capable of comparing the resistance value of the resistive component 12 with the resistance value of a reference component 20. The reference component 20 is an element of the reading block 14.
[0032] In one example, the reference component 20 is a resistor.
[0033] In one example, the resistance value of the reference component 20 is fixed and is between the two resistance values of the two states of the resistive component 12. For example, in the case of a JTM, the resistance value of the reference component 20 is between the resistance value of the parallel state and the resistance value of the antiparallel state.
[0034] Preferably, the resistance value of the reference component 20 is substantially equal to half the sum of the two resistance values of the two states of the resistive component 12.
[0035] In an exemplary embodiment, the reading block 14 comprises two operating modes among a reset mode during which the reading block 14 is reset and a reading mode during which the resistance state of the resistive component 12 is read by the reading block 14.
[0036] In this embodiment, the reading block 14 further comprises a switching unit 22 and a comparator 24. The reading block 14 also preferably comprises an RS latch 26.
[0037] The switching unit 22 is capable of switching the reading block 14 between the two operating modes as a function of a switching signal CLK applied to the switching unit 22. The switching signal CLK is, for example, a voltage.
[0038] In an exemplary embodiment, the switching unit 22 comprises two transistors of the same polarity and one transistor of opposite polarity.
[0039] The comparator 24 is capable of comparing the resistance value of the resistive component 12 with the resistance value of the reference component 20.
[0040] Preferably, the comparator 24 is a circuit whose outputs are the voltages at two reference nodes Q, Q of the comparator 24. In the case of a random bit generator, said voltages are interpreted as a bit value. In other words, the voltages obtained make it possible to determine whether the bit has the value 1 or 0.
[0041] The RS 26 latch is suitable for separating the currents produced during reading and resetting of the reading block 14. In particular, the RS 26 latch is suitable for recording only the bit values obtained during the reading phases.
[0042] The RS 26 latch has two control inputs R (for “reset”) and S (for “set”), each supplied by the voltages of the two reference nodes Q, Q of the comparator 24.
[0043] The control block 16 is capable of controlling the probability of the resistive component 12 being in each of the states by controlling the energy applied to the resistive component 12.
[0044] In particular, the control block 16 is capable of applying additional energy to the resistive component 12 in addition to the energy coming from the ambient environment. The application of this additional energy makes it possible to influence the probability of the resistive component 12 being in one of the states.
[0045] In an exemplary embodiment, the control block 16 is controlled by a control signal CTRL so that the energy applied to the resistive component 12 depends on the amplitude of the control signal CTRL.
[0046] In particular, the switching signal CLK and the control signal CTRL are synchronous, i.e. clocked at the same clock frequency. The amplitudes of the switching signal CLK and the control signal CTRL are different.
[0047] Preferably, the control signal CTRL is a voltage having a non-zero minimum value, preferably greater than or equal to 0.3 Volts.
[0048] In an exemplary embodiment, the control block 16 comprises two transistors of the same polarity) controlled by the control signal CTRL, one of the transistors being connected to the resistive component 12, and the other transistor being connected to the reference component 20.
[0049] A particular example of implementation of the generator 10 is described with reference to [Fig.3].
[0050] In this example, the reading block 14 is supplied by a potential VDD.
[0051] The switching unit 22 comprises a transistor MO (NMOS) and two transistors M1, M2 (PMOS). The transistors MO, M1, M2 are controlled by the same switching signal CLK. Thus, when the switching signal CLK is in the low state, the transistors M1 and M2 are on and the transistor MO is off, and vice versa. The transistor M1 is connected on the one hand to the potential VDD (by its drain or its source) and on the other hand (by the other of its drain or its source) to a node of reference Q of the reading block 14. The transistor M2 is connected on the one hand to the potential VDD (by its drain or its source) and on the other hand (by the other of its drain or its source) to a reference node Q of the reading block 14, different from the reference node Q. The transistor MO is connected on the one hand to the ground (by its drain or its source) and on the other hand (by the other of its drain or its source) to a node T of the reading block 14.
[0052] The comparator 24 comprises two transistors M3, M4 (PMOS) and two transistors M5, M6 (NMOS) forming a comparator. Transistor M3 is connected on the one hand to the potential VDD (by its drain or its source) and on the other hand (by the other of its drain or its source) to the reference node Q of the reading block 14. Transistor M4 is connected on the one hand to the potential VDD (by its drain or its source) and on the other hand (by the other of its drain or its source) to the reference node Q of the reading block 14. Transistor M5 is connected on the one hand (by its drain or its source) to the reference node Q of the reading block 14 and on the other hand (by the other of its drain or its source) to a node X of the reading block 14. Transistor M6 is connected on the one hand (by its drain or its source) to the reference node Q of the reading block 14 and on the other hand (by the other of its drain or its source) to a node Y of the reading block 14.
[0053] Transistors M3 and M5 are controlled by the potential of the reference node Q (the gate of each of the transistors M3 and M5 is connected to the reference node Q). Transistors M4 and M6 are controlled by the potential of the reference node Q (the gate of each of the transistors M4 and M6 is connected to the node Q).
[0054] The resistive component 12 is connected between node X and node T. The reference component 20 is connected between node Y and node T.
[0055] The RS 26 lock has as control inputs the potential at the two reference nodes Q and Q .
[0056] The control block 16 comprises two transistors M7, M8 of the same polarity (PMOS). The two transistors M7, M8 are controlled by the same control signal CTRL. The transistor M7 is connected on the one hand (by its drain or its source) to the potential VDD, and on the other hand (by the other of its drain or its source) to the node X, and therefore to the resistive component 12. The transistor M8 is connected on the one hand (by its drain or its source) to the potential VDD, and on the other hand (by the other of its drain or its source) to the node Y, and therefore to the reference component 20. Thus, depending on the value of the signal CTRL, a more or less significant additional energy is applied to the resistive component 12, which makes it possible to control the read amplification current and can influence the probability of the resistive component 12 being in each state.
[0057] Note that as a variant, the polarities of transistors M1 and M2 on the one hand and MO on the other hand are reversed. In this case, the switching signal CLK is adapted accordingly (high state, low state). Similarly, as a variant, the polarities of transistors M7 and M8 are reversed. In this case, the control signal CTRL is also adapted in consequence.
[0058] An example of operation of the generator 10 is described in the following with reference to the embodiment of [Fig.3].
[0059] During a reset phase, the switching unit 22 switches the reading block 14 into the reset mode via the application of the same switching signal CLK to the transistors MO, M1, M2 making it possible to turn on the transistors M1 and M2, and turn off the transistor MO. This makes it possible to charge the nodes Q, Q , X and Y so that at the end of the charging period the potentials of the nodes Q, Q , X and Y are equal to VDD.
[0060] During a reading phase, the switching unit 22 switches the reading block 14 into the reading mode via the application of the same switching signal CLK to the transistors MO, M1, M2 making it possible to make the transistors M1 and M2 non-conducting, and the transistor MO conducting. This results in a differential current proportional to the value of the resistances of the resistive component 12 and of the reference component 20.
[0061] In parallel, the value of the control signal CTRL is adapted so as to adapt the probability of the resistive component 12 being in one of the states. The resistance value of the resistive component 12 therefore potentially evolves differently due to the control block 16 than in the absence of such a control block 16.
[0062] The nodes Q and Q will then discharge, but at different speeds depending on the resistance values of the resistive component 12 and the reference component 20. In particular, if the resistance value of the resistive component 12 is greater than that of the reference component 20 (antiparallel state of the JTM), the discharge of the node Q is faster than that of the node Q. Conversely, if the resistance value of the resistive component 12 is lower than that of the reference component 20 (parallel state of the JTM), the discharge of the node Q is faster than that of the node Q.
[0063] The node discharging the fastest sees its potential fall below the threshold voltage of the transistors M3, M4, M5, M6 that it controls, allowing it to discharge even more quickly. Conversely, the other node will charge to VDD. More precisely, the node Q controlling the transistors M4, M6 and the node Q controlling the transistors M3, M5, the discharge of the node Q causes the charge of the node Q to the potential VDD, and conversely, the discharge of the node Q causes the charge of the node Q to the potential VDD.
[0064] When the potentials at nodes Q and Q are opposite (one at 0, the other at VDd), the RS 26 latch records the corresponding bit value (0 or 1 depending). For example, when the resistance of resistive component 12 is lower than the resistance of reference component 20 (parallel case), we have Q=0 and Q=1. The RS 26 latch therefore establishes a logic state representative of the value of the JTM for Q=0 and Q=1.
[0065] A new reset phase is then initiated.
[0066] By implementing generator 10 of [Fig.3], we obtained the following experimental results.
[0067] The p-bits are characterized by their sigmoidal response which describes the time average of a fluctuating signal. To evaluate the response behavior of the proposed generator, we vary the "CTRL" signal from 0 to 1.4 Volts (V). For each voltage value, we calculate the probability of being in a state (0 or 1) as follows:
[0068] _ «(Q) * «({))+„(])
[0069] Where: • p represents the probability of having 0 V as the output signal, and • n the number of '0' and T' for output signals.
[0070] [Fig.4] is a graph obtained experimentally from generator 10 of [Fig.3]. In this graph, the abscissa axis represents the potential of the control signal CTRL for a clock calibrated at 50 Megahertz (Mhz) and a supply voltage of 1.5 V (VDD). The ordinate axis represents the probability of being in one of the corresponding to bit 0. With a supply voltage of 1.5 V, the energy consumed per clock cycle is 1300 fJ. By reducing the supply voltage to 1 V and controlling the JTM to maintain the sigmoidal response, the energy is reduced to 40 fJ per cycle.
[0071] Thus, the present invention makes it possible both to read the state variations of the resistive component 12, in particular in the example of a tunnel junction, and also to control its stochasiticity or switching rate. In particular, the increase in the current arriving at the resistive component 12, by controlling the control block 16, makes it possible to amplify the reading current and therefore influences the probability of the resistive component 12 being in one state rather than another.
[0072] Compared to the p-bit presented in the prior art, implemented using a transistor and a comparator, where a current constantly flows through the JTM to act on the switching rate and compare it to a reference, the present invention correlates reading and writing. The differential aspect makes it possible to decouple reading from the bias current of the JTM compared to the p-bit presented in the prior art.
[0073] In addition, the current only flows through the JTM for half of the clock cycle. Energy is consumed only in the charge and discharge phases of the transistors. This feature reduces the static energy consumption of the original p-bit. In addition, the differential architecture of the generator 10 of the invention facilitates the reading of the JTM: the global variations of the process are cancelled and we do not need to add an external reference.
[0074] Thus, the circuit for reading the state of a resistive component is more reliable than in the state of the art while being simple to control.
[0075] Those skilled in the art will understand that the embodiments and variants previously described can be combined provided that they are technically compatible.
[0076] Furthermore, as indicated previously, the invention has been described in the particular case of a random bit generator. However, the present invention is generalized in the case of a differential amplification reading circuit. In this case, the resistive component 12 is capable of taking several distinct states (two or more) corresponding to different resistance values of the resistive component 12. The control block 16 is capable of differentially amplifying the current applied to the resistive component 12 and to the reference component 20, independently of the current flowing through the reading block, called the reading current. In other words, the reading is not affected even in the case of significant amplification of the current passing through the resistive component 12.Note that in this embodiment, the state of the resistive component 12 can be fixed, that is to say that the variations in the current passing through the resistive component 12 do not make it possible to modify the state of the resistive component 12.
Claims
Claims
1. Differential amplification reading circuit (10) comprising: a. a resistive component (12) having distinct states corresponding to different resistance values of the resistive component (12), b. a block (14) for reading the state of the resistive component (12) by comparing the resistance value of the resistive component (12) with the resistance value of a reference component (20), the reading block (14) being traversed by a reading current, and c. a control block (16) capable of differentially amplifying the current applied to the resistive component (12) and to the reference component (20), independently of the reading current.
2. A differential amplification read circuit (10) according to claim 1, wherein the read circuit (10) is a variable random bit generator, the resistive component having two distinct states corresponding to different resistance values of the resistive component (12), the probability of the resistive component (12) being in each of the states depending on the energy applied to the resistive component (12), the control block (16) being able to control the probability of the resistive component (12) being in each of the states by controlling the energy applied to the resistive component (12).
3. A differential amplification readout circuit (10) according to claim 2, wherein the resistance value of the reference component (20) is substantially equal to half the sum of the two resistance values of the two states of the resistive component (12).
4. A differential amplification read circuit (10) according to any one of claims 1 to 3, wherein the read block (14) has two operating modes among a reset mode during which the read block (14) is reset and a read mode during which the resistance state of the resistive component (12) is read by the read block (14), the read block (14) comprising: a. a switching unit (22) adapted to switch the read block (14) between the two operating modes by function of a switching signal (CLK) applied to the switching unit (22), b. the reference component (20), and c. a comparator (24) of the resistance value of the resistive component (12) to the resistance value of the reference component (20).
5. A differential amplification readout circuit (10) according to claim 4, wherein the comparator (24) is a circuit whose outputs are the voltages at two reference nodes (Q, Q) of the comparator (24).
6. A differential amplification read circuit (10) according to claim 5, wherein the read block (14) further comprises an RS latch (26) whose inputs are the voltages of the two reference nodes (Q, Q) of the comparator (24).
7. A differential amplification readout circuit (10) according to any one of claims 4 to 6, wherein the switching unit (22) comprises two transistors (M1, M2) of the same polarity and one transistor (MO) of opposite polarity.
8. A differential amplification readout circuit (10) according to any one of claims 1 to 7, wherein the control block (16) is controlled by a control signal (CTRL) so that the current applied to the resistive component (12) depends on the amplitude of the control signal (CTRL).
9. Differential amplification reading circuit (10) according to claim 8 in its dependency with one of claims 4 to 6, in which the switching signal (CLK) and the control signal (CTRL) are synchronous.
10. Differential amplification reading circuit (10) according to claim 8 or 9, in which the control signal (CTRL) is a voltage having a non-zero minimum value, preferably greater than or equal to 0.3 Volts.
11. A differential amplification read circuit (10) according to any one of claims 1 to 10, wherein the control block (16) comprises two transistors (M7, M8) controlled by the control signal (CTRL), one of the transistors (M7) being connected to the resistive component (12), and the other transistor (M8) being connected to the resistive component (12). reference (20).
12. A differential amplification readout circuit (10) according to any one of claims 1 to 11, wherein the resistive component (12) is a magnetic tunnel junction comprising an assembly of layers, the two states corresponding, on the one hand, to a parallel magnetization of the layers of the junction and, on the other hand, to an antiparallel magnetization of the layers of the junction.