Microelectronic FET device comprising large contact surfaces between the conduction channel and the source and drain regions

Abstract

A microelectronic FET device (100) comprising: - a semiconductor layer (120) of which a first region (122) forms a channel; - several gates (110) and a gate dielectric layer (112) arranged on the first region, the gates being distinct and spaced apart; - dielectric spacers (114) arranged against the flanks of the gates; - source (116) / drain (118) regions electrically coupled to the first region by second regions (124) of the active layer extending between the source / drain regions and the dielectric spacers; wherein the second regions form, with the first region, a continuous layer. Figure for the abbreviation: Figure 7.

Description

Title of the invention: FET microelectronic device comprising large contact surfaces between the conduction channel and the source and drain regions technical field

[0001] The invention relates to the field of microelectronic devices applied to advanced CMOS technologies. The invention relates in particular to FET (Field-Effect Transistor) type microelectronic devices, in particular RFET (Reconfigurable Field-Effect Transistor) type, especially based on two-dimensional materials, or 2D materials, or semiconductor oxides, as well as the realization of such microelectronic devices. Prior art

[0002] The miniaturization of electronics is constantly increasing, but the industry is now approaching the scale limit for conventional materials such as silicon. Recently, 2D materials have emerged as promising candidates for use in miniaturized electronic and optoelectronic devices due to their unique properties and the very thin layers of these materials, which can consist of a single layer of atoms or molecules.

[0003] The document by KP O'Brien et al., "Advancing 2D Monolayer CMOS Through Contact, Channel and Interface Engineering," 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 7.1.1-7.1.4, proposes to fabricate a MOSFET transistor by integrating a MoS2 layer to form the conduction channel. This layer is connected to two metallic source and drain regions based on gold, palladium, TiN, tungsten, or nickel. The back gate is formed by a doped silicon layer positioned on the back side under a dielectric layer based on SiO2, HfO2, or Al2O3.

[0004] To overcome the constraints related to the deposition of metallic materials in the source and drain regions on the 2D material, it is possible to form these regions not on the upper surface of the 2D material layer, but against the sides of the 2D material layer. This configuration, called "side contact," is problematic, however, because the contact area between the 2D material layer and the source and drain regions is small, which generates significant contact resistances to interfaces between the 2D material layer and the source and drain regions.

[0005] US patent 2022 / 045176 A1 describes several methods for manufacturing gate-last FET transistors, in which portions of silicon serve as a support for the deposition of a 2D material layer. Besides the disadvantages related to the fact that the transistors produced have side-contact channel / source-drain interfaces, the silicon portions used to deposit the 2D material form a potential barrier at the interface with the 2D material, which is unfavorable because some of the charge transport may occur in these silicon portions and not in the 2D material. Description of the invention

[0006] An object of the present invention is to propose a microelectronic device of the FET type, in particular RFET, whose structure is compatible with any type of semiconductor material including 2D materials or other materials of the semiconductor oxide type, and not presenting the disadvantages of a "side contact" configuration.

[0007] To this end, the present invention proposes a FET microelectronic device comprising at least: - a substrate; - a semiconductor layer comprising at least a first zone forming an electrical conduction channel of the FET microelectronic device; - several separate electrostatic control grids, spaced apart from each other and arranged on the first area of ​​the semiconductor layer; - a grid dielectric layer disposed between each of the electrostatic control grids and the first zone of the semiconductor layer; - dielectric spacers arranged against the sides of each of the electrostatic control grids; - source / drain regions electrically coupled to the first zone of the semiconductor layer by second zones of the semiconductor layer, the second zones of the semiconductor layer extending between the source / drain regions and the dielectric spacers; and in which the second zones of the semiconductor layer are not arranged directly against the electrostatic control grid and form, with the first zone, a continuous layer.

[0008] The proposed microelectronic device is based on a FET-type architecture without a "side contact" interface between the channel and the source / drain regions, thanks to the second zones of the semiconductor layer which perform the electrical coupling between the channel formed by the first zone of the semiconductor layer. conductor and source / drain regions. These second zones of the semiconductor layer, which extend against at least part of the lateral walls, or flanks, of the source / drain regions, form a large contact area with the source / drain regions, thus reducing the contact resistances of the source / drain regions. Therefore, the electric current flowing in the channel is not reduced due to these contact resistances, and thus the device's performance is not diminished.

[0009] Furthermore, with the proposed architecture, the semiconductor layer can be fabricated just before the fabrication of the source / drain regions or just before the metal deposition of the source / drain regions. Thus, the semiconductor layer, the first zone of which is intended to form the conduction channel, is not damaged by the steps involved in fabricating the source / drain regions. This is particularly advantageous when the semiconductor layer is made of a 2D material.

[0010] Furthermore, the realization of such a device does not require the preservation of portions of silicon to deposit the semiconductor layer intended to form the channel, thus eliminating the potential barrier problem at the interface with the semiconductor layer material.

[0011] The semiconductor layer may comprise a two-dimensional material or any other semiconductor material deposited by MOCVD (Metal-Organic Chemical Vapor Deposition), CVD (Chemical Vapor Deposition), or ALD (Atomic Layer Deposition). In this case, the microelectronic device can be made with very small dimensions.

[0012] Advantageously, the FET microelectronic device can be such that: - each of the source / drain regions is disposed in a cavity comprising side walls formed at least by dielectric spacers and by an insulating dielectric material; - the second zones of the semiconductor layer cover at least part of the walls of the cavities in which the source / drain regions are arranged.

[0013] In the above configuration, the contact surfaces of the source / drain regions with the semiconductor layer are maximized by using the surface of the cavity walls, and advantageously the entire surface of the cavity walls, to form the contact between the second zones of the semiconductor layer and the source / drain regions, which allows for very low contact resistances of the source / drain regions, and therefore a higher current flowing through the conduction channel of the device.

[0014] The microelectronic device comprises several electronic control grids distinct static cells, spaced apart and arranged on the first area of ​​the active layer. In this configuration, the microelectronic device has a "Reconfigurable FET" type architecture.

[0015] The FET microelectronic device may further comprise at least one dielectric portion surrounded by the first zone of the semiconductor layer.

[0016] Alternatively, the first zone of the semiconductor layer may not surround a dielectric portion.

[0017] Advantageously, the invention can be applied to the realization of CMOS components for 5 nm and sub-5nm technology nodes.

[0018] The invention also relates to a method for implementing a FET microelectronic device, comprising at least: a) creation of at least a portion of temporary material on a substrate, then b) construction, at least on the portion of temporary material, of several separate electrostatic control grids spaced apart from each other, and of dielectric spacers arranged against the sides of each of the electrostatic control grids, then c) engraving of the portion of temporary material, then d) fabrication of a semiconductor layer comprising at least a first zone configured to serve as an electrical conduction channel for the FET microelectronic device, disposed under the electrostatic control grids and dielectric spacers in at least one location formed by etching the portion of temporary material, and such that the semiconductor layer extends, without discontinuity with the first zone, to form second zones covering at least a portion of the flanks of the dielectric spacers and which are not disposed directly against the electrostatic control grids, then (e) fabrication, on the substrate, of source / drain regions electrically coupled to the first zone of the semiconductor layer by the second zones of the semiconductor layer, and such that the second zones of the semiconductor layer extend between the source / drain regions and the dielectric spacers.

[0019] The method may further comprise, prior to the implementation of step (c), a deposition of an insulating dielectric material around the dielectric spacers, and then an etching of cavities in the insulating dielectric material such that the cavities include at least one sidewall formed by one of the dielectric spacers, and wherein: - step d) is implemented such that the second zones of the semiconductor layer cover at least part of the lateral walls of the cavities; - step e) is implemented such that each of the source / drain regions is disposed in one of the cavities.

[0020] The process may further include a step of depositing a layer of grid dielectric material implemented: - between steps a) and b), on the portion of temporary material, the electrostatic control grids are then made on the grid dielectric layer, and / or - between steps c) and d), under the electrostatic control grids and dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer being then made by covering the grid dielectric layer.

[0021] The invention also relates to a method for implementing a FET microelectronic device, comprising at least: a) fabrication of at least a portion of temporary material on a substrate, then b) fabrication, at least on the portion of temporary material, of several separate temporary grids spaced apart from each other and of dielectric spacers arranged against the flanks of each of the temporary grids, then c) a deposit of an insulating dielectric material around the dielectric spacers, then d) engraving of the temporary grids, and creation of several electrostatic control grids in place of the temporary grids, the electrostatic control grids being distinct and spaced apart from each other, then e) etching cavities in the insulating dielectric material such that the cavities comprise at least one side wall formed by one of the dielectric spacers, then f) engraving of the portion of temporary material, then (g) fabrication of a semiconductor layer comprising at least a first zone configured to serve as an electrical conduction channel for the FET microelectronic device, disposed under the electrostatic control gates and dielectric spacers in at least one location formed by etching the portion of temporary material, and such that the semiconductor layer extends, without discontinuity with the first zone, to form second zones covering at least a portion of the flanks of the dielectric spacers and which are not disposed directly against the temporary gates, then h) realization, on the substrate, of source / drain regions each disposed in one of the cavities and electrically coupled to the first zone of the semiconductor layer by the second zones of the semiconductor layer, and such that the second zones of the semiconductor layer extend between the source / drain regions and the dielectric spacers.

[0022] The process may further include a step of depositing a dielectric layer grid implementation: - during step e), on the first area of ​​the semiconductor layer, the electrostatic control grids are then made on the grid dielectric layer, and / or - between steps c) and d), under the temporary grids and dielectric spacers, in at least one location formed by etching the portion of temporary material, the semiconductor layer being then made by covering the grid dielectric layer.

[0023] Throughout this document, the terms "on" and "under" are used without distinction as to the spatial orientation of the element to which the term refers. For example, in the feature "on a face of the first substrate," this face of the first substrate is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element should be understood as either having the first element directly against the second element, without any intermediate elements between the first and second elements, or having the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0024] Throughout this document, the term "layer" may refer to a single layer or a stack of several layers.

[0025] Throughout this document, the expression "electrically couple" is used to refer to an electrical connection that may be direct or indirect (i.e., made through one or more intermediate electrical elements). Brief description of the drawings

[0026] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which: - Figs. 1 to 5 schematically represent the steps of a process for making the microelectronic device, the subject of the present invention, according to a particular embodiment; - Fig. 6 schematically represents a microelectronic device, the subject of the present invention, according to one embodiment variant.

[0027] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.

[0028] The different parts shown in the figures are not necessarily according to a uniform scale, to make the figures more legible.

[0029] The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with each other.

[0030] Detailed description of particular embodiments

[0031] A method for making a device 100 of the "Reconfigurable FET" type according to a particular embodiment is described below in relation to figures 1 to 5.

[0032] An etching of a semiconducting layer, corresponding for example to the surface layer of a substrate 102 of type SOI, is implemented so as to form, on the substrate 102 (on the buried dielectric layer 130 in the example described), a portion of temporary material 160. Alternatively, the substrate 102 can be of bulk type.

[0033] A dielectric layer 112 and several electrostatic control grids 110 are made on the temporary portion 160 and spaced apart from each other (see [Fig.1]). In the example described here, the device 100 has two grids: a control grid and a polarity grid.

[0034] The 110 grids produced are distinct and spaced apart from each other.

[0035] Layer 112 comprises, for example, a high-K dielectric material (with high per dielectric mittivity) such as HfO2. Alternatively, this layer 112 may comprise SiO2 or Al2O3 or any other suitable material or combination of materials.

[0036] The control grids 110 are, for example, made by depositing one or more conductive materials on the layer 112, for example a first deposit of a thin layer of TiN (thickness for example equal to 3 nm) on which is stacked a layer of tungsten of thickness for example equal to 200 nm. Alternatively, the grids 110 may comprise one or more materials other than TiN and W, such as, for example, doped polysilicon or any other metal (Mo, etc.).

[0037] Dielectric spacers 114 are formed against the sides of the grids 110. A suitable material for making the dielectric spacers 114 is, for example, SiN, SiCO₃, or SiBCN. The thickness of the layer deposited to make the dielectric spacers 114 is, for example, between 5 nm and 15 nm.

[0038] After the formation of the spacers 114, an insulating dielectric material 128, for example SiO2, is then deposited and planarized, stopping at the hard mask present on the grids 110 (not visible in the figures). The insulating dielectric material 128 is deposited in a thick layer, and then planarization is carried out until the hard mask is reached. The hard mask is then removed, for example, by wet etching, for example, using a dilute H3PO4 solution at a temperature of 110°C.

[0039] The structure obtained at this stage of the process is shown in [Fig.2].

[0040] Cavities 150 are then etched into the insulating dielectric material 128 (see [Fig. 3]). These cavities 150 include side walls formed by the dielectric spacers 114 and remaining portions of the insulating dielectric material 128. These cavities 150 form locations for the realization of the source and drain regions of the device 100. The parts of the temporary portion 160 not covered by the grids 110, the grid dielectric layer 112 and the dielectric spacers 114 and located at the bottom of the cavities are etched.

[0041] The remaining part of the temporary portion 160 covered by the grids 110, the grid dielectric layer 112 and the dielectric spacers 114 is etched, then a semiconductor layer 120 is deposited such that a first area 122 of the semiconductor layer 120 forms a portion of semiconductor material disposed on the substrate 102 and that the grids 110 and the grid dielectric layer 112 are disposed on this first area 122 of the semiconductor layer 120. In addition, in the example shown in [Fig.4], a dielectric layer 152 is deposited prior to the semiconductor layer 120.

[0042] Second zones 124 of the semiconductor layer 120 cover the walls of the cavities 150. These second zones 124 form, with the first zone 122, a continuous layer 120.

[0043] Advantageously, the semiconductor layer 120 comprises at least one 2D semiconductor material, for example a transition metal dichalcogenide such as MoS2, or WSe2, or WS2, or MoTe2. It is also possible that the material of the semiconductor layer 120 corresponds to IGZO, In2O3, IWO, ITO, or an amorphous semiconductor oxide, or any other suitable semiconductor material.

[0044] Source 116 and drain 118 regions are then made in the cavities 150 by depositing, in the example described, one or more metallic materials in the cavities 150. Before this or these metallic deposits, it is possible to deposit a layer of graphene in the cavities 150, this or these metals then being deposited on the graphene layer. These source 116 and drain 118 regions, in [Fig. 5], are electrically coupled to the first zone 122 of the semiconductor layer 120 via the second zones 124 of the semiconductor layer 120 which extend between the source 116 / drain 118 regions and the dielectric spacers 114 as well as against the other walls of the source 116 / drain 118 regions located in the cavities 150. The material of these regions deposited outside the cavities 150 is removed by implementing a planarization with a stop on the insulating dielectric material 128.

[0045] Advantageously, the source 116 / drain 118 regions comprise at least one metallic material such as gold, palladium, TiN, W, Ni, etc. According to one embodiment, each of the source 116 / drain 118 regions comprises a TiN layer on which a tungsten portion is formed. Different metals can be used to form regions 116, 118 in order to promote low contact resistances, such as: S, Bi, Sn, Pd, Ru, Cu, Ni, Ti, TiN, W, Au, etc. These materials can also be modified later (to improve their properties), for example by a doping step.

[0046] In the embodiment described above, the semiconductor layer 120 is such that the space previously occupied by the temporary portion 160 is completely filled by the material of the semiconductor layer 120. Alternatively, it is possible that the semiconductor layer 120 does not completely fill the space previously occupied by the temporary portion 160. In this case, after the deposition of the semiconductor layer 120, the remaining space(s) are filled with dielectric material so as to form a dielectric portion surrounded by the first zone 122 of the semiconductor layer 120. To form this dielectric portion, one or more dielectric layers, comprising for example Al2O3 (or HfO2) and / or SiO2 (or a low-k dielectric, or one with low dielectric permittivity), are deposited and then isotropically etched so as to retain only the portion located in the remaining space.

[0047] Alternatively, the device 100 may have a different number of grids. Thus, in the example of [Fig.6], the device 100 has three grids: two control grids and one polarity grid.

[0048] In the various examples described above, the second zones 124 of the semiconductor layer 120 cover all the sides and bottom walls of the source 116 and drain 118 regions. Generally, it is possible for the second zones 124 of the semiconductor layer 120 to extend between the source 116 and drain 118 regions and the dielectric spacers 114 and / or against walls of the source and drain regions other than those arranged against the dielectric spacers 114. Furthermore, the walls of the source 116 and drain 118 regions may be only partially covered by the second zones 124 of the semiconductor layer 120.

[0049] In the embodiment examples previously described for the first and second embodiments, the grid dielectric layer 112 and the electrostatic control grids 110 are made on the temporary material portion 160 before the deposition of the insulating dielectric material 128 and its planarization (the so-called "gate first" approach).

[0050] Alternatively, according to a so-called "gate last" approach, it is possible to produce, instead of the grid dielectric layer 112 and the electrostatic control grids 110, and before the deposition of the insulating dielectric material 128 and its planarization, several temporary grids arranged on temporary dielectric portions themselves arranged on the temporary material portion 160. The dielectric portions Temporary materials include, for example, SiO2, and temporary grids include, for example, polysilicon. These temporary elements are made by depositing the desired material layers, planarizing the polysilicon layer, and etching these layers according to the desired geometry for these temporary grids (a geometry similar to that of the final grids made later). The dielectric spacers 114 are then made on the flanks of the temporary grids. After the insulating dielectric material 128 is deposited and planarized, the temporary grids and temporary dielectric portions are removed by etching, and then the grid dielectric layer 112 and the electrostatic control grids 110 are made in the locations formed by the etching of the temporary grids and temporary dielectric portions.Device 100 is then completed in a similar manner to the process previously described, by implementing the steps described in relation to Figures 3 to 5.

[0051] In the embodiments described above, the gate dielectric layer 112 is formed just before the electrostatic control gates 110 are formed, whether or not temporary gates have been used. Alternatively, the electrostatic control gates 110 may be formed without first forming the gate dielectric layer 112. In this case, the gate dielectric layer 112 can be deposited just before the semiconductor layer 120 is deposited, at least against the walls of the area obtained by etching the portion of temporary material 160. In this case, the layer 112 covers the various walls onto which the semiconductor layer material 120 is intended to be deposited, thus homogenizing the surfaces, and therefore the interfaces, against which the semiconductor layer 120 is subsequently deposited.

[0052] According to another variant, it is possible that the layer 112 is deposited in two different stages: first, just before the formation of the grids 110 as previously described in connection with [Fig.1], then in the spaces formed by the etching of the portions 160 and in the cavities 150, just before the deposition of the semiconductor layer 120. In this case, the parts of the layer 112 located directly above the grid 110 are thicker than the other parts of the layer 112 because these parts combine the thicknesses of material deposited during the two deposition stages.

Claims

Demands

1. FET microelectronic device (100) comprising at least: - a substrate (102); - a semiconductor layer (120) comprising at least a first zone (122) forming an electrical conduction channel of the FET microelectronic device (100); - several separate electrostatic control gates (110), spaced apart and arranged on the first zone of the semiconductor layer; - a grid dielectric layer (112) disposed between each of the electrostatic control gates (110) and the first zone (122) of the semiconductor layer (120); - dielectric spacers (114) disposed against flanks of each of the electrostatic control gates (110);- source (116) / drain (118) regions electrically coupled to the first zone (122) of the semiconductor layer (120) by second zones (124) of the semiconductor layer (120), the second zones (124) of the semiconductor layer (120) extending between the source (116) / drain (118) regions and the dielectric spacers (114); and wherein the second zones (124) of the semiconductor layer (120) are not disposed directly against the electrostatic control grid (110) and form, with the first zone (122), a continuous layer, - each of the source (116) / drain (118) regions being disposed in a cavity (150) comprising side walls formed at least by the dielectric spacers (114) and by an insulating dielectric material (128);- the second zones (124) of the semiconductor layer (120) covering at least part of the walls of the cavities (150) in which the source (116) / drain (118) regions are arranged.;

2. FET microelectronic device (100) according to claim 1, wherein the semiconductor layer (120) comprises a two-dimensional material or any other semiconductor material deposited by MOCVD, CVD or ALD.

3. A FET (100) microelectronic device according to any one of the preceding claims, further comprising at least one dielectric portion surrounded by the first zone (122) of the semiconductor layer (120).

4. Method for making a FET (100) microelectronic device, comprising at least: a) production of at least a portion of temporary material (160) on a substrate (102), then b) fabrication, at least on the portion of temporary material (160), of several separate electrostatic control grids (110) spaced apart from each other, and of dielectric spacers (114) arranged against flanks of each of the electrostatic control grids (110), then c) engraving of the portion of temporary material (160), then d) fabrication of a semiconductor layer (120) comprising at least a first zone (122) configured to serve as an electrical conduction channel for the FET microelectronic device (100), disposed under the electrostatic control grids (110) and the dielectric spacers (114) in at least one location formed by the etching of the portion of temporary material (160), and such that the semiconductor layer (120) extends, without discontinuity with the first zone (122), forming second zones (124) covering at least a portion of the flanks of the dielectric spacers (114) and which are not disposed directly against the electrostatic control grids (110), then e) realization, on the substrate (102), of source (116) / drain (118) regions electrically coupled to the first zone (122) of the semiconductor layer (120) by the second zones (124) of the semiconductor layer (120), and such that the second zones (124) of the semiconductor layer (120) extend between the source (116) / drain (118) regions and the dielectric spacers (114), and wherein the method further comprises realization of a grid dielectric layer disposed between each of the electrostatic control grids and the first zone of the semiconductor layer.

5. A method according to claim 4, further comprising, before the implementation of step c), the deposition of an insulating dielectric material (128) around the dielectric spacers (114), and then the etching of cavities (150) in the insulating dielectric material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), and in which:

6.

7. - step d) is implemented such that the second zones (124) of the semiconductor layer (120) cover at least part of the side walls of the cavities (150); - step e) is implemented such that each of the source (116) / drain (118) regions is disposed in one of the cavities (150). A method according to claim 4 or 5, further comprising a step of depositing the layer (112) of grid dielectric material used: - between steps a) and b), on the portion of temporary material (160), the electrostatic control grids (110) are then made on the grid dielectric layer (112), and / or - between steps c) and d), under the electrostatic control grids (110) and the dielectric spacers (114), in at least one location formed by the etching of the portion of temporary material (160), the semiconductor layer (120) being then made by covering the grid dielectric layer (112). Method for making a FET (100) microelectronic device, comprising at least: a) production of at least a portion of temporary material (160) on a substrate (102), then b) construction, at least on the portion of temporary material (160), of several separate temporary grids spaced apart from each other and of dielectric spacers (114) arranged against the sides of each of the temporary grids, then c) a deposit of an insulating dielectric material (128) around the dielectric spacers (114), then d) engraving of the temporary grids, and production of several electrostatic control grids (110) in place of the temporary grids, the electrostatic control grids (110) being distinct and spaced apart from each other, then e) etching cavities (150) in the insulating dielectric material (128) such that the cavities (150) comprise at least one side wall formed by one of the dielectric spacers (114), then f) etching the portion of temporary material (160), then (g) fabrication of a semiconductor layer (120) comprising at least a first zone (122) configured to serve as an electrical conduction channel for the FET microelectronic device (100), disposed under the electrostatic control gates (110) and the dielectric spacers (114) in at least one location formed by the etching of the portion of temporary material (160), and such that the semiconductor layer (120) extends, without discontinuity with the first zone (122), forming second zones (124) covering at least a portion of the flanks of the dielectric spacers (114) and which are not disposed directly against the temporary grids, then h) realization, on the substrate (102), of source (116) / drain (118) regions, each disposed in one of the cavities (150) and electrically coupled to the first zone (122) of the semiconductor layer (120) by the second zones (124) of the semiconductor layer (120), and such that the second zones (124) of the semiconductor layer (120) extend between the source (116) / drain (118) regions and the spacers dielectrics (114),and wherein the process further comprises the fabrication of a grid dielectric layer disposed between each of the electrostatic control grids and the first zone of the semiconductor layer.

8. Method according to claim 7, further comprising a step of depositing the grid dielectric layer (112) implemented: - during step d), in the locations formed by the etching of the temporary grids, the electrostatic control grids (110) being subsequently made on the grid dielectric layer (112), and / or - between steps c) and d), under the temporary grids and the dielectric spacers (114), in at least one location formed by the etching of the portion of temporary material (160), the semiconductor layer (120) being subsequently made by covering the grid dielectric layer (112).

Images