SEMICONDUCTIVE STRUCTURE

Abstract

The invention relates to a semiconductor structure comprising: a wafer; a chiplet fixed to said wafer, and comprising a semiconductor device and one or more metallic layers connected to said semiconductor device; an interface structure for connecting an electronic package to the wafer; and a heat dissipation structure for transferring heat from the chiplet to the interface structure. Figure for the abstract: Fig. 8

Description

Title of the invention: SEMICONDUCTIVE STRUCTURE technical field

[0001] The present invention relates to semiconductor structures and in particular to semiconductor structures comprising a heat dissipation structure.

[0002] CONTEXT

[0003] Nowadays, an increasing number of applications require high linearity, high power handling, low noise, and low power consumption. Since these requirements are, in most cases, conflicting, they are very difficult to meet in Monolithic Microwave Integrated Circuits (MMICs). Therefore, it is common to use system-in-package (SiP) techniques to enclose several integrated circuits from different technologies in a single module, in order to benefit from the best of each. The chips are then connected to each other using jumper wires or bumps. This SiP technique allows for system-level integration of multiple chips / technologies.

[0004] GaN is a relatively new technology compared to other semiconductors, such as Si and GaAs, but it has become the technology of choice for high-frequency, high-power applications, such as those required to transmit signals over long distances or at high power levels. GaN transistors offer high power density, high operating temperatures, improved efficiency, low on-state resistance, and they can operate in various frequency bands ranging from 1 GHz to 110 GHz.

[0005] Silicon-on-insulator (SOI) technology is used in semiconductor manufacturing, particularly in microelectronics, to reduce parasitic capacitance through a substrate structure of silicon-insulator-silicon layers (rather than bulk silicon). CMOS SOI allows for reduced power consumption in mixed analog and digital RF circuits in the design of low-power RF transceivers due to its low leakage.

[0006] To obtain some of the advantages of GaN and SOI, attempts have been made to grow GaN on SOI, using trench etching to isolate the GaN transistors. Microtransfer printing [1] can also be used to transfer a GaN device from a native / source wafer to a target SOI wafer. During this process, the GaN device is detached / lifted from the native wafer on which it was grown and reattached to the SOI wafer. Both the SOI devices and the GaN transistors are fabricated separately in their processing environment and can have different wafer diameters. Most of the circuit can be designed on SOI technology, while relatively few transistors are micro-transfer printed on top of the SOI wafer.

[0007] [1] R. Lemer, et al. "Heterogeneous Integration of Microscale Gallium Nitride Transistors by Micro-Transfer-Printing". 2016 IEEE 66th Electronic Components and Technology Conference, pp 1186-1189.

[0008] SUMMARY

[0009] Aspects of the present invention provide a semiconductor structure, a system and a method for forming a semiconductor structure as described in the attached claims.

[0010] Embodiments of the invention are described below with reference to the accompanying drawings. Brief description of the drawings

[0011] Fig. 1 shows a sequence of steps to release a chiplet during the micro-transfer printing process;

[0012] [Fig.2] shows a schematic cross-section of a semiconductor structure;

[0013] Fig. 3 shows a schematic cross-section of a semiconductor structure comprising a heat dissipation structure;

[0014] [Fig.4] shows a schematic top view of a semiconductor structure comprising a heat dissipation structure;

[0015] Fig. 5 shows a schematic top view of another semiconductor structure comprising a heat dissipation structure;

[0016] Fig. 6 shows a schematic cross-section of another semiconductor structure comprising a heat dissipation structure;

[0017] [Fig.7] shows a schematic cross-section of another semiconductor structure comprising a heat dissipation structure;

[0018] Fig. 8 shows a schematic cross-section of another semiconductor structure comprising a heat dissipation structure;

[0019] Fig. 9 shows a schematic cross-section of a semiconductor structure comprising a heat dissipation structure;

[0020] Figure 10 shows a schematic perspective view of a semiconductor structure comprising a heat dissipation structure;

[0021] Figure 11 shows a circuit diagram of an SPDT switch; and

[0022] Figure 12 shows a circuit diagram of a transistor printed by microtransfer connected to a target plate. DETAILED DESCRIPTION

[0023] Micro-transfer printing (pTP) allows monolithic designs with Shorter interconnections can avoid losses and transitions between chips and substrates. Interconnections are provided directly between the two stacked chips with metal (e.g., thick copper), called a redistribution layer (RDL). During microtransfer printing, one or more chiplets are peeled from the original substrate and attached to the target wafer. A chiplet, as mentioned above, is a (small) piece of chip from which the native substrate has been removed.

[0024] A potential problem with transfer printing technology is heat dissipation from the transfer-printed chiplet, which can lead to thermal breakdown of components at lower power levels and thus limit the power processing capacity of the components.The transfer-printed chiplet is thermally isolated from the target substrate, and the conventional technology of using silicon interconnect holes (TSVs) to direct heat away from the wafer is not compatible with micro-transfer printing technology.

[0025] The embodiments described in this document can at least partially solve this problem by improving heat transfer from the chiplet.

[0026] Fig. 1 illustrates some of the steps of a transfer printing process by releasing a chiplet 2 (e.g., a GaN chiplet) from a native silicon substrate 4. (A) The passivation layer 6 and the dielectric layers 8 of the base stack 10 are etched to reveal the underlying active layer 14 (i.e., the device layer) around the chiplet 2. (B) An etch (e.g., a GaN etch) is then performed to isolate the chiplet 2, followed by (C) the deposition of an encapsulation layer 16 (e.g., SiN) to protect the chiplet 2. (D) The encapsulation layer 16 is etched to reveal the top metal 18 of the chiplet 2 to form connections with the target wafer (not shown) after transfer printing. (E) Another etching is performed around the chiplet to reveal the underlying silicon 4 substrate, followed by (F) the release of chiplet 2 by etching the silicon 4 substrate under chiplet 2.After release, chiplet 2 can be transferred and attached to a target wafer (e.g., an SOI wafer). As part of the attachment process, an adhesion-enhancing layer can be provided on the target wafer. For example, a layer of adhesive can be deposited on the target wafer before delivering the chiplet to the target wafer.

[0027] Figure 2 shows a schematic diagram of a cross-section of a portion of a semiconductor structure 1 comprising a chiplet 2, being a GaN chiplet, attached to a target wafer 20, being a silicon-on-insulator (SOI) wafer. The same reference numerals have been used for the same or equivalent features in different figures for ease of understanding and are not intended to limit the embodiments illustrated. The chiplet 2 comprises an active layer 14, comprising one or more semiconductor devices such as transistors, a dielectric layer 8, a first passivation layer 6, and a second passivation layer 16. The chiplet 2 is attached to the target wafer 20 by an adhesion-enhancing layer 22, which is an adhesive layer (e.g., containing benzocyclobutene, BCB). A redistribution layer (RDL) 12 electrically connects the chiplet to the target wafer 20. In particular, the RDL 12 connects the top metal layer 18 of the chiplet 2 to a metal pad 24 (e.g., an aluminum pad) on the surface of the target wafer 20. The RDL may be 3 µm thick. The target wafer 20 comprises a top layer of silicon 26 (e.g., an epitaxial layer) and a silicon substrate 28 separated by a buried oxide layer (BOX) 30. The wafer 20 comprises a passivation layer 32 (e.g. SiON) covering the top layer of silicon 26.The top silicon layer 26 of the SOI 20 wafer is shown as a single layer, but it includes the base comprising metallic layers, dielectric layers to separate the metallization, and an active silicon layer to form semiconductor devices in the SOL wafer. The passivation layer 32 is open to expose the metallic pad 24. The structure, comprising both the chiplet, the RDL 12 and the SOI 20 wafer, is covered with a third passivation layer 34.

[0028] Figure 3 shows a schematic cross-section of a portion of another semiconductor structure 1. In addition to the features illustrated in Figure 2, the semiconductor structure 1 includes a thermal pin 36. The thermal pin 36 comprises a portion of the upper metal layer 18 of the chiplet 2 and an interconnect hole 38 connected to this portion of the upper metal layer 18 and terminating at or near the active layer 14 of the chiplet 2. The active layer 14 may include one or more semiconductor devices (e.g., transistors) of the chiplet 2, which dissipate heat during operation. The thermal pin 36 is arranged to transfer heat from the active layer 14 to a portion of the RDL 12, thereby reducing temperature buildup in the chiplet 2.This portion of the RDL 12 is in turn connected to an interface structure 42 comprising a connection pad 43 located in an opening in the passivation layer 34. An electronic package such as a PCB (not shown) can be connected to the RDL 12 via the interface structure 42. Preferably, the electronic package includes a heat sink that is configured to be connected to the RDL 12 and to the thermal pin 36 via the interface structure 42. For example, the semiconductor structure 1 can be thermally connected to the electronic package by soldering or by wire connection. Although the RDL 12 is also used to electrically connect the chiplet 2 to the wafer 20, the portion of the RDL 12 connected to the thermal pin 36 has no [other features]. The electrical connection in chiplet 2 or wafer 20 can be left floating. In other words, while other parts of the RDL 12 are electrically connected to semiconductor devices in the active layer 14 of chiplet 2 at one end, and to other semiconductor and / or passive devices in the target wafer 20 at the other end, the portion of the RDL 12 connected to the thermal pin 36 is part of a heat dissipation structure, which is not used for electrical connections. In other embodiments, the heat dissipation structure can be grounded. The heat dissipation structure further includes the third passivation layer 34, which comprises a thick layer of aluminum nitride (AIN). The passivation layer 34 can have a thickness greater than 5 µm, for example, 7 µm.The dielectric passivation layer 16 and chiplet 2 may also include AlN to further increase heat transfer from chiplet 2. In other embodiments, a different dielectric material with high thermal conductivity may be used.

[0029] Figure 4 shows a schematic top view of a portion of a semiconductor structure 1, such as the portion shown in Figure 2 or Figure 3. The structure 1 includes a transistor 44 comprising a gate pin 46, a source pin 48, and a drain pin 50. Each pin is connected to a corresponding portion of the RDL 12a-c, which connects the transistor 44 to the wafer 20. The structure 1 further includes a thermal pin 36 connected to another portion of the RDL 12d. This portion of the RDL 12d may have a relatively larger surface area compared to the other portions 12a-d in order to reduce thermal resistance. The portion of the RDL 12d connected to the thermal pin 36 is not electrically connected to any of the other portions of the RDL 12a-c and may be left floating.

[0030] Figure 5 shows a schematic top view of a portion of a semiconductor structure 1 comprising several thermal pins 36. Similar to structure 1 illustrated in Figure 4, structure 1 comprises a transistor 44 having a gate pin 46, a source pin 48, and a drain pin 50. Each pin is connected to a corresponding portion of the RDL 12a-c, which connects the transistor 44 to the wafer 20. Structure 1 further comprises five thermal pins 36 connected to other portions of the RDL 12d-f. These portions can be electrically connected to each other, but not to pins 46, 48, and 50.

[0031] Figure 6 shows a schematic cross-section of a portion of another semiconductor structure 1. In addition to the features of structure 1 illustrated in Figure 3, the heat dissipation structure further comprises a plurality of metallic layers 52 in the upper silicon layer 26 of the target SOI wafer 20 and connected by interconnect holes 54. The metallic layers 52 This further increases the total cross-sectional area of ​​the thermally conductive material between the chiplet 2 and the interface structure 42. For example, the combined height / thickness of the RDL and the plurality of metal layers 54 can be greater than 10 µm, for example, 12 µm. The target SOI 20 wafer comprises a plurality of metal pads 24 in openings in the passivation layer 32, connecting the plurality of metal layers 52 to the RDL 12 and thus indirectly to the thermal pin 36. In use, heat is conducted from the thermal pin 36 to the RDL 12, from the RDL 12 to the plurality of metal layers 52 in the target SOI 20 wafer, and from the plurality of metal layers 52 to the connecting pad 43 of the interface structure 42.Only a portion of each metallic layer 52 can constitute part of the heat dissipation structure, while other portions can be used to connect to semiconductor devices in the SOL wafer. Therefore, the heat dissipation structure includes a portion of the bottom stack of the target SOI 20 wafer.

[0032] Figure 7 shows a schematic cross-section of a portion of another semiconductor structure 1. The semiconductor structure 1 is similar to that shown in Figure 6, but includes a silicon through-hole interconnect (SLO) 56 connected to the plurality of metal layers 52 in the wafer 20. The SLO 56 is part of the interface structure 42 to which a PCB or other external component can be connected. The SLO 56 allows heat to be transferred from the chiplet 2 via the RDL 12 and the metal layers 52 out of the wafer 20.

[0033] Figure 8 shows a schematic cross-section of part of another semiconductor structure 1, in which the interface structure 42 comprises both a connection pad 43 in an opening of the upper passivation 34 to allow connection to the RDL 12 and a TSV 56 connected to the plurality of metal layers 52 of the target wafer 20. The upper passivation 34 comprises a thick layer (e.g. 7 pm) of AIN to further increase heat transfer from the chiplet 2. Figure 8 also shows a solder bump 58 connected to the RDL 12 via the connection pad 43 and forming part of the interface structure 42 for connection to a PCB (not shown).

[0034] Figure 9 illustrates a portion of another semiconductor structure, in which the thermal pin 36 is not connected to the metal RDL 12, but directly to a layer of AIN 60. The AIN 60 layer may be the upper passivation layer 34 or may be covered by the upper passivation layer 34. The AIN 60 layer is connected to a connection pad 43 of an interface structure 42 for connection to a PCB or other electronic package with a solder bump 58 and for transferring heat away from the wafer. The AIN 60 layer may also be in contact with the RDL 12 (not shown in Figure 9) to increase further the thermal conductivity between chiplet 2 and interface structure 42. The second passivation layer 16 on chiplet 2 may also include AlN, in order to further reduce the thermal resistance between chiplet 2 and interface structure 42.

[0035] Figure 10 shows a schematic perspective view of a semiconductor structure 1, comprising a chiplet 2 including a transistor 44 and gate, source, and drain pins 46, 48, and 50 for connection to the corresponding terminals of the transistor 44. The chiplet 2 is fixed to an SOI wafer 20 by a layer of adhesive 22. The adhesive layer 22 can reduce the heat dissipation of the transistor 44, and the chiplet therefore includes a heat dissipation structure 62 comprising a thermal pin 36 located in the chiplet 2 and a thermally conductive path 64 connected to the thermal pin 36 at one end and to an interface structure 42 including a copper pillar at the other end. The thermally conductive path may include a portion of an RDL layer or a thermally conductive dielectric layer (comprising, for example, AlN).

[0036] Figure 11 shows a circuit diagram of a single-pole, double-throw (SPDT) switch comprising a semiconductor structure as described herein. The heat dissipation structure allows the maximum power of the SPDT to be increased before thermal breakdown occurs. The regions indicated by dashed lines include circuit components from one or more chiplets that have been microtransfer printed onto the RF-SOI wafer.

[0037] Figure 12 shows a circuit diagram of a circuit 66 comprising a semiconductor structure as described herein. The circuit includes a transistor 44 and a thermal pin 36 (in the chiplet) and input and output impedance matching elements for connections to the target wafer. The circuit 66 can be part of a low-noise amplifier (LNA) and can be connected to the SPDT illustrated in Figure 11.

[0038] In general, the embodiments described herein can provide a semiconductor structure comprising a wafer, a chiplet attached to the wafer, and comprising a semiconductor device (for example, a transistor) and one or more metallic layers connected to the semiconductor device, an interface structure for connection to the wafer, and a heat dissipation structure for transferring heat from the chiplet to the interface structure. There may be limited heat transfer through the bottom of the chiplet into the wafer, and the heat dissipation structure can prevent thermal buildup and breakdown by increasing heat transfer from the chiplet. The chiplet is generally attached to the wafer by an adhesion-enhancing layer, such as an adhesive layer, and may include at least one material from among benzocyclobutene (BCB) and a photoelectric material such as InterVia™.

[0039] The chiplet may be a GaN chiplet comprising one or more GaN devices, such as field-effect transistors (FETs) or binary junction transistors (BJTs). In other embodiments, the chiplet comprises an element of GaAs, SiC, and InP. The wafer may be a silicon-on-insulator (SOI) wafer. The interface structure may include a silicon through-hole (TSV) through a buried oxide layer (BOX) of the SOL wafer. The semiconductor structure may consist of a bidirectional unipolar switching circuit (SPDT).

[0040] The heat dissipation structure may include a thermal pin located in the chiplet and comprising a portion of an upper metal layer of one or more metal layers of the chiplet, and an interconnect hole connected to that portion of the upper metal layer. The interconnect hole terminates at or near the active layer of the chiplet (near one or more semiconductor devices) in order to transfer the heat dissipated by the semiconductor device(s). The heat dissipation structure may include a plurality of thermal pins in the chiplet. Each thermal pin may include one or a plurality of interconnect holes to the active layer.

[0041] The heat dissipation structure may include at least a portion of a dummy metal layer consisting of a top metal layer of one or more metal layers of the chiplet. In this context, the term "dummy" refers to the fact that the dummy metal layer is not used to form electrical connections and does not (significantly) affect the performance of the final device. The semiconductor device normally includes a device metal layer for electrical connections to the semiconductor device (i.e., for electrical connections to doped regions in the active layer), and the dummy metal layer is not in contact with the device metal layer.The dummy metal layer and the device metal layer can advantageously be formed within the top metal layer of the semiconductor device's base stack and separated during the shaping of the top metal layer. The dummy metal layer does not form any electrical connection but increases the chiplet's mechanical strength, thereby reducing warping and preventing cracking during the microtransfer printing process. The dummy metal layer can be part of, or connected to, one or more of the chiplet's thermal pins.

[0042] The dummy metallic layer can have a thickness in the range of 0.3 pm and 4 pm, and preferably a thickness of 1.25 pm, which provides sufficient mechanical strength. Advantageous chiplet mechanical strength properties have been found for a dummy metal layer with a thickness in the range of 1 pm to 2 pm. For example, the gap between the dummy metal layer and the device metal layer can be at least 10 pm wide to avoid capacitive effects that could negatively affect device performance. For devices operating at frequencies below 5 GHz, a smaller gap can be used, while for high-frequency applications (e.g., > 20 GHz), a gap of at least 30 pm may be preferable. For GaN transistors, the device metal layer includes metal contacts such as source, drain, and gate contacts.

[0043] The dummy metal layer and the device's metal layer can be arranged so that the metal is distributed substantially uniformly over the chiplet. Uniform metal distribution on the chiplet can improve its mechanical properties and further reduce the occurrence of defects during microtransfer printing. To this end, the dummy metal layer can also be arranged substantially symmetrically on the chiplet. The dummy metal layer and / or the device's metal layer can exhibit x and / or y symmetry. To increase the chiplet's mechanical strength, it can be advantageous to cover a large portion of the chiplet's surface with metal. The dummy metal layer and the device's metal layer together can cover between 20% and 90% of the chiplet's total surface area.

[0044] The heat dissipation structure may include a portion of a redistribution layer (RDL) connected to the chiplet. The RDL may include metallic lines (e.g., Cu) having a thickness in the range of 1 pm to 5 pm.

[0045] Alternatively or in addition, the heat dissipation structure may include a dielectric layer that is thermally conductive (e.g., AIN). For example, the heat dissipation structure may include a portion of the upper passivation. The dielectric material may be an aluminum-based ceramic, such as Al₂O₃ or AIN, which exhibits good chemical stability and a low coefficient of thermal expansion (close to that of silicon). Various processes may be used to form the dielectric layer. For example, an alumina nanocomposite exhibiting good thermal conductivity may be formed as described in Kumari et al. [2] by chemical vapor deposition and spark plasma sintering. Electrolytic plasma oxidation (EPO) may also be used to form the dielectric layer. Such a process is described in T.E.S. Araujo et al. [3].PEO can be an environmentally friendly and inexpensive process for forming an oxide coating on a light metal. The process involves the application of a... A continuous voltage is applied to a sample in an electrolytic solution. Under lower voltages, ions containing primarily oxygen are attracted to the sample, resulting in the formation of an insulating oxide layer on the surface. The voltage is then increased to form complex structures involving species on the substrate and coating. The coatings can exhibit good adhesion and corrosion resistance.

[0046] [2] L. Kumari, T. Zhang, GH Du, et al. Compos. Sci. Technol. 68 (9) (2008) 2178-2183.

[0047] [3] Tamires ES Araûjo, Marcos Macias Mier, Alfredo Cruz Orea, Elidiane C. Rangel Nilson C. Cruz, Materials Letter: X 3 (2019) 100016.

[0048] The wafer generally comprises a plurality of metallic layers, such as the (M1, M2, M3, ..., MT0P) metals of the back end of the line (BEOL). The plurality of metallic layers can be connected to the active silicon layer (also known as the device layer) of the wafer to form and provide connections to the semiconductor devices within the wafer. The heat dissipation structure may include a portion of one or more of the metallic layers. For example, the heat dissipation structure may include a portion of each metallic layer of the plurality of metallic layers, in which the portions are connected by interconnect holes. This can allow for improved heat transfer across the wafer to the interface structure.

[0049] The heat dissipation structure may further include a passivation layer formed by the chiplet. For example, the upper passivation layer (also called the encapsulation layer) of the chiplet may comprise a thermally conductive material such as PAIN.

[0050] The interface structure may include a connection pad in an opening in a passivation layer on the wafer. Typically, the interface structure includes a connection to the RDL (Remote Distribution Layer) to enable bonding to the semiconductor structure. For example, the interface structure may include at least one of the following: a connection pad, a solder bump, a wire connection, a copper pillar, and a silicon through-hole (TSV). For example, the interface structure may include a TSV for connection to one side of the wafer and a connection pad for connection to the opposite side of the wafer. An electronic package including a heat sink can then be connected to the semiconductor structure via the interface structure.

[0051] The semiconductor structure may comprise a plurality of passivation layers including a first passivation layer constituted by the wafer, in which the chiplet is fixed to the first passivation layer, a second passivation layer constituted by the chiplet, and a third passivation layer covering the chiplet and the wafer.

[0052] Other embodiments provide a system comprising a semiconductor structure as described above and a printed circuit board (PCB) connected to the semiconductor structure by the interface structure. The system further comprises a heat sink attached to the PCB to dissipate the heat transferred through the interface structure.

[0053] This document also describes a method for forming a semiconductor structure. The method includes providing a chiplet comprising one or more semiconductor devices and a thermal pin comprising a portion of an upper metallic layer of the chiplet and an interconnect hole connected to the portion of the upper metallic layer, attaching the chiplet to a target wafer, forming a redistribution layer (RDL), and forming a passivation layer covering at least a portion of the RDL.

[0054] For example, the step of providing the chiplet may include a micro-transfer printing process, in which the chiplet is peeled from its original substrate. The chiplet may be coated with a passivation layer before being lifted. The passivation layer may comprise a thermally conductive dielectric material such as PAIN.

[0055] Although specific embodiments of the invention have been described above, it will be appreciated that other embodiments are possible. The above descriptions are intended to be illustrative and not limiting. It will be obvious to a person skilled in the art that modifications can be made to the invention as described without departing from the scope of the claims set forth below.

[0056] Each feature disclosed or illustrated in this specification may be incorporated into the invention, either alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

Demands

1. Semiconductor structure (1) comprising: a wafer (20); a chiplet (2) attached to said wafer (20) and comprising a semiconductor device (44) and one or more metal layers connected to said semiconductor device (44); a redistribution layer (12) electrically connecting the chiplet (2) to the target wafer (20); said redistribution layer (12) being connected to an upper metal layer (18) of the chiplet (2) and to a metal pad (24) located on the surface of the target wafer (20); an interface structure (42) for connecting an electronic package to the wafer (20); and a heat dissipation structure for transferring heat from the chiplet (2) to the interface structure (42).

2. Semiconductor structure (1) according to claim 1, wherein the wafer (20) is a silicon-on-insulator wafer, SOI.

3. Semiconductor structure (1) according to claim 1 or 2, wherein the heat dissipation structure comprises a thermal pin (36) located in said chiplet (2) and comprising a portion of an upper metal layer of said one or more metal layers of said chiplet and an interconnect hole (38) connected to said portion of the upper metal layer.

4. Semiconductor structure (1) according to claim 3, wherein the heat dissipation structure comprises a plurality of such thermal pins (36) in said chiplet (2).

5. Semiconductor structure (1) according to any one of the preceding claims, wherein said heat dissipation structure comprises at least a portion of a dummy metal layer consisting of an upper metal layer (18) of said one or more metal layers of said chiplet (2).

6. Semiconductor structure (1) according to any one of the preceding claims, wherein the heat dissipation structure comprises a portion of the redistribution layer (12) connected to said chiplet (2).

7. Semiconductor structure (1) according to claim 6, wherein said redistribution layer (12) comprises metallic lines having a thickness in the range of 1 pm to 5 pm.

8. Semiconductor structure (1) according to any one of the preceding claims, wherein said heat dissipation structure comprises a dielectric layer.

9. Semiconductor structure (1) according to claim 8, wherein said dielectric layer comprises an aluminum-based ceramic.

10. Semiconductor structure (1) according to claim 8 or 9, wherein said dielectric layer comprises an element of aluminium nitride, AIN, and aluminium oxide, A12O3.

11. Semiconductor structure (1) according to any one of the preceding claims, wherein said wafer (20) comprises a plurality of metallic layers (52), and wherein said heat dissipation structure comprises a portion of a metallic layer of said plurality of metallic layers (52).

12. Semiconductor structure (1) according to any one of claims 1 to 10, wherein said wafer (20) comprises a plurality of metallic layers (52) and wherein said heat dissipation structure comprises a portion of each metallic layer of said plurality of metallic layers and wherein said portions are connected by interconnecting holes.

13. Semiconductor structure (1) according to any one of the preceding claims, wherein said heat dissipation structure (6) comprises a passivation layer constituted by said chiplet (2).

14. Semiconductor structure (1) according to any one of the preceding claims, wherein said interface structure (42) comprises a connection pad (43) in an opening of a passivation layer (34) on said wafer (20).

15. Semiconductor structure (1) according to any one of claims 1 to 13, wherein said interface structure (42) comprises at least one of a connection pad (43), a solder bump (58), a wire link, a copper pillar and a silicon through-hole interconnect, TSV (56).

16. Semiconductor structure (1) according to any one of the preceding claims, further comprising a first passivation layer constituted by said wafer (20), in which said chiplet (2) is fixed to said first passivation layer (32), a second passivation layer (6) constituted by said chiplet (2), and a third passivation layer (34) covering said chiplet (2) and said plaque (20).

17. Semiconductor structure (1) according to any one of the preceding claims, further comprising an adhesion-enhancing layer (22) located between said chiplet (2) and said wafer (20).

18. System comprising: a semiconductor structure (1) according to any one of claims 1 to 17; a printed circuit board, PCB, connected to said semiconductor structure (1) by the interface structure (42); and a heat sink attached to the PCB to dissipate the heat transferred via said interface structure (42).

19. A method for forming a semiconductor structure, the method comprising the steps of: providing a wafer (20); providing an interface structure (42) for connecting an electronic package to the wafer (20); providing a chiplet comprising a semiconductor device (44) and one or more metal layers connected to said semiconductor device (44); fixing the chiplet (2) to said wafer (20); providing a heat dissipation structure for transferring heat from the chiplet (2) to the interface structure (42); forming a redistribution layer (12) electrically connecting the chiplet (2) to the target wafer (20); said redistribution layer (12) being connected to a top metal layer (18) of the chiplet (2) and to a metal pad (24) located on the surface of the target wafer (20).

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