Memory calculation device and method
Patent Information
- Application Number
- FR2023001691
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-02-24
- Publication Date
- 2025-03-21
- Estimated Expiration
- 2043-02-24
Smart Images
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Abstract
Description
Title of the invention: Device and method for computing in memory Technical field
[0001] The present description relates generally to electronic devices, and, more particularly, to electronic devices adapted to implement in-memory calculations (IMC from the English “In Memory Computing”). Prior art
[0002] Many known electronic applications or systems use devices adapted to implement calculations in memory. In these devices, calculations, for example multiplications and a summation of the results of the multiplications, are implemented at least in part directly in memory cells of a memory, preferably non-volatile, of the device.
[0003] Artificial intelligence (AI), artificial neural networks (ANN) and convolutional neural networks (CNN) are examples of applications using devices adapted to implement calculations in memory.
[0004] However, known devices suitable for implementing calculations in memory suffer from various drawbacks, for example with regard to errors in the calculations implemented by these known devices and / or the size of these devices. Summary of the invention
[0005] There is a need to overcome all or part of the drawbacks of known devices adapted to implement calculations in memory.
[0006] One embodiment overcomes all or part of the drawbacks of known devices adapted to implement calculations in memory.
[0007] For example, one embodiment provides a device suitable for implementing calculations in memory which has reduced calculation errors compared to known devices, for example when these calculation errors result from PVT (Process Voltage Temperature) variations.
[0008] For example, one embodiment provides a device suitable for implementing calculations in memory which has a reduced footprint compared to known devices, for example when these calculation errors result from PVT variations (from the English "Process Voltage Temperature" - manufacturing voltage temperature).
[0009] One embodiment provides a device comprising: memory cells each comprising a control input configured to receive a pulse width modulated control voltage and an output configured to provide an output current having a value at least partly determined by a level of the control voltage of the cell and by a weight programmed in said cell; a connection node configured to receive, for a first duration, the output currents of several cells among said cells; a first circuit having an input connected to the first node, the first circuit being configured to provide an output signal having a value determined by a total amount of current received by the input of the first circuit during the first duration; and for each cell of the plurality of cells, a second circuit configured to receive a digital word and to supply, during the first duration, the control voltage to said cell at a first level only during a second duration determined by said digital word.
[0010] According to one embodiment, each memory cell is configured so that the value of its output current is solely determined by the level of its control voltage and by the weight programmed in said cell.
[0011] According to one embodiment, each memory cell further comprises a selection input and is configured so that: the value of its output current is at a value, preferably zero, independent of the level of its control voltage and the weight programmed in said cell if its selection input receives a selection signal in a first state; and the value of its output current is determined by the level of its control voltage, the weight programmed in the cell and the state of the selection signal received by its selection input if the state of the selection signal is different from the first state.
[0012] According to one embodiment, the device further comprises a selection circuit configured to provide, to each cell of the plurality of cells, the cell selection signal.
[0013] According to one embodiment, each second circuit is configured so that the control voltage supplied by this second circuit comprises exactly two levels, said two levels comprising the first level.
[0014] According to one embodiment, the first node is connected to the output of each of the cells of the plurality of cells.
[0015] According to one embodiment, the device further comprises: a connection network having an output connected to the first node and inputs connected to the outputs of the cells of the plurality of cells; and a control circuit for said network configured, during the first duration, to control the network such that the first node receives the output current from each of the cells of the plurality of cells.
[0016] According to one embodiment, the first circuit comprises an integrator circuit configured to integrate the quantity of current received by the first circuit during the first duration and to provide a first signal determined by said integration.
[0017] According to one embodiment, the first signal is an analog signal and the first circuit further comprises an analog-to-digital converter configured to convert the first analog signal into a digital signal determining the output signal of the first circuit.
[0018] According to one embodiment, the first circuit comprises: - an oscillator having an oscillation frequency determined by a total current available on the first node, and - a counter configured to provide a digital signal having a value determined by a counted number of oscillations during the first duration, the output signal of the first circuit being determined by the digital signal provided by the counter.
[0019] According to one embodiment, the first duration is equal to K times a clock period, with K a constant number, and, for each cell of the plurality of cells, the second duration is equal to Q times the clock period, with Q a number less than or equal to the number K.
[0020] According to one embodiment, the numbers K and Q are integers.
[0021] According to one embodiment, each second circuit comprises a counter configured for: - receive the digital word received by said second circuit, - count, during the first duration, a number of periods of the clock, and - provide, during the first duration, an output signal in a first binary state if the counted number of periods is less than a value determined by said digital word, and in a second binary state otherwise, said second circuit being further configured to provide said control voltage at the first level if the output signal of the counter is in the first binary state.
[0022] According to one embodiment, the number K is determined by a maximum value of the digital words and, for each cell of the plurality of cells, the number Q is determined by a value of the digital word received by the second circuit supplying the control voltage to said cell.
[0023] One embodiment provides a method implemented in a device comprising memory cells each comprising a control input. configured to receive a control voltage and an output configured to provide an output current having a value at least partly determined by a level of the control voltage of the cell and by a weight programmed in said cell, the method comprising, for a first duration: providing a connection node with the output currents of a plurality of cells among the cells of the device; providing with a first circuit having an input connected to the first node, an output signal having a value determined by a total amount of current received by the input of the first circuit during the first duration; and for each cell of the plurality of cells, receiving a digital word with a second circuit and providing with the second circuit the control voltage of the cell at a first level only for a second duration determined by the received digital weight. Brief description of the drawings
[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0025] [Fig.l] represents, schematically and in the form of blocks, an example of a device adapted to implement calculations in memory;
[0026] [Fig.2] represents, schematically and in the form of blocks, an example of an embodiment of a device suitable for implementing calculations in memory;
[0027] [Fig.3] represents, schematically and in the form of blocks, an exemplary embodiment of a circuit of the device of [Fig.2];
[0028] [Fig.4] represents, schematically and in the form of blocks, an example of an embodiment of another circuit of the device of [Fig.2];
[0029] [Fig. 5] represents, schematically and in the form of blocks, another example of an embodiment of a device adapted to implement calculations in memory; and
[0030] [Fig. 6] represents, schematically and in the form of blocks, an alternative embodiment of the devices of figures 2 and 5. Description of the embodiments
[0031] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the cells usual memories used in the devices described to implement calculations in memory have not been described in detail, the embodiments and variants described being compatible with these usual memory cells. In addition, the usual electronic systems and usual applications (AI, ANN, CNN) in which one or more devices adapted to implement calculations in memory are used have not been detailed, the embodiments and variants described being compatible with these usual systems and applications.
[0033] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0035] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0036] [Fig.l] represents, schematically and in the form of blocks, an example of a device adapted to implement calculations in memory.
[0037] The device 1 comprises N identical memory cells Ci, with N an integer greater than or equal to 2, and i an integer index ranging from 1 to N. In the example of [Fig.l], N is equal to four and the device therefore comprises N memory cells C1, C2, C3 and C4. The N memory cells Ci are for example part of a memory of the device 1 comprising M memory cells identical to the cells Ci, with M an integer greater than or equal to N.
[0038] Each cell Ci comprises a control input configured to receive a control voltage Vi_a, with i integer index ranging from 1 to N (Vl_a, V2_a, V3_a and V4_a in [Fig.l]).
[0039] Each cell Ci further comprises an output providing a current li, with i being an integer index ranging from 1 to N (II, 12, 13 and 14 in [Fig.l]). For each cell Ci, the current li has a value determined by the value of the voltage Vi_a received by the cell Ci and by a weight Wi programmed in the cell Ci, for example a value equal to the product of the voltage Vi_a by the weight Wi. For example, the programming of a weight Wi in a cell Ci corresponds to a programming of a resistance value of the cell or of a polarization current of the cell.
[0040] The outputs of the N cells Ci are all connected to the same connection node 100. The node 100 therefore receives the currents li from the N cells Ci.
[0041] The device 1 further comprises, for each of the N cells Ci, a digital-to-analog converter DACi, with i integer index ranging from 1 to N (DAC1, DAC2, DAC3 and DAC4 in [Fig.l]). Each converter DACi is configured to receive a digital word Vi_n (Vl_n, V2_n, V3_n and V4_n in [Fig.l]), that is to say a value coded in the form of a digital word, therefore of several bits. Each converter DACi is further configured to supply to the corresponding cell Ci (having the same index i) the control voltage Vi_a of the cell Ci, so that the value of the voltage Vi_a is determined by the digital word Vi_n. In other words, each converter DACi is configured to convert the digital word Vi_n that it receives into the analog voltage Vi_a that it supplies to the cell Ci.
[0042] By way of example, the device 1 comprises a circuit 102 configured to provide the digital words Vi_n to the DACi converters. By way of example, these digital words Vi_n are the results of a previous calculation, for example a calculation implemented by a previous layer of a neural network.
[0043] The device 1 further comprises a digital-to-analog converter ADC. The ADC converter has an input connected to the node 100. Thus, the input of the ADC converter receives a current IS equal to the sum of the currents li. The ADC converter is configured to provide a digital output word V_n corresponding to the result of the analog-to-digital conversion of the current IS.
[0044] Thus, in operation, the device 1 allows the implementation of a calculation in memory consisting of N multiplications Vi_n*Wi, that is to say N multiplications Vi_a*Wi, and the summation of the result of the N multiplications. The result of this sum, namely the current IS in [Fig.l], is then converted by the ADC circuit to obtain the word V_n.
[0045] However, in device 1, the more the multiplication number N increases, the more the number of DACi converters, and therefore the size of device 1, increases.
[0046] Furthermore, the ADC circuit for converting the current IS into the digital word V_n is sensitive to PVT variations, hence errors related to PVT variations can be introduced into the result V_n by the ADC converter. In the same way, the DACi circuits are sensitive to PVT variations, hence errors related to PVT variations can be introduced into the values of the voltages Vi_a, and therefore into the result V_n.
[0047] Furthermore, when the digital words Vi_n can take X distinct values, with X strictly greater than 2, not only must the DACi converters have sufficient precision, or resolution, to provide analog control voltages Vi_a which can take X corresponding distinct values, and, in addition, each cell Ci must be able to provide, for each weight value Wi that can be programmed in this cell, a current li that can take X corresponding distinct values, which makes the device 1 complex to implement. In particular, this implies providing an ADC circuit with sufficient resolution.
[0048] A device and method are provided herein for implementing memory calculations in which memory cells similar to the preceding cells Ci are each controlled by a binary control voltage modulated in pulse width on the basis of the value of the corresponding digital word.
[0049] This makes it possible to avoid the use of digital-to-analog converters to generate the cell control voltages from the digital words.
[0050] This also makes it possible to simplify the implementation of a circuit of the device providing a signal representative of the result of the calculation in memory from the output currents of the cells, and / or to make this circuit more robust to P VT variations.
[0051] [Fig.2] represents, schematically and in the form of blocks, an exemplary embodiment of a device 2 adapted to implement calculations in memory.
[0052] Similar to device 1, device 2 comprises N identical memory cells Ci, with N an integer greater than or equal to 2, and i an integer index ranging from 1 to N. In the example of [Fig.2], N is equal to four and the device therefore comprises N memory cells C'1, C'2, C'3 and C'4.
[0053] The N memory cells Ci are, for example, part of a memory of the device 2 comprising M memory cells identical to the cells Ci, with M an integer greater than or equal to N.
[0054] By way of example, when the device 2 comprises a number M of memory cells identical to the N memory cells Ci, with M strictly greater than N, the M cells are for example arranged in a matrix of memory cells comprising rows and columns of memory cells. In this case, the N cells Ci are, for example, part of the same column of the matrix.
[0055] However, in other examples, the N cells Ci' may be part of different rows and / or columns of the matrix of M cells.
[0056] Each cell Ci comprises a control input configured to receive a control voltage Vi_pwm, with i integer index ranging from 1 to N (V l_pwm, V2_pwm, V3_pwm and V4_pwm in [Fig.2]). The Vi_pwm voltages are voltages taking only two levels, namely a first high level and a second low level. Preferably, the low level of each Vi_pwm voltage corresponds to a zero Vi_pwm voltage.
[0057] The control input of each cell Ci corresponds for example to a row selection input of a matrix of M cells identical to the cells Ci'. In this case, all the cells of the same row of the matrix receive, for example, the same voltage Vi_pwm, the latter being supplied to the cells of the row of the matrix by a conductive line, for example called a word line, connected to the control input of each of the cells of this row of the matrix.
[0058] To supply, for a first duration DI, the control voltages Vi_pwm to the N cells Ci from the digital words Vi_n, the device 2 comprises, for each cell Ci, a circuit PWMi, with i integer index ranging from 1 to N (PWM1, PWM2, PWM3, PWM4 in [Fig.2]).
[0059] Each PWMi circuit is configured to receive the corresponding digital word Vi_n, and to supply, during the duration Dl, the corresponding control voltage Vi_pwm to the cell Ci concerned.
[0060] Each PWMi circuit is configured so that, during the duration D1, the voltage Vi_pwm is at its first high level for a second duration D2 determined by the digital word Vi_n, that is to say by the value of the digital word Vi_n.
[0061] For example, for each voltage Vi_pwm, the ratio of the duration D2 to the duration D1 is minimal and zero when the corresponding word Vi_n is zero, i.e. represents a zero value, and this ratio D2 / D1 is maximal and equal to 1 when the word Vi_n is maximal, i.e. represents a maximum value. In other words, during the duration D1, the duty cycle D2 / D1 of each voltage Vi_pwm is determined by the value of the corresponding digital word Vi_n.
[0062] For example, in the device 2, the words Vi_n are supplied to the circuits PWMi by a control circuit CTRL of the device 2. For example, when the N cells Ci are part of a matrix of M identical cells, the circuit CTRL is a circuit for controlling the rows of the matrix.
[0063] In the device 2, for each memory calculation implemented, the duration Dl is constant and common to all N cells Ci involved in the memory calculation.
[0064] According to one embodiment, although this is not illustrated in [Fig.2], the duration D1 corresponds to a constant number K of cycles of a clock clk of the device 2. Preferably, the number K is an integer which simplifies the implementation of the device 2 compared to a case where the number K is a decimal number.
[0065] In such an embodiment, for each cell Ci, the duration D2 of the first high level of the corresponding control voltage Vi_pwm corresponds to a number Q of the period of the clock clk of the device 2. Preferably, the number Q is an integer which simplifies the implementation of the device 2 compared to a case where the number K is a decimal number.
[0066] However, in alternative embodiments, the voltages Vi_pwm, which each have a duration ratio D2 / D1 determined by the corresponding word Vi_n, are generated with usual circuits for generating a pulse width modulated voltage and the durations DI and D2 then do not necessarily correspond to numbers respectively K and Q of periods of a clock clk of the device 2.
[0067] Preferably, when the durations DI and D2 correspond to respective numbers K and Q of periods of the clock clk of the device 2, the number K is determined by the maximum value taken by the words Vi_n, and the number Q is determined, for each cell Ci, or, in other words, for each circuit PWMi, by the value of the word Vi_n received by this circuit PWMi.
[0068] Preferably, when the durations DI and D2 correspond to integers respectively K and Q of the period of the clock clk, the number K is equal to the total number of values that each word Vi_n can take minus 1. In this case, each value of the word Vi_n corresponds to an integer value of Q between 0 and K1, for example a zero value when the word Vi_n is zero, and a maximum value equal to K when the word Vi_n is maximum. This further simplifies the implementation of the device 2.
[0069] Each cell Ci further comprises an output providing a current Ii_pwm, with i integer index ranging from 1 to N (Il_pwm, I2_pwm, I3_pwm and I4_pwm in [Fig.2]). Each cell Ci is configured to provide the current Ii_pwm at a value at least partly determined by the product of the voltage Vi_pwm that it receives with the weight Wi programmed in the cell. Preferably, when a cell Ci receives a voltage Vi_pwm at the low level, the current Ii_pwm that it provides is zero.
[0070] According to one embodiment, each cell Ci is configured to provide a current Ii_pwm at a value determined solely by the level of the voltage Vi_pwm that it receives and by the weight Wi programmed in the cell.
[0071] As a variant not illustrated in [Fig.2], each cell Ci further comprises a selection input. The selection input of the cell Ci is configured to receive a selection signal, preferably a selection voltage.
[0072] In such a variant, each cell Ci is configured to provide a current Ii_pwm having a value determined by the level of the voltage Vi_pwm that it receives, by the weight Wi programmed in the cell and by the value of the selection voltage that it receives, for example a value determined by the product of the voltage Vi_pwm, the weight Wi and the selection voltage of the cell.
[0073] This selection input of each cell Ci corresponds, for example, to a column selection input when the cells Ci are part of a matrix of M cells. In this case, all the cells of the same column of the matrix receive, for example, the same selection voltage, the latter being supplied to the cells of the column of the matrix by a conductive line, for example called a bit line. ("bitline" in English), connected to the selection input of each of the cells in that column of the matrix.
[0074] Preferably, in such a variant, each cell Ci is configured to provide its current Ii_pwm at a zero value if the selection signal that it receives is in a first state, for example a first state corresponding to a zero value of the selection signal.
[0075] For example, when the selection signal supplied to a cell Ci can take at least two other states in addition to the first state, this makes it possible to weight the value of the weight Wi programmed in the cell with the selection signal of this cell.
[0076] The device 2 comprises a connection node 200. The node 200 is configured to receive, during the first duration D1, that is to say during the entire duration D1, the output currents Ii_pwm of the N cells Ci.
[0077] According to one embodiment, as illustrated in [Fig.2], the node 200 is connected to the outputs of all the N cells Ci, the node 200 being further able to be connected to outputs of other memory cells among the M memory cells of the device 1.
[0078] As a variant not illustrated in [Fig.2], the node 200 is coupled to the outputs of the N cells Ci by a connection network having inputs connected to the outputs of N cells Ci and, for example, to outputs of other memory cells among the M cells of the device 2.
[0079] The device 2 then comprises a connection network control circuit configured to control the connection network so that, during the duration D1, that is to say during the entire duration D1, the node 200 receives the output currents Ii_pwm of the N cells Ci. By way of example, when the connection network is connected to the outputs of memory cells other than the N cells Ci, the connection network control circuit is further configured so that, during the entire duration D1, the outputs of these other memory cells are electrically isolated from the node 200 by the connection network.
[0080] The device 2 also comprises an INT / ADC circuit. An input 202 of the INT / ADC circuit is connected to the node 200. Thus, the INT / ADC circuit receives, during the duration D1, the sum IS_pwm of the output currents Il_pwm, I2_pwm, I3_pwm and I4_pwm supplied by the N cells C'l, C'2, C'3 and C'4 which have their outputs electrically coupled to the node 200 during the duration DL. The INT / ADC circuit is configured to provide, from the sum IS_pwm of the currents Ii_pwm that it receives from the node 200, a signal V_n having a value determined by a total quantity of current IS_pwm received by its input 202 during the entire duration DL. Preferably, the signal V_n is a digital word, i.e. a digital signal on several bits, coding a value determined by the total amount of current received by input 202 of the circuit during the entire period Dl.
[0081] According to one embodiment, to provide the signal V_n from the total quantity of current IS_pwm received by its input 202 during a duration D1, the INT / ADC circuit comprises an integrator circuit (not shown in [Fig.2]) configured to integrate the quantity of current IS_pwm received during the entire duration D1, that is to say to calculate, or determine, the total quantity of current received by the input 202 during the period D1. The integrator circuit then provides a signal representative of the total quantity of current received by its input 202 during the period D1.
[0082] By way of example, the integrator circuit is an analog circuit having an input coupled, preferably connected, to the input 202 of the INT / ADC circuit. In this case, the signal provided by the integrator circuit is an analog signal. The INT / ADC circuit may then comprise an analog-to-digital converter configured to provide a digital word resulting from the analog-to-digital conversion of the output signal of the integrator circuit, and the signal V_n is determined from this digital word. Alternatively, the signal V_n is an analog signal determined by the output signal of the integrator circuit and the INT / ADC circuit is devoid of an analog-to-digital converter.
[0083] As an alternative example, the integrator circuit is a digital circuit. In this case, the INT / ADC circuit comprises an analog-to-digital converter having an input coupled, preferably connected, to the input 202 of the INT / ADC circuit, and which converts the signal IS_pwm received during a duration D1 into digital samples at a higher acquisition frequency, for example at least 10 times higher, than the inverse of the duration DL. The digital integrator circuit receives these digital samples and integrates them, i.e. here sums them, to provide a digital signal representative of the total quantity of current IS_pwm received during this duration DL. The signal V_n is then a digital signal determined from the digital output signal of the integrator circuit.
[0084] As an alternative embodiment, to provide the signal V_n from the total quantity of current IS_pwm received by its input 202 for a duration D1, the INT / ADC circuit comprises an oscillator (not shown in [Fig.2]), having an oscillation frequency determined by the current IS_pwm received by the input 202. For example, the oscillator is powered by the current IS_pwm, so that when the value of the current IS_pwm changes, the frequency of the oscillations changes correspondingly. The oscillator is for example a ring oscillator. In such an alternative, the INT / ADC circuit further comprises a counter configured to provide a digital output signal having a value determined by a counted number of oscillations of the oscillator during this duration D1, i.e. during this entire duration Dl. Thus, the number of oscillations counted is representative of the total amount of current IS_pwm received during the duration Dl, and the output signal V_n of the INT / ADC circuit is then determined from the output signal of the counter.
[0085] Whereas in device 1, the instantaneous value of the current li of each cell Ci is representative of the product of the voltage Vi_a (therefore of the value of the word Vi_n) by the weight wi programmed in this cell, in device 2, because the voltages Vi_pwm are voltages modulated in pulse width on the basis of the words Vi_n, it is the total quantity of current Ii_pwm supplied by each cell Ci over the entire duration Dl which is representative of the product of the voltage Vi_pwm (therefore of the value of the word Vi_n) by the weight Wi programmed in this cell.
[0086] This makes it possible to simplify device 2 compared to device 1 because the Vi_pwm voltages only take two levels unlike the Vi_a voltages.
[0087] Furthermore, this makes it possible to make the device 2 less bulky than the device 1 because the N DACi circuits are replaced by N PWMi circuits and the PWMi circuits are less bulky than the DACi circuits.
[0088] This also makes it possible to improve the accuracy of the calculation, because the PWMi circuits, and therefore the Vi_pwm voltages, are less sensitive to PVT variations than the DACi circuits, and therefore the Vi_a voltages.
[0089] [Fig. 3] represents, schematically and in the form of blocks, an exemplary embodiment of a PWMi circuit of the device 2 of [Fig. 2], in the case where the durations D1 and D2 correspond to numbers K and Q of periods of a clock clk of the device 2 of [Fig. 2]. Preferably, all the PWMi circuits are identical.
[0090] In this exemplary embodiment, the circuit PWMi comprises a counter COUNTER clocked at the frequency of the clock clk. The circuit PWMi and the counter COUNTER then each receive the clock clk. The counter COUNTER also receives the digital word Vi_n. To know the start of the duration Dl, the circuit PMW_i and the circuit COUNTER each receive a signal start indicating, for example by switching between two states of the signal start, the start of each duration DL
[0091] During each duration D1, the counter COUNTER is configured to count the number of periods of the clock clk. As long as the counted number is less than a value determined by the word Vi_n, the counter COUNTER provides a binary signal sig2 in a first state, and in a second binary state otherwise, that is to say as soon as the counted number of periods of the clock clk reaches this value or is greater than this value.
[0092] The Vi_pwm signal is then determined from the sig2 signal.
[0093] For example, when the first state of signal sig2 is a high state and the second state of signal sigl is a low state, signal Vi_pwm corresponds to, or is equal to, the signal sig2. In other words, the Vi_pwm voltage is at its first high level if the sig2 signal is in its first binary state, and the Vi_pwm voltage is at its second low level if the sig2 signal is in its second binary state.
[0094] As an alternative example, when the first state of signal sig2 is a low state and the second state of signal sigl is a high state, signal Vi_pwm corresponds to, or is equal to, a complementary (or inverse) signal of signal sig2.
[0095] As another alternative example, the voltage Vi_pwm is obtained at the output of a circuit, for example a voltage divider bridge, configured to adapt the values of the high and low levels of the voltage Vi_pwm relative to the level of the first and second binary states of the signal sig2 or its binary complement.
[0096] The person skilled in the art will be able to provide other implementations of the PWMi circuit from a counter. For example, the word Vi_n can be supplied to a digital comparator also receiving a digital output word from the counter indicating the number of periods of the clock clk counted since the start of a period DI indicated by the signal start. For example, the counter is reset to zero at the start of each duration DI and the comparator provides a binary signal in a first state as long as the digital output word of the counter is less than the word Vi_n, and in a second binary state otherwise, the voltage Vi_pwm being determined from the binary output signal of the comparator.
[0097] [Fig.4] represents, schematically and in the form of blocks, an example of embodiment of the INT / ADC circuit of device 2 of [Fig.2].
[0098] More particularly, [Fig.4] illustrates an exemplary embodiment described previously in relation to [Fig.2], in which: - the INT / ADC circuit comprises an integrator circuit INT configured to integrate the quantity of current IS_pwm received during the duration Dl, and to provide an analog signal sig3 representative of this integration, that is to say of the result of this integration; and - the INT / ADC circuit may comprise an analog-to-digital converter ADC configured to provide a digital word resulting from the analog-to-digital conversion of the output signal sig3 of the integrator circuit, the signal V_n being determined from this digital output word of the ADC converter, for example being equal to this digital output word of the ADC converter.
[0099] [Fig.5] represents, schematically and in the form of blocks, another example of an embodiment of the device 2.
[0100] In this example, the device 2 comprises M identical memory cells C'ku, with k an integer index ranging from 1 to P and u an integer index ranging from 1 to L and M equal to L times P. The cells C'ku are identical to the cells Ci described previously in relation to [Fig.2].
[0101] Furthermore, the C'ku cells are organized into a matrix of P rows (horizontal in [Fig.5]) and L columns (vertical in [Fig.5]).
[0102] In the example of [Fig.5], P equals 4 and L equals 3, therefore M equals 12.
[0103] In this example, in each row, each cell C'ku of the row of index k receives the same control voltage Vk_pwm on its control input, with k integer index ranging from 1 to P.
[0104] Thus, in the particular example of [Fig.5], the cells C11, C'12 and C'13 of the row with index k equal to 1 each receive the same control voltage V l_pwm, the cells C'21, C'22 and C'23 of the row with index k equal to 2 each receive the same control voltage V2_pwm, the cells C'31, C'32 and C'33 of the row with index k equal to 3 each receive the same control voltage V3_pwm, and the cells C'41, C'42 and C'43 of the row with index k equal to 4 each receive the same control voltage V4_pwm.
[0105] In this exemplary embodiment, the device 2 therefore comprises a PWMk circuit per line, with k an integer index ranging from 1 to P.
[0106] In the particular example of [Fig.5], the device 2 therefore comprises a PWM1 circuit providing the voltage Vl_pwm from the digital weight Vl_n, a PWM2 circuit providing the voltage V2_pwm from the digital weight V2_n, a PWM3 circuit providing the voltage V3_pwm from the digital weight V3_n, and a PWM4 circuit providing the voltage V4_pwm from the digital weight V4_n.
[0107] The set of PMWk circuits taken with a CTRL circuit providing the digital words Vk_n, with k integer index ranging from 1 to P, form, for example, a control circuit for the P lines of the matrix.
[0108] In this exemplary embodiment, N memory cells of the same column, here the column with index u equal to 3, are used to implement a calculation in memory. In the particular example of [Fig. 5], N is equal to 3 and the cells C'13, C'23 and C'33 are used to implement a calculation in memory. These N cells C'ku then have their outputs coupled, for example connected in the example of [Fig. 5], to the same node 500. The node 500 is, like the node 200 described previously in relation to [Fig. 2], configured to receive the output currents of the N cells C'ku during the duration DI corresponding to the calculation in memory using these N cells.
[0109] Further, an INT / ADC circuit has its input 202 connected to node 500.
[0110] Thus, during a period DI corresponding to this calculation in memory, the control voltages Vk_pwm are supplied to the N cells C'ku, the N cells C'ku then supply the output currents Iku_pwm (I13_pwm, I23_pwm and I33_pwm in the particular example of [Fig.5]) to the node 500, and the INT / ADC circuit connected to the node 500 provided the signal V_n from the total amount of current received by its input 202 during this period Dl.
[0111] As an example, as shown in [Fig.5] for the column with index u equal to 3, all cells C'uk of the same column have their outputs connected to the same node, node 500 in this example, itself connected to input 202 of an INT / ADC circuit. In particular, as shown in [Fig.5] by dotted lines, cell C'43 is connected to node 500 while it does not participate in the calculation implemented in memory involving the N cells C'13, C'23, C'33. In this case, so that a cell C'ku of the column not participating in the calculation in memory, namely cell C'43 in the particular example of [Fig.5], does not distort the result of the calculation, it must not, during the duration Dl, provide an output current I43_pwm to node 500 or provide a zero output current I43_pwm to node 500.
[0112] For this, the corresponding word V4_n is set to a minimum value, for example zero, so that the voltage V4_pwm remains at its second low level for the entire duration D1, from which it follows that the current I43_pwm remains zero for the entire duration D1.
[0113] As an alternative example, in each column, the cell or cells which do not participate in the implementation of a memory calculation involving the other cells of the column are not connected to the connection node which is connected to the input 202 of the INT / ADC circuit. Taking the particular example of [Fig. 5], the cell C'43 is then not connected to the node 500.
[0114] Preferably, in an embodiment where the M cells are organized in a matrix of P rows and L columns, and where all the cells of the same row receive, at each duration D1, the same row control voltage Vk_pwm, with k the index of this row, the cells C'ku of the matrix further comprise a column selection input as described previously. In this case, the cells of the same column receive for example the same selection signal selu, with u an integer index ranging from 1 to L.
[0115] For example, as shown in [Fig.5], the cells of the column with index u equal to 1 receive the signal sell, the cells of the column with index u equal to 2 receive the signal sel2 and the cells of the column with index u equal to 3 receive the signal sel3. As an example, the signals selu are provided by a SEL circuit of the device 2, for example a column control SEL circuit.
[0116] Thus, when implementing a memory calculation involving cells of a single column of index u, the cells of this column receive a selection signal selu at a value allowing the cells of this column to provide output currents determined by the control voltages Vk_pwm received by the cells of this column and by the weights programmed in these cells. Conversely, the memory cells of the other columns of the matrix receive selection signals selu at a value forcing the output current supplied by each of these cells to a constant and zero value regardless of the level of the control voltage Vk_pwm received by this cell.
[0117] Although not illustrated in [Fig.5], the device 2 may comprise more than one INT / ADC circuit, for example exactly one INT / ADC circuit per column of the matrix. For example, in the device 2 of [Fig.4], in each column of the matrix, the outputs of all cells in the column are then connected to the INT / ADC circuit of that column.
[0118] Alternatively or additionally, for each column, the device 2 may comprise several INT / ADC circuits, for example a first INT / ADC circuit connected or coupled to the outputs of first memory cells of the column and a second INT / ADC circuit connected or coupled to the outputs of second memory cells of the column. This makes it possible, for example, to simultaneously implement several calculations in memory during the same duration DI and with the cells of a single column. For example, using the device 2 of [Fig. 5], rather than connecting the output of cell C'43 to the INT / ADC circuit shown, the output of this cell is connected to another INT / ADC circuit.
[0119] In the example shown in [Fig.2], respectively in [Fig.5], the outputs of all the memory cells Ci, respectively C'ku, participating in the implementation of a calculation in memory during a corresponding duration DI are connected to the node 200, respectively 500, itself connected to the input 202 of a corresponding INT / ADC circuit.
[0120] However, it may be desirable, in order to make the device 2 reconfigurable in a simple manner, that the memory cells which provide, for a given duration DI, output currents to a node connected to the input 202 of a corresponding INT / ADC circuit, may be at least partly different from the memory cells which provide, for another duration D1, output currents to this same node.
[0121] For this, as has already been mentioned in relation to [Fig.2], each INT / ADC circuit of the device 2, and, more broadly, each connection node, for example 200 in [Fig.2] and 500 in [Fig.5], configured to receive the output currents of N memory cells of the device 2 during a duration D1 of the implementation of a calculation in memory, can be coupled to the outputs of these N cells and, for example, to the outputs of one or more other cells among the M cells of the device 2 by a connection network controllable by a network control circuit.
[0122] In this case, the connection network has inputs connected to the outputs of these cells, and an output connected to the connection node. The control circuit of the connection network is then configured, for the duration D1, to control the network so that the connection node receives the output current from each of the N cells involved in the memory calculation implemented during this duration D1. The network control circuit is further configured, during the duration D1, to control the network so that the outputs of the other memory cells which are connected to the inputs of the network and which are not involved in the memory calculation implemented during this duration D1 are electrically isolated from the connection node. In other words, the network R and / or its control circuit are configured so that, during a duration D1, the connection node connected to the output of the network R receives the output currents only from the memory cells involved in the memory calculation corresponding to this duration D1.
[0123] [Fig. 6] represents, schematically and in the form of blocks, an alternative embodiment of the devices 2 of figures 2 and 5, in the case where the device 2 comprises a connection network R as described above, it being understood that the device 2 can comprise more than one network R, for example one network R per INT / ADC circuit of the device 2.
[0124] The particular example of [Fig.6] corresponds to the particular example of [Fig.5] in which, for a duration D1, the cells C'13, C'23 and C'33 are involved in the implementation of a calculation in memory and where the cell C'43 is not and must not provide output current I43_pwm to the node 500.
[0125] The network R then comprises four inputs connected to the respective outputs of the cells C'13, C'23, C'33 and C'43, and one output connected to the node 500, itself connected to the input 202 of the INT / ADC circuit.
[0126] The device 2 further comprises a circuit R_CTRL for controlling the network R. The circuit R_CTRL provides the network R with a control signal sig4. The signal sig4, for example a digital word on several bits, determines for a given period D1 which of the inputs of the network R are electrically coupled to the output of the network R by the network R, and which of the inputs of the network R are electrically isolated from the output of the network R.
[0127] By way of example, the network R comprises, for each of its inputs connected to the output of a corresponding cell C'ku, a switch IT connected between this input of the network and the output of the network R. The switches are controlled by the signal sig4. The person skilled in the art will however be able to provide other examples of implementation of the network R.
[0128] In the particular example of [Fig.6], for the entire duration D1 of a memory calculation using cells C'13, C'23 and C'33, the control circuit R_CTRL controls the network R so that the output of each of these cells is electrically coupled to the output of the network, so that the output currents supplied by these cells are supplied to node 500 where they are added. Furthermore, for this same duration D1, the circuit R_CTRL controls the network R so that its input connected to the output of cell C'43 is electrically isolated from the output of network R, and therefore from node 500.
[0129] In the example of [Fig.6] where the network R is implemented by IT switches, the IT switch connected between the output of cell C13 and node 500, the IT switch connected between the output of cell C'23 and node 500, and the IT switch connected between the output of cell C'33 and node 500 are put in the on state by the circuit R_CTRL for the entire duration DI of the calculation in memory, and the IT switch connected between the output of cell C'43 and node 500 is put in the on state for this entire duration D1.
[0130] Although in the example of [Fig.6] the cells C'13 to C'43 which have their outputs connected to corresponding inputs of the array R are all part of the same column, this is not a necessity. Indeed, the array R of the device 2 can have inputs connected to any of the M memory cells of the device 2, for example to cells of two different columns of the matrix.
[0131] The embodiments and variants of devices 2 described above in relation to Figures 2 to 6 allow the implementation of a memory calculation method. The method then comprises, for a duration D1, the following steps: providing a connection node (200 in [Fig. 2], 500 in Figures 5 and 6) with the output currents of a plurality N of cells among the M cells of the device; providing, with an INT / ADC circuit having an input 202 connected to the connection node, an output signal V_n having a value determined by a total quantity of current IS_pwm received by this input 202 of the INT / ADC circuit during this entire duration Dl; and for each of the N cells, receive a digital word Vl_n, V2_n, V3_n, V4_n with a circuit PWM1, PWM2, PWM3, PWM4 and supply with this circuit PWM1, PWM2, PWM3, PWM4 the control voltage Vl_pwm, V2_pwm, V3_pwm, V4_pwm of the cell at a first level, preferably non-zero, for a duration D2 determined by the digital weight received.
[0132] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.
[0133] In particular, although memory cells having a control input and, for example, a selection input have been mentioned here, memory cells comprising additional inputs may be used in the devices 2 described.
[0134] Furthermore, as briefly mentioned in connection with [Fig.5], the device 2 may comprise several INT / ADC circuits, or, in other words, several connection nodes each configured to receive, for the same duration D1, the output currents of corresponding memory cells, so that several memory calculations are implemented simultaneously in the device 2 during this duration D1.
[0135] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
[0136] In particular, as regards the implementation of the PWMi circuits, as has already been indicated, this is not limited to what has been described in relation to [Fig.3], and, more generally, is not limited to PWMi circuits comprising counters.
[0137] Similarly, as regards the implementation of the INT / ADC circuits, this is not limited to what has been described in relation to [Fig.4].
[0138] Furthermore, although this has not yet been specified, the person skilled in the art will understand that, during a given duration D1, the control voltage received by a memory cell involved in the corresponding memory calculation is at its first level only during the duration D2 (the duration D2 may be continuous or not, and may furthermore be zero or on the contrary equal to D1), and at its second level during the remainder of the duration D1, that is to say during a duration D3 equal to D1 minus D2 (the duration D3 may be continuous or not, and may furthermore be equal to D1 or on the contrary be zero).
[0139] To implement the memory cells described, the person skilled in the art can use memory cells designated by the sign eSTM, or, more generally, non-volatile memory cells with at least two programming levels ("multi-level memory cell" in English).
Claims
1. Claims Device (2) adapted to implement a calculation in memory, the device comprising: memory cells (Cl, C'2, C'3, C'4; C'13, C'23, C'33, C'34) each comprising a control input configured to receive a pulse width modulated control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) and an output configured to provide an output current (Il_pwm, I2_pwm, I3_pwm, I4_pwm; I13_pwm, I23_pwm, I33_pwm, I43_pwm) having a value at least partly determined by a level of the control voltage of the cell and by a weight programmed in said cell; a connection node (200; 500) configured to receive, for a first duration, the output currents (Il_pwm, I2_pwm, I3_pwm, I4_pwm; I13_pwm, I23_pwm, I33_pwm) of several cells (Cl, C'2, C'3, C'4; C'13, C'23, C'33) among said cells; a first circuit (INT / ADC) having an input (202) connected to the first node (200; 500), the first circuit being configured to provide an output signal (V_n) having a value determined by a total amount of current (IS_pwm) received by the input (202) of the first circuit during the first duration; for each cell of said plurality of cells (Cl, C'2, C'3, C'4; C'13, C'23, C'33), a second circuit (PWM1, PWM2, PWM3, PWM4) configured to receive a digital word (V l_n, V2_n, V3_n, V4_n) and to supply, during the first duration, the control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) to said cell at a first level only during a second duration determined by said digital word; a connection network (R) having an output connected to the first node (500) and inputs connected to the outputs of at least said several cells (C'13, C'23, C'33); and a control circuit (R_CTRL) of said network configured, during the first duration, to control the network (R) so that the first node (500) receives the output current (I13_pwm, I23_pwm, I33_pwm) only from said several cells involved in the calculation in memory and that the outputs of the others cells that are connected to the network inputs and are not involved in in-memory computation are electrically isolated from the first node.
2. Device according to claim 1, in which each memory cell (Cl, C'2, C'3, C'4) is configured so that the value of its output current (Il_pwm, I2_pwm, I3_pwm, I4_pwm) is solely determined by the level of its control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) and by the weight programmed in said cell.
3. Device according to claim 1, in which each memory cell (C13, C'23, C'33, C'43) further comprises a selection input and is configured so that: the value of its output current (I13_pwm, I23_pwm, I33_pwm, I43_pwm) is at a value, preferably zero, independent of the level of its control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) and of the weight programmed in said cell if its selection input receives a selection signal (sel3) in a first state; and the value of its output current (I13_pwm, I23_pwm, I33_pwm, I43_pwm) is determined by the level of its control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm), the weight programmed in the cell and the state of the selection signal received by its selection input if the state of the selection signal (sel3) is different from the first state.
4. Device according to claim 3, wherein the device further comprises a selection circuit (SEL) configured to provide, to each cell of the plurality of cells (C'13, C'23, C'33), the selection signal (sel3) of the cell.
5. Device according to any one of claims 1 to 4, wherein each second circuit (PWM1, PWM2, PWM3, PWM4) is configured so that the control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) provided by this second circuit comprises exactly two levels, said two levels comprising the first level.
6. Device according to any one of claims 1 to 5, wherein the first circuit (INT / ADC) comprises an integrator circuit (INT) configured to integrate the quantity of current (IS_pwm) received by the first circuit (INT / ADC) during the first duration and to provide a first signal (sig3) determined by said integration.
7. Device according to claim 6, wherein the first signal (sig3) is an analog signal and the first circuit (INT / ADC) further comprises an analog-to-digital converter (ADC) configured to convert the first analog signal into a digital signal determining the output signal (V_n) of the first circuit (INT / ADC).
8. Device according to any one of claims 1 to 5, in which the first circuit (INT / ADC) comprises: - an oscillator having an oscillation frequency determined by a total current (IS_pwm) available on the first node (200, 500), and - a counter configured to provide a digital signal having a value determined by a counted number of oscillations during the first duration, the output signal (V_n) of the first circuit (INT / ADC) being determined by the digital signal provided by the counter.
9. Device according to any one of claims 1 to 8, in which the first duration is equal to K times a clock period (clk), with K a constant number, and, for each cell of the plurality of cells, the second duration (D2) is equal to Q times the clock period, with Q a number less than or equal to the number K.
10. A device according to claim 9, wherein the numbers K and Q are integers.
11. Device according to claim 10, wherein each second circuit (PWMi) comprises a counter (COUNTER) configured to: - receive the digital word (Vi_n) received by said second circuit, - count, during the first duration, a number of periods of the clock (clk), and - provide, during the first duration, an output signal (sig2) at a first binary state if the counted number of periods is less than a value determined by said digital word (Vi_n), and at a second binary state otherwise, said second circuit (PWMi) being further configured to provide said control voltage (Vi_pwm) at the first level if the output signal (sig3) of the counter (COUNTER) is at the first binary state.
12. Device according to any one of claims 9 to 11, in which the number K is determined by a maximum value of the
13. digital words (Vi_n) and, for each cell of the plurality of cells, the number Q is determined by a value of the digital word (Vi_n) received by the second circuit (PWMi) supplying the control voltage (Vi_pwm) to said cell. A method of memory calculation implemented in a device (2) comprising memory cells (Cl, C'2, C'3, C'4; Cl3, C'23, C'33, C'34) each comprising a control input configured to receive a control voltage (Vl_pwm, V2_pwm, V3_pwm, V4_pwm) and an output configured to provide an output current (Il_pwm, I2_pwm, I3_pwm, I4_pwm; I13_pwm, I23_pwm, I33_pwm, I43_pwm) having a value at least partly determined by a level of the control voltage of the cell and by a weight programmed in said cell, the method comprising, for a first duration: providing to a connection node (200, 500) the output currents (I1_pwm, I2_pwm, I3_pwm, I4_pwm; I13_pwm, I23_pwm, I33_pwm) of a plurality of cells (C1, C'2, C'3, C'4; C13, C'23, C'33) among the cells of the device, by controlling with a control circuit a connection network of the device having an output connected to the first node (500) and inputs connected to the outputs of at least said several cells (C13, C'23, C'33), so that the first node (500) receives the output current (I13_pwm, I23_pwm, I33_pwm) only from said several cells involved in the calculation in memory and that the outputs of the other cells which are connected to the inputs of the network and which are not involved in the memory calculation are electrically isolated from the first node; providing with a first circuit (INT / ADC) having an input (202) connected to the first node, an output signal (V_n) having a value determined by a total amount of current (IS_pwm) received by the input (202) of the first circuit during the first duration; and for each cell of the plurality of cells (Cl, C'2, C'3, C'4; C'13, C'23, C'33), receiving a digital word (Vl_n, V2_n, V3_n, V4_n) with a second circuit (PWMI, PWM2, PWM3, PWM4) and providing with the second circuit the control voltage (V l_pwm, V2_pwm, V3_pwm, V4_pwm) of the cell at a first level only during a second duration determined by the received digital word.