RESISTIVE MEMORY CELL

Abstract

RESISTIVE MEMORY CELL The invention relates to a resistive memory cell (1) comprising: A lower electrode (2) based on titanium nitride; An upper electrode (4); An active layer (3) having a first contact surface (S1) with the lower electrode and a second contact surface (S2) with the upper electrode, said active layer (3) comprising a zone, called the local zone (5), said local zone being made of a material comprising vanadium, titanium, and oxygen extending from the first contact surface (S1), the remainder of the active layer being made of conductive vanadium oxide (V2O3). Figure to be published with the abbreviation: Figure 1

Description

Title of the invention: RESISTIVE MEMORY CELL TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of resistive memories. The present invention relates to a non-volatile resistive memory cell. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] For applications requiring information storage even when the power is off, non-volatile memories of the EEPROM or FLASH type are commonly used. However, these memories have drawbacks such as long write times, a limited memory point density due to the size of the transistors used, and a limited number of rewrite cycles.

[0003] More recently, resistive non-volatile memories have been a promising alternative to FLASH or EEPROM type memories.

[0004] Resistive memories rely on the use of an active medium whose electrical resistance depends on the electrical voltage applied across the material. In other words, a resistive memory cell has two states: a High Resistive State (HRS) corresponding to a high resistance state and a Low Resistive State (LRS) corresponding to a low resistance state. The active medium is inserted between two electrodes that allow the application of an electrical voltage and ensure the reading and writing of the state of the resistive memory cell.

[0005] Depending on the type of active material used, different types of resistive memory can be made: phase change materials (PCRAM or “Phase Change RAM” memories also called PCM “Phase Change Memory”), ionic conduction (CBRAM or “Conductive Bridging RAM” memories), metal oxide (OxRAM or “Oxide Resistive RAM” memories), magnetic (MRAM or “Magnetic RAM” memories), spin transfer magnetic (STTRAM or “Spin Torque Transfer RAM” memories) or Mott insulators.

[0006] Mott memories are based on the use of an active layer made of Mott insulating materials. These materials, according to band theory, should be conductive but are actually insulating due to strong electronic correlations. It is possible to switch the material from this Mott insulating state to a metallic state by applying pressure or an electric field. In Mott memories, a SET voltage applied to the memory electrodes controls the transition from the insulating state to the metallic state, and a RESET voltage applied to the memory electrodes controls the transition from the metallic state to the insulating state. It should be noted that Mott memories are of the apolar type: in other words, it does not matter which sign the SET or RESET voltage is applied, unlike bipolar resistive memories such as CB RAM memories for example, for which it is necessary to reverse the sign of the potential applied to the electrodes depending on whether one seeks to perform a SET or RESET operation.

[0007] Among Mott insulators, crystalline vanadium sesquioxide in which some of the vanadium atoms are replaced by chromium, for example (V2xCrx)O3 (with x > 0.011), is a Mott insulator in which the phenomenon of reversible resistive switching induced by an electrical pulse is possible. It is therefore used for the realization of Mott memories. The advantage of Mott resistive memories compared to other resistive RRAM memories is that they are based solely on electronic transition phenomena. Unlike some other resistive memories with an initial state where the active material of the active storage area is insulating (pristine state), Mott memory does not require an initialization or forming step (i.e., a step during which an initial electrical stress must be applied to the blank memory cell in order to generate the LRS state for the first time).

[0008] The production of thin layers of crystalline (V2xCrx)O3 (with x > 0.011) suitable for use in a Mott memory has been achieved by physical vapor deposition (PVD) techniques such as magnetron sputtering. This involves abrasion of vanadium-chromium-based targets with argon ions under oxygen pressure to obtain an amorphous vanadium oxide that is not stoichiometric in oxygen and chromium. However, the (V2xCrx)O3 (with x > 0.011) material used in Mott memories must be crystalline and perfectly stoichiometric. Consequently, the PVD deposition step is followed by an annealing step at a temperature of 500°C or higher under a reducing atmosphere. Such a technique presents certain disadvantages in a CMOS back-end integration logic where the thermal budget must not exceed 450°C. Summary of the invention

[0009] The invention offers a solution to the problems mentioned above, by proposing a non-volatile resistive memory cell based on vanadium oxide which is in particular more easily integrated into a CMOS back end process.

[0010] A resistive memory cell is defined as an electrical device having a first highly resistive state, or HRS state, or RESET state, and a second low-resistive state, or LRS state, or SET state. Non-volatility lies in the fact that the memory cell retains its resistive state once the SET or LRS voltage is applied. RESET is no longer applied.

[0011] The invention relates more specifically to a resistive memory cell including: • A lower electrode made of titanium nitride, • A top electrode, • An active layer having a first contact surface with the lower electrode and a second contact surface with the upper electrode, said active layer comprising a zone, called local zone, said local zone being in a material comprising vanadium, titanium and oxygen extending from the first contact surface, the rest of the active layer being made of conductive vanadium oxide V2O3.

[0012] Vanadium oxide V2O3 conductive means a V2O3 material with a resistivity less than or equal to 0.1 ohm.cm.

[0013] Unlike Mott memories, which rely on the use of a (V₂xCrx)O₃ material (with x > 0.011) in the Mott insulating phase, the memory cell according to the invention uses an active layer primarily made of V₂O₃ with a singular region in this layer at the interface between the active layer and the lower electrode: this region of the active layer at the lower electrode is not made of conductive vanadium oxide (V₂O₃) and comprises a highly resistive material including vanadium, titanium, and oxygen. Surprisingly, the applicant discovered that such a cell exhibited resistive memory operation, allowing switching between a highly resistive (HRS) state and a low resistive (LRS) state.These RESET and SET operations are performed by applying a potential difference of opposite polarity between the upper and lower electrodes of the memory cell: in other words, unlike Mott memories, the cell according to the invention has a bipolar operation.

[0014] Surprisingly, the applicant discovered the operation of the invention while attempting to produce an insulating V2O3 material for a Mott memory using an ion beam deposition (IBD) technique. Using this deposition technique, the inventors obtained a conductive V2O3 material, which was therefore unsuitable for a Mott memory known from the prior art. However, by performing RESET / SET cycle operations on a stack including an active layer of conductive V2O3 deposited between two electrodes, the inventors observed resistive memory-type operation.They also observed that, during the first initialization operation (or forming according to English terminology), the conductive V2O3 layer transitioned from a low resistive state LRS to a highly resistive state HRS with the appearance of this unique local zone based on titanium, oxygen and highly resistive vanadium. in the V2O3 layer. This particular cell structure, including this zone formed from a V-Ti-O alloy, gives the cell according to the invention the function of a bipolar resistive memory cell. We will return later in the description to the structure of this cell, its operation, and the mechanism of creation of this localized V-Ti-O zone, probably linked to significant heating at the interface between the lower electrode and the active layer during the forming step. It should be noted that IBD deposition techniques allow the fabrication of crystalline or partially crystalline conductive V2O3 layers at crystallization temperatures above 280°C, thus perfectly compatible with CMOS back-end integration.

[0015] It should be noted that the terms "lower" and "upper" are of course used for a better understanding of the invention but remain relative so that the lower electrode can be considered as the upper electrode and the upper electrode as the lower electrode by reversing the memory cell while remaining within the scope of the memory cell according to the invention.

[0016] In addition to the characteristics mentioned in the preceding paragraphs, the memory cell according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The upper electrode is made of titanium nitride; • the local area is without contact with the second contact surface; • the thickness of the active layer is between 5 and 200 nm and preferably between 10 and 100 nm; • the local zone has a dome shape whose cross-section parallel to the plane of the layers decreases from the first contact surface; • The lower titanium nitride-based electrode contains vanadium, titanium, and oxygen in a localized area near the first contact surface. In this case, the local area has, for example, a mushroom shape with a dome whose cross-section parallel to the plane of the layers decreases from the first contact surface; • The first contact surface has an area less than or equal to 6000 nm² • 9 • the first contact area is equal to the upper surface of the lower electrode and strictly less than the total lower surface of the active layer; • the lower electrode has a rectangular parallelepiped shape of the "Wall" type or an L-shaped shape; • Vanadium oxide V2O3 conductive is crystalline or partially crystalline; • the local area is made of a crystalline or partially crystalline material.

[0017] Another object of the invention is a method for manufacturing a memory cell comprising the following steps: • Fabrication of a lower electrode based on titanium nitride; • Deposition of a layer made of vanadium oxide V2O3 having a first contact surface with the lower electrode; • Fabrication of a top electrode; said process comprising a step, called the initialization step, consisting of injecting a current through the stack formed by the lower electrode, the V2O3 layer and the upper electrode, the current density being chosen to create said local zone comprising vanadium, titanium and oxygen.

[0018] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The process includes a heat treatment step during or after said deposition step until said layer is made conductive in vanadium oxide V2O3; • said deposited layer is made of amorphous vanadium oxide V2O3; • the current density of the initialization stage is greater than or equal to 50.106 A / cm2; • the deposition of the layer made of vanadium oxide V2O3 is carried out by an ion beam deposition technique; • the process includes a step of cleaning the lower electrode by ionic pickling (Ar, Xe, or Kr) in situ (i.e. in the same equipment as the V2O3 deposition step, without re-airing) before the V2O3 deposition step; • The upper electrode can be made in situ or after exposure to air. BRIEF DESCRIPTION OF THE FIGURES

[0019] The figures are presented for illustrative purposes only and are in no way limiting of the invention.

[0020] Fig. 1 schematically represents a 3D view of the memory cell according to the invention.

[0021] Fig. 2 represents the behavior during 1000 write (SET) and erase (RESET) cycles of a memory cell according to the invention.

[0022] Fig. 3 shows a dark-field STEM image of a pre-forming cell.

[0023] Figure 4 shows a dark-field STEM image of a memory cell according to the invention.

[0024] Figures [Fig. 5], [Fig. 6], [Fig. 7] and [Fig. 8] show energy-dispersive X-ray spectroscopy (EDX) and TEM microscopy analyses of a memory cell according to the invention.

[0025] Figs.9, 10, 11 and 12, 13, 14 and 15 show results of write (SET) and erase (RESET) cycles for cells according to the invention with different contact surfaces and different active layer thicknesses.

[0026] Figure 16 schematically illustrates the operation of a memory cell according to the invention.

[0027] Figures [Fig.17] and [Fig.18] are EELS analyses showing the presence of oxygen and vanadium in the upper part of the lower electrode of the memory cell according to the invention.

[0028] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. DETAILED DESCRIPTION OF THE INVENTION

[0029] Unless otherwise specified, the same element appearing on different figures has a unique reference.

[0030] Fig. 1 schematically represents in three dimensions a memory cell 1 according to the invention in an Oxyz frame, the Oxy plane defining the plane of the layers, the Oz axis defining the direction of the height of the layers, the Oy axis defining the direction of the length of the layers and the Ox axis defining the direction of the width of the layers.

[0031] Memory cell 1 comprises: • A lower electrode 2 made of TiN; • A top electrode 4 made of TiN; • An active layer 3 mainly made of conductive vanadium oxide V2O3 and crystallized or partially crystallized but with a singular localized zone 5 comprising titanium, vanadium and oxygen which we will return to later.

[0032] The upper surface of the active layer 3 is in contact with the lower surface of the upper electrode 4, according to a contact surface S2.

[0033] The lower surface of the active layer 3 is in contact with the upper surface of the lower electrode 2, along a contact surface SL

[0034] The lower electrode 2 has a "wall" type architecture, that is to say, it forms a parallelepiped wall of length 1, width L and height h: the area IxL of the upper surface of the electrode is strictly less than the area of ​​the surface in lower of the active layer 3; in other words, the contact surface area SI is equal to IxL. The contact surface area SI is strictly less than the contact surface area S2 (i.e., the lower electrode 2 here has a width L much less than the width of the upper electrode 4 and a length 1 less than or equal to that of the upper electrode 4). Note that the lower electrode 2 can also have other shapes, such as an L-shape with an upper part identical to the wall shown above and a lower part parallelepiped-shaped and parallel to the plane of the layers.

[0035] The active layer 3 of the memory cell 1 according to the invention can be produced, in particular, by depositing a layer of crystalline or partially crystalline conductive V2O3 using an ion beam deposition (IBD) technique. The deposition consists of sputtering a vanadium target with an argon ion beam. The deposition chamber is placed under vacuum (5 x 10⁸ Torr) before deposition. During deposition, the partial pressure of oxygen is controlled and influences the degree of oxidation of the final material. The deposition takes place at room temperature and does not necessarily require heat treatment, thus making the method for obtaining the memory cell according to the invention compatible with CMOS back-end integration. Even with crystallization annealing, the temperatures remain below 450°C, which is the maximum temperature for CMOS back-end integration.

[0036] According to another embodiment, after IBD deposition, the V2O3 is insulating (resistivity on the order of a few ohms.cm to a few tens of ohms.cm) and amorphous (no detectable diffraction peaks in XRD characterization). In this case, annealing at a temperature below 450°C and preferably above or equal to 280°C is carried out to obtain a conductive V2O3 material (i.e., with a resistivity less than or equal to 0.1 ohm.cm) that is crystallized or partially crystallized. It should be noted that the annealing step can be carried out during the fabrication of the wall-type memory cell, which incorporates certain technological steps, such as the deposition of encapsulating dielectrics, at temperatures on the order of 300°C, the temperatures at which the amorphous IBD V2O3 crystallizes.

[0037] The upper and lower titanium nitride electrodes are manufactured using techniques well known to those skilled in the art. At this stage, the active layer is exclusively made of crystalline or partially crystalline conductive V2O3, whereas, as we have seen, the active layer 3 according to the invention comprises a unique localized zone 5 containing titanium, vanadium, and oxygen. The conductive V2O3 could also be obtained by other deposition techniques such as PVD deposition. It is also possible to use crystalline conductive V2O3 in which a portion of the vanadium is substituted by chromium, as long as the V2O3 remains in control.

[0038] To obtain this singular localized zone 5, a forming (i.e., initialization) step is required through the stack formed by the two electrodes (the lower electrode having the shape of wall 2) and the crystalline or partially crystalline conductive V2O3 layer. It is understood that at this stage, called the pristine state (i.e., the virgin state), the stack is in a low resistivity state (LRS) since the V2O3 layer is conductive. The forming step consists of injecting a current with a high current density, preferably strictly greater than 50 x 10⁶ A / cm², by applying a positive voltage between the first and second electrodes (forming voltage). This step will cause the stack to switch from its pristine state (LRS) to a high resistivity state (HRS) and will lead to the appearance of the localized zone 5 shown in [Fig. 1].The appearance of this zone including titanium, oxygen and vanadium can be explained by the injection of a high density current at the contact surface SI between the first electrode 2 and the active layer 3. The upper surface area IxL of the first wall-shaped electrode is chosen to be small enough to cause local heating at SI and the area near SI (i.e. above in the active zone 3 and below in the first electrode 2).Electrothermal simulations using the COMSOL tool show that the temperature reached at the interface between the lower wall electrode 2 and the active layer 3 can reach 2000°K: this local heating leads to the creation of zone 5 made of a V-Ti-O alloy having a first part 6 in the shape of a dome extending from the first SI contact surface and rising into the interior of the active layer 3 and a second part 7 located on the upper end of the lower electrode 2. In other words, zone 5 has the shape of a mushroom with its cap in the active zone 3 and its stem in the top of the lower electrode 2.

[0039] Once this forming operation is completed and the V-Ti-0 based zone 5 is created, the memory cell 1 behaves like a bipolar resistive memory cell. In other words, applying a SET voltage pulse will perform a SET operation and switch to a low-resistive state (LRS). Then, applying a RESET voltage pulse of opposite sign to the SET voltage will switch to a high-resistive state (HRS). The memory cell exhibits non-volatile behavior, so that it retains the resistance value once the SET or RESET voltage is no longer applied. Figure 2 shows the behavior during 1000 write (SET) and erase (RESET) cycles of a memory cell according to the invention with an active layer thickness of 50 nm, a lower wall-type electrode length 1 of 100 nm and a width L of 24 nm. The SET pulse is 1.2V for 100 ns and the RESET pulse of opposite polarity to the SET pulse is 1.3 V for 200 ns. On. The memory cell according to the invention, which switches from an LRS resistance of a few kOhms to an HRS resistance of a few hundred kOhms, exhibits good endurance (i.e., during 1000 SET / RESET cycles). The endurance results show low dispersion of resistive states compared to other types of resistive memories such as CBRAM or OxRAM. It is noted that the SET and RESET pulses have amplitudes of less than 2 V and durations of less than 1 ps.

[0040] The localized zone 5 was identified using scanning transmission electron microscopy (STEM) images, as illustrated in Figures 3 and 4. Figure 3 shows a dark-field STEM image of a cell before forming, and Figure 4 shows a dark-field STEM image of a memory cell according to the invention after the forming step and 40 programming cycles. The circle shown in Figure 4 surrounds the specific zone 5 of Figure 1 created after the initialization step, above the lower TiN wall electrode. This zone 5, not present in Figure 3 before the forming step, is an altered zone a few nanometers thick with a high atomic density, dome-shaped, whose cross-section parallel to the plane of the layers decreases from the first contact surface.It is observed that this zone 5 is indeed located within the conductive V2O3 active layer 3 and has a different atomic density than the conductive V2O3 portion. Furthermore, it is noted that this zone 5 originates from the contact surface between the active layer 3 and the lower TiN electrode 2, then extends upwards through the thickness of the active layer 3 without reaching its upper surface. Therefore, zone 5 is not in contact with the upper electrode 4. The localized zone 5 remains present throughout the various programming cycles and can be viewed as a zone in contact with the lower electrode 2 within a larger conductive V2O3 region. The fact that the memory cell according to the invention is in a highly resistive state after the forming step indicates that zone 5 is made of a highly resistive material.Thus, the forming step induces a change in the composition of the conductive V2O3 material in this zone and the formation of a highly resistive alloy based on vanadium, titanium, and oxygen. This result is supported by data from the literature which indicate high resistivities on the order of 105 Ohm.cm for TiO2-V2O3-V2O5 alloys and especially by energy-dispersive X-ray spectroscopy (EDX) analyses illustrated in Figures 5 to 8, which demonstrate the presence of titanium in this particular zone. Figures 5 to 8 each show: • On the right, a transmission electron microscopy image. TEM (Transmission Electron Microscopy, according to English terminology) of the memory cell according to the invention; • On the upper part, a diffraction image of the area surrounded by the rectangle present on the TEM image; • On the lower part, the EDX spectrum of the area surrounded by the rectangle present on the TEM image.

[0041] TEM and EDX analyses show the formation of a local dome-shaped zone 6 containing vanadium, titanium, and oxygen. The presence of vanadium and oxygen is not surprising since this zone is located in a layer initially composed of V2O3. In contrast, EDX analyses clearly show the presence of titanium in the first wall-type electrode, as well as in the local zone located immediately above the first electrode and labeled 5 in [Fig. 1]. The amount of titanium is observed to be greatest at the SI contact interface between the active layer 3 and the lower electrode 2, then gradually decreases until it disappears in the active layer 3, which contains only V2O3 in its upper part: this observation clearly identifies the singular zone 5, which does not extend over the entire height of the active layer 3. The presence of titanium is again evident at the upper electrode 4.

[0042] Figures 17 and 18 show EELS analyses by electron energy loss spectrometry illustrating the distribution of vanadium and oxygen respectively for a stack of a memory cell according to the invention before the forming step and for a memory cell according to the invention once formed. For each [Fig. 17] and 18, the upper part shows a transmission electron microscopy image of the analyzed area: the lower electrode and the active layer are visible. In [Fig. 17], the EELS images of the uninitialized stack (bottom left for vanadium and bottom right for oxygen) show the presence of vanadium and oxygen only in the active layer. In contrast, in [Fig. 18], the EELS images of the memory cell according to the invention (bottom left for vanadium and bottom right for oxygen) show the presence of oxygen and vanadium, in addition to titanium, in the upper part 7 of the lower electrode 2.We therefore have a local zone 5 in the shape of a mushroom (dome 6 and upper part 7 of the lower electrode) containing vanadium, titanium and oxygen.

[0043] Figures 9 to 15 show cycling results for cells according to the invention with different SI contact surfaces and different active layer thicknesses 3. These results show that the thickness of the conductive V2O3 layer has little impact on the memory behavior of the cell according to the invention: this thickness is, however, preferably between 5 and 200 nm and even more advantageously between 10 and 100 nm. The SI contact surface (i.e., corresponding to the upper surface of the lower electrode wall 2) is, for its part, preferably smaller at 6000 nm2.

[0044] Figure 16 schematically illustrates an explanation of the operating mode of the cell according to the invention. The left part of the figure shows the stacking before the forming step without the presence of the highly resistive local area 5: in this blank configuration, the stacking is low resistivity. After the initialization step, which allows the transition from a low resistivity blank state to a high resistivity (HRS) state, the memory cell according to the invention 1 is created with the presence of the highly resistive singular area 5, which includes, in particular, Ti, V, and O. Subsequently, the resistive memory cell could behave like a filamentary resistive memory with the singular area 5 acting as a solid electrolyte.Thus, when a positive potential is applied to the lower electrode 2, mobile titanium-based ions move from the lower electrode 2 under the influence of the electric field applied to the electrodes, leading to the growth of a titanium metallic filament within the singular zone 5 based on Ti, V, and O. Since the remainder of the active layer 3 is composed of metal oxide, the memory cell according to the invention then transitions to a low-resistance state (LRS). The transition to the high-resistance state (HRS) is achieved by applying a negative voltage to the lower electrode 2, resulting in the total or partial dissolution of the conductive filament.

Claims

Demands

1. Resistive memory cell (1) comprising: - A lower electrode (2) based on titanium nitride, - An upper electrode (4), - An active layer (3) having a first contact surface (SI) with the lower electrode and a second contact surface (S2) with the upper electrode, said active layer (3) comprising a zone, called local zone (5), said local zone being in a material comprising vanadium, titanium and oxygen extending from the first contact surface (SI), the remainder of the active layer being made of conductive vanadium oxide V2O3.

2. Memory cell according to the preceding claim characterized in that the upper electrode (4) is based on titanium nitride.

3. Memory cell according to any one of the preceding claims characterized in that said local area is without contact with the second contact surface (S2).

4. Memory cell according to any one of the preceding claims characterized in that the thickness of the active layer is between 5 and 200 nm and preferably between 10 and 100 nm.

5. Resistive memory cell according to any one of the preceding claims characterized in that the local area has a dome shape whose cross-section parallel to the plane of the layers decreases from the first contact surface.

6. Memory cell according to any one of the preceding claims characterized in that the lower titanium nitride-based electrode comprises vanadium, titanium and oxygen in a localized area near the first contact surface.

7. Memory cell according to any one of the preceding claims characterized in that the first contact surface has an area less than or equal to 6000 nm2.

8. Memory cell according to any one of the preceding claims characterized in that the first contact area is equal to the upper surface of the lower electrode and is strictly less than the total lower surface of the active layer.

9. Memory cell according to any one of the preceding claims characterized in that the lower electrode has a rectangular parallelepiped shape of the “Wall” type or an L-shaped shape.

10. Memory cell according to any one of the preceding claims characterized in that the conductive vanadium oxide V2O3 is crystalline or partially crystalline.

11. Memory cell according to any one of the preceding claims characterized in that the local area is in a crystalline or partially crystalline material.

12. A method for manufacturing a resistive memory cell according to any one of the preceding claims, characterized in that it comprises the following steps: - Fabrication of a lower electrode based on titanium nitride; - Deposition of a layer made of vanadium oxide V2O3 having a first contact surface with the lower electrode; - Fabrication of an upper electrode; said method comprising a step, called the initialization step, consisting of injecting a current through a stack formed by the lower electrode, the V2O3 layer and the upper electrode, the current density being chosen to create said local zone comprising vanadium, titanium and oxygen.

13. The method according to the preceding claim characterized in that it comprises a heat treatment step during or after said deposition step until said layer is made conductive in vanadium oxide V2O3.

14. A method for manufacturing a memory cell according to any one of claims 12 to 14 characterized in that the current density of the initialization step is greater than or equal to 50.106 A / cm2.

15. Method of manufacturing a memory cell according to any one of claims 12 to 14 characterized in that the deposition of the layer made of vanadium oxide V2O3 is carried out by an ion beam deposition technique.

Images