PROGRAMMABLE READ-ON MEMORY CELL

Abstract

A once-programmable memory cell comprises a transistor with a drain, a source, and a channel between the drain and the source. The transistor is connected to a data storage element and a memory cell selector element. The transistor channel comprises a first and a second channel portion. The dopant concentration in the first channel portion is higher than in the second channel portion. (See accompanying figure: Figure 2)

Description

Title of the invention: PROGRAMMABLE READ-ONLY MEMORY CELL Technical field

[0001] The present invention relates to memory cells, and more particularly to one-time programmable memory cells.

[0002] CONTEXT

[0003] Non-volatile memory (NVM) is a type of memory that does not require a continuous power supply to retain stored information. One-time programmable (OTP) memories are a special type of NVM, they contain memory elements that can only be programmed once and cannot be changed after programming. OTP memories are used in a wide range of electronic products, for example in consumer products or critical security systems.

[0004] [Fig.l] illustrates an example of a known simple OTP memory cell. The cell includes a transistor (100) and (as a memory element) a gate oxide capacitor (102). The OTP memory cell illustrated in [Fig.l] is an anti-fuse type OTP memory cell, i.e., the memory element has low conductivity before programming and high conductivity after programming. The transistor (100) allows a particular memory cell (a memory device typically has a large number of memory cells) to be selected for programming or reading.

[0005] To program the memory cell of [Fig.l], a programming voltage is applied to a data line connected to the top plate of the capacitor (102). At the same time, a selection voltage is applied to the gate of the transistor (100) to activate the transistor (100) and a low voltage (e.g. 0 V) ​​is applied to the source of the transistor (100) (the PSUB pin of the transistor (100) is connected to ground). The programming voltage is selected to be higher than the breakdown voltage of the capacitor, so that a gate oxide burning process occurs, destroying the insulating properties of the gate oxide and establishing a conductive connection between the two plates of the capacitor (102), thereby programming the memory cell. Thus, the programming state of the memory cell can therefore be determined by measuring the current flowing through the capacitor (102).

[0006] It is often desirable (e.g., in battery-powered systems) to implement memory cells with low-voltage transistors that can operate with a low switching voltage. However, in the memory cell shown in [Fig.l], the transistor (100) must be able to withstand the high voltage and current present when programming the memory cell. For example, the transistor (100) may have a drain-source breakdown voltage higher than the (required) programming voltage. Therefore, the memory cell of [Fig.l] may not allow the use of low voltage transistors.

[0007] SUMMARY

[0008] One of the problems with conventional OTP memory cells is that they cannot be selected (e.g., for read or program operations) using low voltage signals. This means that conventional OTP memory cells are not suitable, for example, for use in battery-powered devices. To at least partially solve this problem, the present invention provides an improved memory cell, a method of operating the proposed memory cell, and an improved memory device as set forth in the appended claims.

[0009] In summary, the present invention aims to provide new and useful one-time programmable (OTP) memory cells and memory devices. In general, embodiments of the present invention may enable, for example, OTP memory cells that can be selected (for read or program operations) using a lower voltage than conventional OTP memory cells. Embodiments may achieve this by providing a transistor (between a data storage element and a memory cell selection element) that has a channel comprising (at least) two channel portions where a dopant concentration in one channel portion is higher than in the other channel portion. Such a transistor may protect the selection element from high voltages and currents (and thus potential breakdown damage) during programming of the memory cell.Thus, the selection element may be implemented, for example, by a low voltage transistor that can be switched by applying a low voltage. Thus, the embodiments may be particularly suitable for battery-powered devices. Furthermore, the embodiments may be made with a small footprint and may be integrated to form high-density memory arrays. Embodiments of the present invention may be manufactured using conventional foundry processes. Brief description of the drawings

[0010] Embodiments of the invention will now be described, by way of example only, with reference to the attached schematic drawings, in which:

[0011] [Fig.l] shows a known simple OTP memory cell;

[0012] [Fig.2] shows a diagram of an OTP memory cell according to a mode of realization ;

[0013] [Fig.3] shows a cross-section of a structure of the memory cell of [Fig.2];

[0014] [Fig.4] shows an equivalent circuit of the memory cell of [Fig.2] during programming of the memory cell;

[0015] [Fig.5] shows a current measurement obtained experimentally during programming of the memory cell of [Fig.2];

[0016] [Fig.6] shows an equivalent circuit of the programmed memory cell of [Fig.2];

[0017] [Fig.7] shows a cross-section of a portion of the programmed memory cell of [Fig.2] when the memory cell is not selected and a programming voltage is applied;

[0018] [Fig.8] shows a diagram of an arrangement of four memory cells, and

[0019] [Fig.9] shows a diagram of the arrangement of [Fig.8].

[0020] To avoid unnecessary repetition, similar numerical references will be used to indicate similar features in the figures. DETAILED DESCRIPTION

[0021] According to a first embodiment, a one-time programmable memory cell is provided. The one-time programmable memory cell comprises a transistor comprising a drain, a source, and a channel between the drain and the source. The transistor is connected to a data storage element and a memory cell selection element (e.g., an additional transistor). The channel of the transistor comprises a first and a second channel portion (e.g., the two channels may be in direct contact with each other). The dopant concentration in the first channel portion may be higher than in the second channel portion.

[0022] Providing a transistor with two differently doped channel portions allows, for example, the use of a low voltage device to implement the memory cell selection element. Indeed, the transistor can be used to protect the memory cell selection element from potential damage during programming operations (i.e., operations that typically include high voltages and currents).

[0023] The drain of the transistor may be connected to the data storage element, and the source of the transistor may be connected to the memory cell selection element. The second channel portion may be adjacent (e.g., in direct contact) to the drain of the transistor. In this manner, a breakdown voltage between the drain and the gate of the transistor may be increased compared to a transistor that is provided, for example, with a lightly doped drain region between the drain and the channel of the transistor.

[0024] The transistor may further comprise a gate and the source. The gate and the drain may be arranged next to each other in the length direction of the transistor. The first and second channel portions may extend in the length direction of the transistor, respectively over a first and a second length. In particular, the first length may be equal to or greater than one third of the second length. Additionally or alternatively, the first length may be equal to or less than three times the second length. For example, the first length may be 50% greater than the second length.

[0025] The one-time programmable memory cell may further include a lightly doped source region extending between the source and the gate of the transistor. The drain and the source may include respective n-doped regions, and the first channel portion may include a p-doped region. In some implementations, the one-time programmable memory cell may not include a lightly doped drain region extending between the drain and the gate of the transistor.

[0026] The transistor may be formed on a substrate having a substrate polarity and dopant concentration. The second channel portion may have a polarity and dopant concentration substantially equal to the substrate dopant polarity and the substrate dopant concentration. This means that the second channel portion may be considered a "native" channel portion (i.e., the formation of this channel may not require an additional doping step).

[0027] The data storage element may be configured to be programmable by applying a programming voltage. The programming voltage may be higher than an operating voltage of the additional transistor and, when applied to the additional transistor, the programming voltage would damage the additional transistor. In this way, it is thus possible to use high programming voltages without increasing the risk of breakdown of the additional transistor.

[0028] In some implementations, the data storage element may be a capacitor formed on the substrate (i.e., the same substrate on which the transistor is formed). The capacitor may include a source provided in the substrate, a gate oxide layer formed on the substrate, and a top plate. (for connection to a data pin) provided above the gate oxide layer. In some implementations, the one-time programmable memory cell may not include a lightly doped source region extending between the capacitor source and the capacitor gate oxide layer.

[0029] According to another embodiment, there is provided a method of programming or reading the memory cell according to the first embodiment. The method comprises applying a selection voltage to the memory cell selection element, applying a blocking voltage to the gate of the transistor, and applying a programming or reading voltage to the data storage element to program or read the selected memory cell, wherein the blocking voltage is greater than the selection voltage and less than the programming voltage. By providing a blocking voltage greater than the selection voltage and less than the programming voltage, the voltage received from the transistor by the memory cell selection element can be sufficiently low so that the risk of damaging the memory cell selection element is low.

[0030] According to another embodiment, there is provided a memory device which comprises the memory cell according to the first embodiment.

[0031] According to another embodiment, there is provided a memory device which comprises a first, a second, a third and a fourth memory cell according to the first embodiment. The memory cell selection element of each memory cell further comprises a respective additional transistor comprising a gate. The memory device further comprises a shared data line for applying a programming or reading voltage. The shared data line is connected to the data storage element of each memory cell. The memory device further comprises a blocking line for applying a blocking voltage. The blocking line is connected to the gate of the transistor of each memory cell. The memory device further comprises a first and a second selection line.The first selection line is connected to the source of the additional transistor of the first memory cell and to the source of the additional transistor of the third memory cell. The second selection line is connected to the source of the additional transistor of the second memory cell and to the source of the additional transistor of the fourth memory cell. The memory device further comprises a first and a second word line. The first word line is connected to the gate of the additional transistor of the first memory cell and to the gate of the additional transistor of the second memory cell. The second word line is connected to the gate of the additional transistor of the third memory cell and to the gate of the transistor. additional of the fourth memory cell. The device is designed so that at least one of the four memory cells can be selected for programming or reading by applying a voltage to at least one of the select and word lines.

[0032] The proposed memory device may offer the advantage of reducing the number of contacts required to access the four memory cells for reading or programming purposes compared to an arrangement in which the four memory cells must be accessed individually. The proposed memory device may further be made compactly and may be formed using conventional low-voltage CMOS technology without additional steps or additional photolithography (e.g., additional masks). This means that the proposed memory device may be used in high-volume, low-cost OTP memories.

[0033] In general terms, there is provided an anti-fuse type one-time programmable (OTP) memory cell that can be formed in (and on) a semiconductor substrate using standard CMOS manufacturing processes. The memory cell comprises a data storage element, a transistor, and a memory cell selection element (connected in series). Programming the memory cell comprises applying a relatively high voltage (hereinafter "programming voltage") to the data storage element to cause an irreversible change in the conductivity of the storage element. The transistor functions to protect the memory cell selection element from the programming voltage, so that the memory cell selection element can be implemented by an element that can be switched with a low voltage, e.g., a low-voltage transistor.

[0034] Throughout the present disclosure, dimensions or voltage values ​​refer to embodiments of the proposed memory cell when formed using conventional 0.11 pm Metal Oxide Semiconductor (MOS) processes. It is understood that these values ​​are only examples and may vary when the proposed memory cell is formed using a different process. For example, a person of ordinary skill in the art would understand that, when using 0.18 pm MOS processes, the respective dimensions and voltage values ​​may be correspondingly larger.

[0035] [Fig.2] shows a schematic of a one-time programmable (OTP) memory cell (1) according to one embodiment. The memory cell (1) comprises a memory capacitor (202) (as a data storage element), a first transistor (200) and a second transistor (201). The first and second transistor (200, 201) comprise respective source, drain, gate and substrate contacts.

[0036] Generally, in the embodiment of [Fig. 2], the first and second transistors (200, 201) are low voltage n-channel transistors connected in series. The first transistor (200) is configured to enable selection of the memory cell (1) for a read or program operation. The second transistor (201) is configured to perform a high potential latching function during program operations. Since the first and second transistors (200, 201) are low voltage transistors, the memory cell (1) can be selected for a read or program operation by applying a low voltage. For example, the memory cell (1), when formed using 0.11 pm MOS processes, can be selected for a read operation by applying a voltage of 1.2 V (to the gate contacts of the first and second transistors (200, 201), as described in detail below).

[0037] As indicated above, the first transistor (200) is configured to enable selection of the memory cell for read and program operations. The gate of the first transistor (200) is connected to the selection pin WL. The source of the first transistor (200) is connected to the pin S. The substrate of the first transistor (200) is connected to ground via a pin PSUB. The drain of the first transistor (200) is connected to the source of the second transistor (201).

[0038] The second transistor (201) is configured to protect the first transistor (200) from damage during programming operations. For this purpose (and as further described with reference to Figures 3 and 4), the second transistor (201) comprises a "split-channel", i.e. its channel region comprises (at least) two parts which have different dopant concentrations. The gate of the second transistor (201) (hereinafter referred to as "split-channel transistor (201)") is connected to a BLK pin. The substrate of the second transistor (201) is connected to ground by a PSUB pin. The drain of the second transistor (201) is connected to a bottom plate of the capacitor (202). A top plate of the capacitor (202) is connected to a data pin (D). The capacitor (202) may be a native-type, low-voltage, n-channel capacitor with a thin gate oxide thickness.In this case, the programming of the cell (1) is carried out by breaking the oxide of the capacitor (202) (as described in detail below with reference to Figures 4 and 5).

[0039] Referring now to [Fig. 3], an exemplary semiconductor structure implementing the memory cell (1) is described. The semiconductor structure comprises a semiconductor substrate (400). The substrate may have a low concentration of impurities. The semiconductor structure comprises a p-type well (500) (i.e., a region of the substrate formed by ion implantation and in which low voltage devices can be implemented). The semiconductor structure further comprises shallow trench isolation regions (100) (i.e., trenches in the substrate surface filled with an STI material such as silicon oxide) around the transistors (200, 201) and the capacitor (202) (e.g., to provide isolation between individual memory cells when multiple cells are provided on the same substrate).

[0040] The memory capacitor (202) is provided on the substrate region (400) with a thin gate oxide (300). The thin gate oxide (300) may have a thickness of about 2.9 nm when formed using a 0.11 pm MOS process. The top plate (52) of the capacitor (202) is connected to the data pin D of the memory cell (1). The top plate (52) may be formed of poly-Si. The source of the capacitor (202) is provided with an n-type active region (152) in the substrate region (400). A (thick) oxide spacer (62) provides isolation between the source region (152) and the top plate (52).

[0041] Unlike conventional thin gate oxide capacitors, the source region (152) of the capacitor may be formed without an NLDD (n-type lightly doped drain / source) implantation region. In other words, the surface of the substrate (400) between the n-type active region (152) and the gate oxide (300) of the capacitor (202) may be native (i.e., of the same dopant polarity and dopant concentration as the substrate (400)). As described below with reference to Figures 4 and 5, the absence of an NLDD implantation region in the source region of the capacitor (152) may increase the breakdown voltage between the capacitor plate (52) and the source region of the capacitor (152) once the memory cell 1 is programmed. The increased breakdown voltage may be a particular advantage of the memory cell 1.For example, increasing the breakdown voltage can reduce the risk of leakage current when the memory cell is not selected and the high programming voltage is applied to data pin D.

[0042] The split-channel transistor (201) includes a gate (51) on a thin gate oxide layer (300). The gate (51) may be formed of poly-Si. The oxide layer (300) of the split-channel transistor (201) may have a thickness of about 2.9 nm when formed using a 0.11 µm MOS process. The gate (51) is connected to the blocking pin BLK of the memory cell (1). As described in detail below with reference to Figures 6 and 7, in programming mode, a “blocking voltage” VBlk is applied to the BLK pin. Typically, the blocking voltage VBlk is selected to be appropriate (e.g., approximately equal to 50% of the programming voltage Vpp) to protect the drain of the first transistor (200) (low voltage) from the high voltage Vpp applied to pin D. In other words, VBlk can be selected so that (VBlk - Vt) is less than the drain breakdown voltage of the first transistor (200), where Vt is the threshold voltage of the split-channel transistor (201) (appropriately corrected for the source / substrate voltage of the device).

[0043] The split-channel transistor (201) further comprises first and second channel portions (L1 and L2). In general, the first and second channel portions have different doping concentrations. In one embodiment, the doping concentration in the first channel portion (L1) may be at least 20 times higher than the doping concentration in the second channel portion (L2). For example, when formed using a 0.11 pm MOS process, the doping concentration in the channel portion (L1) may be 5.8e+17 cm3 and the doping concentration in the channel portion (L2) may be 2e+16 cm3. In the embodiment of [Fig. 3], the first channel portion (L1) is provided in the p-type well (500) and may thus act as an “enhancement” portion (hereinafter referred to as the “enhancement channel portion (L1)”). As shown in [Fig.3], the enhancement channel portion (L1) is provided on the source side of the transistor. The second portion (L2) may be provided in the substrate (400) (i.e., the second channel portion may be considered a "native" portion, and the second channel portion (L2) is hereinafter referred to as the "native channel portion (L2)"). In other words, the native channel portion (L2) may have the same dopant polarity and dopant concentration as the substrate (400). In other embodiments, the second channel portion may have a different dopant concentration than the substrate (400).

[0044] The native channel portion (L2) is provided on the drain side of the split-channel transistor (201). In general, providing a drain-side channel portion having a lower doping concentration than a source-side channel portion can reduce the risk of avalanche breakdown of the drain during programming of the memory cell (1).

[0045] Conduction through the enhancement channel portion and the native channel portion (L1, L2) may be controlled by the common gate (51). As shown in [Fig. 3], the source (151), the enhancement channel portion (L1), the native channel portion (L2) and the drain (152) of the transistor (201) may be arranged next to each other in the length direction of the transistor. The enhancement channel portion and the native channel portion (L1, L2) may extend along the length direction of the transistor (201) respectively for a first and a second length. As described in detail below, the first length (i.e., the length of the enhancement portion (Ll) in the length direction of the transistor (201)) can be selected to be large enough to avoid a "snap-back" effect in the channel of the transistor (201) when the programmed memory cell (1) is de-selected while the programming voltage is applied to the data pin (D).

[0046] In general, to achieve the above-mentioned effect, the lengths of the enhancement and native portions may be selected according to the doping of the p-type well (500) and the doping of the substrate (400). For example, in an embodiment with a lower doping concentration of the p-type well (500), the length of the enhancement portion (L1) may be increased according to the same principle. In an embodiment with a lower doping concentration of the substrate (400), the length of the native portion (L2) may be increased according to the same principle.

[0047] In one embodiment, the first length may be equal to or greater than one-third of the second length. Additionally or alternatively, the first length may be equal to or less than three times the second length. In some embodiments, the first length may be 50% greater than the second.

[0048] For example, in an embodiment where the memory device (1) is formed using a 0.11 pm MOS process and the doping concentrations of the p-type well (500) are 5.8e+17 cm3 and the doping concentrations of the p-type substrate (400) are 2e+16 cm 3, the lengths of the enhancement channel portion and the native channel portion (L1, L2) may be equal, for example 0.4 pm.

[0049] Furthermore, the enhancement channel portions and the native channel portion (L1, L2) may be provided with a width (i.e., the extension of these channel portions in a direction perpendicular to the longitudinal direction of the split-channel transistor (201) and parallel to the surface of the substrate (400)) such that the conductance of the split-channel transistor (201) does not significantly limit the programming current during programming of the memory cell (1).

[0050] The semiconductor structure of [Fig.3] further comprises an n-type active region (151) in the p-type well (500) forming the source of the split-channel transistor (201). On the source side of the split-channel transistor (201), an NLDD region (21) is provided. The lightly doped region (21) may extend between the source (i.e., the n-type active region (151)) and the gate oxide (300) of the split-channel transistor (201).

[0051] The n-type active region (152) in the substrate area (400) forms the drain of the split-channel transistor (201) (as well as the source of the capacitor, as described above). Isolation between the gate (51) and the drain region (152) of the split-channel transistor (201) is provided by the thick oxide spacer (61). The drain region (152) of the split-channel transistor (201) can be formed without an NLDD implantation region. In other words, the surface of the substrate (400) between the n-type active region (152) and the gate oxide (300) of the split-channel transistor (201) can be native (i.e., of the same dopant polarity and dopant concentration as the substrate (400)). Thus, unlike conventional MOS transistors, the split-channel transistor (201) of [Fig. 3] has an asymmetric LDD structure in that an LDD region is provided between the gate (51) and the source (151) but no LDD region is provided between the gate (51) and the drain (152).

[0052] Advantageously, the absence of an NLDD implantation region in the drain region (152) of the transistor can increase the breakdown voltage between the gate (51) and the drain region (152) of the transistor once the memory cell (1) is programmed. Furthermore, providing the drain of the split-channel transistor (201) as an n-type region surrounded by the p-type (high resistivity) substrate region (400) provides good protection of the transistor against avalanche breakdown of the drain of the split-channel transistor (201) during programming of the memory cell when a large programming current flows in the channel of the split-channel transistor (201).

[0053] The first transistor (200) may be a conventional enhancement n-channel low voltage transistor. The first transistor (200) is formed in the p-type well (500) and includes a gate (50) on a thin gate oxide layer (300). The gate (50) may be formed of poly-Si. The oxide layer (300) of the first transistor (200) may have a thickness of about 2.9 nm when formed using a 0.11 pm MOS process. The gate (50) is connected to the WL pin of the memory cell (1). The drain of the first transistor (200) is provided by the n-type active region (151) (which is also the source of the split-channel transistor (201), as described above). The source and drain regions of the first transistor (200) include conventional NLDD regions 20 and oxide spacers (60). The source (150) of the first transistor (200) is connected to the S pin of the memory cell (1).The semiconductor structure further comprises a p-type active region (90) in the p-type well (500) providing contact with the substrate. The p-type active region (90) is connected to the PSUB pin of the memory cell (1).

[0054] An operation of the memory cell (1) will now be described. The memory cell (1) may be part of a memory array which, in turn, may form with associated peripheral circuitry (e.g. to enable reading and programming of the cells) an OTP memory device. In this case, a data line connected to the data pin (D) may be shared with several memory cells of the memory device (an example arrangement of four memory cells is described below with reference to Figures 8 and 9). As described in detail below, when the memory device is in programming or reading mode, a respective programming or reference voltage is applied to the data pin (D). To enable operation in such a "shared data loop" configuration, the memory cell (1) may be configured to be programmed or read only when selected, and not to interfere with the programming or reading of other memory cells when not selected (as described below, this may be achieved by applying appropriate voltages to the first transistor (200) and the split-channel transistor (201)).

[0055] In general, the memory cell (1) may be selected so that the binary value stored in the memory cell (1) can be read or the memory cell (1) can be programmed. The memory cell (1) may be selected by turning on the first transistor (200), i.e., by applying a selection voltage Vseiect to the WL pin (connected to the gate of the first transistor (200)) and a low voltage (typically 0 V) ​​to the S and PSUB pins. The selection voltage may be higher than a threshold voltage of the first transistor (200), for example, Vseiect = 1.2 V when the memory cell (1) is formed using 0.11 pm MOS processes. In this case, the first transistor (200) is "on" because its gate-source voltage is positive and higher than its threshold voltage.In some embodiments, the selection voltage Vseiect may correspond to a supply voltage at a memory device comprising the memory cell (1) operating.

[0056] To read or program the selected memory cell (1), the appropriate voltages can be applied to the BLK and D pins. In particular, to read the value of the stored bit, a reference current (or a reference voltage) is applied to the data pin (D), and a low voltage (e.g. Vseiect, i.e. about 1.2 V when the memory cell (1) is formed using 0.11 pm MOS processes) is applied to the BLK pin (connected to the gate (51) of the split-channel transistor (201)). In this case, the first transistor (200) and the split-channel transistor (201) are "on", and the potential of the data pin (D) depends on the resistivity of the gate oxide (300) of the capacitor (202).When the memory cell (1) is not programmed, the gate oxide (300) of the capacitor (202) is intact and the potential of the data pin (D) is high (this state may correspond to a logic state "0" of the memory cell (1)). When the memory cell (1) is programmed, the gate oxide (300) of the capacitor (202) is damaged (i.e., shortened) and the potential of the data pin . (D) is low (because both the first transistor and the split-channel transistor are "on"). This state can correspond to a logic "1" state of memory cell (1). Thus, the memory device can determine the stored binary value of memory cell (1), for example, by determining the potential of data pin (D).

[0057] To program the selected memory cell 1, a (high) programming voltage Vpp (e.g., Vpp = 7.4 V when the memory cell 1 is formed using 0.1 Ipm MOS processes) is applied to the data pin D (connected to the top plate 52 of the capacitor 202), and the blocking voltage Vbik is applied to the BLK pin (connected to the gate 51 of the split-channel transistor 201). In general, the blocking voltage may be greater than Vseiect (applied to the WL pin) and less than Vpp (applied to the data pin D). In some examples, the blocking voltage Vbik may be approximately half the programming voltage Vpp, i.e., VMk = Vpp / 2. In this case, the bottom plate of the capacitor (202) is at a low potential since the first transistor (200) and the split-channel transistor are both "on".The programming voltage Vpp is selected to be higher than the breakdown voltage of the gate oxide of the capacitor (202). Therefore, the gate oxide (300) of the capacitor (202) is damaged (i.e., shortened) during programming of the memory cell (1).

[0058] Some particular advantages of the memory cell (1) can be understood by examining in detail the breakdown of the capacitor (202) during the programming of the memory cell (1) which is described in the following with reference to Figures 4 and 5. [Fig.4] shows an equivalent circuit of the memory cell (1) when the memory cell is programmed, and [Fig.5] shows experimentally obtained values ​​of an electric current flowing through the capacitor (202) (during the breakdown of the capacitor (202)). In general, it has been found that the breakdown of the capacitor (202) can be described as a process having three phases: a soft breakdown phase, a hard breakdown phase and a breakdown region formation phase.

[0059] The initial phase of the breakdown (i.e., the soft breakdown phase) begins when a voltage difference between the memory capacitor plates becomes greater than the breakdown voltage of the gate oxide (which occurs, as noted above, when the programming voltage Vpp is applied to the data pin (D) and the potential of the lower plate of the memory capacitor (202) is low, because the first transistor and the split-channel transistor (200, 201) are both "on"). Then, a current Ipp of a few tens of microamperes begins to flow through the memory cell (1) (i.e., through the first transistor and the split-channel transistors (200, 202) to pin S, as shown in [Fig. 4]). At this stage, there is practically no current Ippi in the substrate (400). In this phase, the resistance (10) of the intact gate oxide of the memory capacitor (202) limits the current. The resistance (10) of the intact gate oxide can typically be in the order of tens of MΩ, but this is only an example. It is understood that the resistance (10) of the intact gate oxide depends on the specific geometry of the capacitor (202) and the thickness of the gate oxide (300). Up to this point, the capacitor has not undergone any irreversible transformation, i.e. if the voltage applied to pin D is lowered at this point in the process, the oxide returns to its initial state.At this point, the channel resistances of the first transistor and the split-channel transistors (200, 201) are significantly lower than the resistance of the gate oxide of the unbroken capacitor.

[0060] During the soft breakdown phase, the gate oxide (300) of the capacitor (202) may experience a "self-heating" effect. When the "self-heating" of the gate oxide (300) exceeds a (design-specific) threshold, the "hard breakdown" phase begins, where the programming current Ipp increases sharply to hundreds of microamperes (as shown in [Fig. 5]) and the structure of the gate oxide (300) begins to undergo irreversible changes (i.e., the gate oxide suffers irreversible damage). In general, the programming current Ipp can be determined by the (large) substrate current Ippi and the current flowing through the channels of the transistors of the memory cell Ipp2 (as shown in [Fig. 4]). At this stage, the substrate current Ippi can cause the transfer of material from the top plate (52) of the memory capacitor (202) to the substrate (400).As a result, an efficient pn junction diode (48) and an efficient "native" transistor (33) can be formed, wherein the drain of the transistor (33) can be connected to the diode (48) and the source can be connected to the n-type region (152) (as shown in [Fig. 4]). This novel configuration can be advantageous in that it allows for robust isolation of the memory cell (1) during programming and reading operations when the cell is not selected, which in turn allows for the arrangement and operation of multiple memory cells in a highly integrated manner which is described in detail below with reference to Figures 8 and 9.The transistors (200 and 201) can be configured such that, during the hard breakdown phase, the conductivity of the channels of the transistors (200 and 201) is high enough so that the part Ipp2 of the programming current Ipp is high enough to ensure the non-reversible breakdown of the gate oxide (300) of the memory capacitor (202).

[0061] In particular, as mentioned above, the channel width of the split-channel transistor (201) may be selected to be sufficiently large (e.g., in particular large enough to compensate for any resistance associated with the low doping concentration of the native channel portion (L2)) so that the conductance of the split-channel transistor (201) during the hard breakdown phase may be sufficiently high so as not to significantly limit the programming current Ipp. A particular advantage of the memory cell (1) may be that, by providing a native channel portion on the drain side of the split-channel transistor, the risk of avalanche breakdown (and thus damage to the memory cell) caused by the high programming current is reduced compared to a conventional transistor device with a uniformly doped channel.This risk can be further reduced by providing that the drain of the split-channel transistor (201) (i.e., the n-type active region (152)) does not have an NLDD region.

[0062] Further, the first transistor (200) may be configured to provide a conductivity high enough that the large programming current Ipp2 during the hard breakdown phase can flow through the first transistor (200), thereby ensuring the onset of oxide destruction (in embodiments where the memory cell (1) is formed using 0.11 pm MOS processes, Ipp2 may exceed 200 pA). As noted above, the memory cell is in a selected state, i.e., the first transistor (200) receives a low selection voltage Vseiect at the gate, and a low voltage (e.g., 0 V) ​​at the source. The voltage at the drain may be approximately equal to (VBlk - Vt), where Vt is the threshold voltage of the split-channel transistor (201) (e.g., about 0.8 V).Thus, in embodiments where the blocking voltage VBlk is equal to half the programming voltage Vpp, the drain voltage of the first transistor may be equal to (½Vpp - Vt). A particular advantage of the memory cell (1) may be that the channel length of the first transistor (200) may be shorter than in conventional OTP memory cells since the drain voltage is lower (e.g., about 2.5 V when the memory cell (1) is formed using 0.11 pm MOS processes). This allows the size of the memory cell (1) to be reduced (i.e., the memory cell (1) to be provided with a smaller footprint).

[0063] During the final phase of capacitor breakdown, the resistance of the fractured gate oxide (10) may decrease due to the destruction of the gate oxide (300). The portion of the programming current Ipp2 that flows through the first transistor and the split-channel transistor (200, 201) may change and stabilize at a lower value that can be determined by the common resistance of the gate oxide of the destroyed capacitor (10), the channel resistance of the split-channel transistor (201) and the channel resistance of the first transistor (200). Typically, the resistance of the fractured gate oxide (10) can be in the order of a few tens of kilo-ohms after the breakdown process is complete.

[0064] As mentioned above, the memory cell (1) may be configured to respectively not undergo programming or affect the read signal when the memory signal is not selected. For example, the memory cell (1) may be configured such that, when the memory cell (1) is unprogrammed and unselected, the capacitor (202) does not undergo the breakdown described above in programming mode (i.e., when the programming voltage Vpp is applied to the data pin (D) and the blocking voltage VBlk is applied to the BLK pin). Indeed, the memory cell (1) may be in an unselected state because the first transistor (200) is in an "off" state (e.g., when a low voltage (e.g., 0 V) ​​is applied to the WL, S, and PSUB pins). Thus, in this case, the source of the capacitor (202) may be floating.Therefore, no inversion layer can be formed under the capacitor plate (52) (only a depletion region in the substrate (400)). The capacitance of the depletion region Cdpi can be small compared to the capacitance of the gate Cox. The formed capacitance divider can set the surface potential V i under the capacitor plate (52) close to the potential of the upper poly plate (Vi = VPP*COX / (COX + Cdpi). Therefore, the electric field on the gate oxide (300) of the capacitor (202) is very small (Vpp - Vi « 0 V) ​​and the gate oxide (300) cannot undergo the breakdown process described above.

[0065] In general, the memory cell (1) may be configured such that in programming mode (i.e., when the programming voltage Vpp is applied to the data pin (D), and the blocking voltage VBLK is applied to the BLK pin) and when the memory cell (1) is programmed and not selected, no substantial leakage current flows through the memory cell (1), and no breakdown occurs. As mentioned above, the memory cell (1) may be in an unselected state because the first transistor (200) is in an "off" state (e.g., when a low voltage (e.g., 0 V) ​​is applied to the WL, S, and PSUB pins). As the memory cell (1) is programmed in this example, the drain potential (152) of the split-channel transistor (201) may be close to the programming voltage (due to the breakdown of the gate oxide of the memory capacitor (202)).In this case, the source (151) of the split-channel transistor (201) is floating.

[0066] With reference to Figures 6 and 7, a detailed description of the relevant breakdown voltages of the memory cell (1) is now provided to illustrate that the breakdown voltage of an unselected but programmed memory cell (1) is higher than the programming voltage Vpp (and that the memory cell (1) can therefore be used in an arrangement where several memory cells share a data line connected to pin D without significant risk of breakdown). [Fig. 6] shows a corresponding equivalent circuit and [Fig. 7] shows a cross-section of a portion of the memory cell (1) (programmed and unselected). With reference to [Fig.6], after programming, the equivalent circuit of the memory capacitor (202) may include the ohmic resistor (10) of the broken oxide structure of the memory capacitor (202), the p / n junction diode (48) (formed during the breakdown process of the memory capacitor (202) by material transfer from the plate (52) to the substrate (400)), the transistor (33) described above, and the diodes (46 and 47). A substrate breakdown voltage of the diode (48) may be very high since it is formed in the p-type (high resistivity) substrate (400). The diode (48) may be effectively a gate diode, i.e., its breakdown voltage depends on the potential of the gate (52). For example, the breakdown voltage of the diode (48) may increase as the potential of the plate (52) increases.Thus, when the programming voltage Vpp is applied to pin D, the breakdown voltage of the diode (48) can be sufficiently high (i.e., higher than the programming voltage Vpp, for example, the breakdown voltage of the diode (48) can be about 13.0 V when the memory device (1) is formed using 0.11 pm MOS processes).

[0067] The transistor (33) may be connected to a diode (i.e., its drain and gate may be connected across the resistor (10)). The drain of the transistor (33) may be formed in the aforementioned p / n junction of the substrate (48), the gate of the transistor (33) may be the plate (52), and the source of the transistor (33) may be the source region (152) of the memory capacitor (202). The diode (47) may be a p / n junction between the source region (152) of the memory capacitor (202) and the p-type substrate (400). Like the diode (48), the diode (47) may be provided with a gate. The diodes (47 and 48) may have the plate (52) as a common gate. A breakdown voltage of the diode (47) may be similar to the breakdown voltage of the diode (48). The diode (46) may be a substrate p / n junction between the source region (152) of the memory capacitor (202) and the p-type substrate (400).The diode (46) may be of a conventional type having a breakdown voltage (defined by the manufacturing process) which is in practice typically very high (e.g., about 25 V when the memory device (1) is formed using 0.11 pm MOS processes). As mentioned above, the breakdown voltage between the plate (52). and the source (152) of the memory capacitor (202) is very high, when no NLDD implantation area in the region of the capacitor source is provided. Thus, in general, the lowest breakdown voltages of the equivalent circuit of the capacitor (202) after programming can be determined by the diodes (47 and 48) and can be sufficiently high (i.e., sufficiently higher than Vpp when Vpp is applied to pin D).

[0068] With reference to Figures 6 and 7, the breakdown voltage of the drain of the split-channel transistor (201) is now described (when the memory cell (1) is programmed and not selected). In the equivalent circuit of [Fig.6], the representation of the split-channel transistor (201) comprises two conventional n-channel transistors (32 and 31). Transistor (32) represents the native channel part of the split-channel transistor (201) and can be considered as a conventional low-voltage native-type transistor. The drain of transistor (32) can be connected to the source (152) of the storage capacitor (202). The gate of transistor (32) can be connected to the blocking pin BLK. The source of transistor (32) can be connected to the drain of transistor (31). Transistor (31) represents the enhancement channel part of the split-channel transistor (201) and can be considered as a conventional low-voltage enhancement-type transistor.The drain of transistor (31) can be connected to the source of transistor (32). The gate of transistor (31) can be connected to the BLK pin. The source of the source of transistor (31) can be connected to the drain of the first transistor (200).

[0069] The breakdown voltage of the drain of the split-channel transistor (201) may be partly determined by the breakdown voltage between the gate and the drain of the transistor. As illustrated in [Fig.7], the native channel portion (L2) (represented by the native transistor (32) in the equivalent circuit of [Fig.6]) is located on the drain side of the split-channel transistor (201). As mentioned above, when no NLDD at the drain of the transistor (201) is provided, the breakdown voltage between the gate and the drain of the split-channel transistor (201) is sufficiently high (i.e., it is not a limiting factor in determining the breakdown voltage at the drain).

[0070] The breakdown voltage at the drain of the split-channel transistor (201) may also be determined by the gate (effective) diode (45), shown in [Fig. 6]. The diode (45) may be formed by a p / n junction between the drain region (152) of the split-channel transistor (201) and the p-type substrate (400). The diode (45) may be a gate diode (because the thin gate oxide (300) of the split-channel transistor (201) is very thin), similar to the gate diode (47) described above. Therefore, the breakdown voltage of the diode (45) is very high when the blocking voltage VBlk applied to the gate of the split-channel transistor (201) is sufficiently high (e.g., in embodiments where the memory cell (1) is formed using 0.11 pm MOS processes, the breakdown voltage of the diode (45) can be about 9.0 V when VBlk is equal to 1 / 2VPP).

[0071] In [Fig.6], the gate diode (44) represents p / n injunction between the source (151) and the p-type well (500). The breakdown voltage of the breakdown voltage of the diode (44) may depend on the blocking voltage VBlk applied to the gate of the split-channel transistor (201). For example, when the blocking voltage VBLK is about 1 / 2VPP, the breakdown voltage of the diode (44) may be higher than the breakdown value of conventional diodes of this type (for example, the breakdown voltage may be about 7.0 V instead of about 5.5 V for conventional diodes, when the memory cell is formed using 0.11 pm MOS processes).The breakdown voltage of the diode (44) may be lower than the breakdown voltage of the diode (45) because the p / n junction is formed in the p-type well (500), which may have a higher impurity concentration compared to the high resistivity p-type substrate (400) (in an embodiment where the memory device (1) is formed using a 0.11 pm MOS process, the doping concentrations of the p-type well (500) may be 5.8e+17 cm3 and the doping concentrations of the p-type substrate (400) may be 2e+16 cm3). The diode (43) of [Fig.6] may be a channel p / n junction between the n-type region (151) and the p-type well (500) with a breakdown voltage that may be lower than the breakdown voltage of the gate diode (44) (e.g., conventional diodes of about 5.5 V, when the memory cell is formed using 0.11 pm MOS processes).

[0072] As mentioned above, when the memory cell (1) is programmed and not selected, the drain of the first transistor (200) cannot exceed a value of approximately (VBLK - Vt). Therefore, the drain of the first transistor (200) can be at a relatively low potential. This eliminates (or at least significantly reduces) the risk of a drain-gate breakdown of the first conventional n-channel transistor (200) at low voltage.

[0073] The equivalent circuit of the first transistor (200) may include a diode (42) that represents the p / n junction between the drain (151) and the p-type well (500), and that is similar to the diode (44) described above, i.e., the breakdown voltage of the diode (42) may depend on the potential applied to the gate of the first transistor (200) (due to the thin gate oxide (300). When the memory cell (1) is not selected, the gate potential of the first transistor (200) may be low (0 V). In this case, the breakdown voltage of the diode (42) may be equal to the breakdown voltage of the conventional diode (43) described above. The equivalent circuit of the first transistor (200) may further include a diode (41) that represents the source of the first transistor (200) and may also be a diode gate (similar to diode (42)). As before, when the memory cell (1) is not selected, the gate potential of the first transistor (200) may be low (0 V), and the breakdown voltage of the diode (41) may be equal to the breakdown voltage of the conventional diode (43) described above. The equivalent circuit of the first transistor (200) may further comprise a diode (40) connected in parallel to the diode (41) and having a substrate p / n junction between the n-type region (150) and the p-type well (500). The diode (40) may have a breakdown voltage similar to that of the diode (43) described above. Thus, it is clear from the above description, with reference to Figures 6 and 7, that the breakdown voltage of an unselected but programmed memory cell (1) can be determined by the breakdown voltage on the drain of the split-channel transistor (201), which is greater than the programming voltage Vpp.

[0074] As mentioned above, in addition to having a sufficiently high breakdown voltage, the memory cell (1) is also configured to, when programmed but not selected, prevent any substantial leakage current in programming mode. This point is described in more detail in Figures 6 and 7. In general, no additional leakage current occurs at the drain of the split-channel transistor (201) because, as described above, the breakdown voltage of the diode diode (45) (which presents the drain of the split-channel transistor (201)) is higher than the programming voltage Vpp when the blocking voltage VBlk applied to the BLK pin is approximately 1 / 2VPP. Therefore, no leakage current can flow through the diode (45) to the substrate (400). As shown in [Fig.7], when a potential close to Vpp is applied to the drain (152) of the split-channel transistor (201), the depletion region (14) of the p / n junction at the drain (152) can extend through the native channel portion (L2) and can touch the enhancement channel portion (L1) of the split-channel transistor (201). The length of the enhancement portion (L1) can be selected to avoid a "snap-back" effect (see [Fig.7]). In other words, the length of the enhancement channel portion (L1) can be sufficient to prevent the depletion region (14) from extending to the (floating) source (151) of the split-channel transistor (201). Indeed, if the enhancement portion (L1) is too short, the potential (close to Vpp) of the drain of the split-channel transistor (201) can reach the source (151).This potential is higher than the breakdown voltage of the gate diode (44) (described above) and therefore a leakage current (indicated by "I_leakage_l" in [Fig.7]) can flow from the drain (152) of the split-channel transistor (201), through the depletion region (14) of the channel portions (Ll, L2), the source junction (151) of the split-channel transistor (201) and the substrate (500) to the substrate contact (90). In addition to the leakage current. leakage mentioned above, a "snap-back" effect can also result in an additional leakage current ("I_leakage_2" in [Fig.7]) because the gate diode (42) may also be in a breakdown state. Thus, the additional leakage current can flow through the depletion region (14) of the channel portions (L1, L2), the diode (42) and the substrate (500) to the substrate contact (90). In addition, a "snap-back" can also cause a "punch-through" effect in the channel region of the first transistor (200), which can result in a third leakage current ("I_leakage_3" in [Fig.7]) flowing from the drain (151) of the first transistor (200) through the channel to the source (150) (as shown in [Fig.7]).The aforementioned "snap-back" phenomenon (when the cell is programmed and not selected, and the memory device is in programming mode) and additional leakage currents at the common data pin D (in programming mode) are therefore avoided by appropriately selecting the length (Ll) of the boost portion of the split-channel transistor (201). The memory cell (1) can thus be used in large-volume OTP memories.

[0075] In general, the memory cell (1) may be further configured such that in read mode (i.e., when a reference current is applied to the data pin (D) and a small voltage is applied to the BLK pin to turn on the split-channel transistor (201)) and when the memory cell (1) is not selected (i.e., when the first transistor (200) is "off"), no substantial leakage current flows through the memory cell (1). This is because when the memory cell is not being programmed, there is no current path because the memory capacitor (202) is not broken and the first transistor (200) is "off". Since there is no leakage current, the potential of the data pin (D) is high. When the memory cell is programmed, the source of the split-channel transistor (201) is floating because the first transistor (200) is "off".There is no current path in the memory cell (1) for the reference current, since the drain of the split-channel transistor (201) is at too low a potential (e.g., 1.2 V) to cause leakage from the drain of the split-channel transistor (201). This means that the potential at the data pin (D) remains high.

[0076] The memory cell (1) (described above with reference to Figures 2 to 7) can enable memory devices with high memory density (i.e., a large number of memory cells implemented in a small area). With reference to Figures 8 and 9, an exemplary arrangement is described in which a 4-bit cluster (i.e., four instances of the memory cell (1)) is compactly implemented. [Fig. 8] shows a schematic of the 4-bit cluster and [Fig. 9] shows a corresponding arrangement. In general, the 4-bit cluster can be formed using conventional low-voltage CMOS technology without steps. additional technologies or photolithography (e.g., additional masks). This means that the 4-bit cluster can be manufactured at low cost, allowing its use in high-volume, low-cost OTP memories. Furthermore, as shown in [Fig.8], the 4-bit cluster can be implemented in a highly integrated manner. For example, using 0.11 pm MOS processes, the 4-bit cluster can be implemented in an area of ​​approximately 6.7 pm2 per bit (i.e., per memory cell).

[0077] The 4-bit cluster illustrated in Figures 8 and 9 comprises the first to fourth memory cells (501-504). Each of the memory cells (501-504) can be implemented as an instance of the memory cell (1) described above. As shown in [Fig. 8], the memory cells (501-504) share a common data pin (i.e., the common data pin D is connected to the memory capacitors of the memory cells (501-504)). In addition, the memory cells (501-504) share a common pin BLK (connected to the gates of the split-channel resistors of the memory cells (501-504)).

[0078] The 4-bit cluster may further comprise select pins (WL1, WL2, SI and S2). The select pin (WL1) may be connected to the WL select pins of the memory cells (501 and 502), and the select pin (WL2) may be connected to the WL select pins of the memory cells (503 and 504). The select pin (SI) may be connected to the S pins of the memory cells (501 and 503), and the select pin (S2) may be connected to the S pins of the memory cells (502 and 504). The memory cells (501-504) may share a common PSUB pin which may be connected to ground. The 4-bit cluster makes it possible to organize a memory matrix with which it is possible to realize high-density OTP memories (i.e., OTP memories with large ratios between storage capacity and required area). This is illustrated in [Fig.9], where a 4-bit cluster arrangement is shown. The diagram in [Fig.9] can be fabricated using 0.11 pm MOS processes. The small memory area of ​​the memory array is achieved by sharing the contacts with the data pin (D) and the select pin S between 4 adjacent cells.

[0079] In programming or reading mode, only one of the four memory cells (501-504) is selected. The selected memory cell can then be programmed or read as described above with reference to memory cell (1). Each memory cell (501-504) can be selected in programming or reading mode by applying the appropriate voltages to the pins (WL1, WL2, SI and S2). Table 1 shows examples of voltage levels that can be applied to the pins (WL1, WL2, SI and S2) respectively to select the different memory cells (501-504). For example, the memory cell (501) can be selected when WL1 = Vseb WL2 = 0 V, SI = 0 and S2 = Vsei; memory cell (502) can be selected when WL1 = Vsei, WL2 = 0 V, SI = Vsei and S2 = 0 V, etc. As shown above, the selection voltage Vseiect can be about 1.2 V when the memory cells are formed using 0.11 pm MOS processes. Memory cell (501) Memory cell (502) Memory cell (503) Memory cell (504) WL1 vsel vsel OV OV WL2 0 V 0 V vsel vsel SI 0 V vsel OV vsel S2 vsel 0 V vsel OV

[0080] When one of the memory cells is selected, the other memory cells are not selected. As described above with reference to memory cell (1), the memory cells may be configured not to affect the programming or reference voltage when not selected.

[0081] Certain embodiments have been described, these embodiments have been presented solely by way of example and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; further, various omissions, substitutions, and modifications of the form of the devices, methods, and products described herein may be made without departing from the spirit of the inventions. The appended claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.

Claims

Claims

1. A one-time programmable memory cell (1) comprising: a transistor (201) comprising a drain (152), a source (151) and a channel between the drain and the source, the transistor being connected to a data storage element (202) and a memory cell selection element (200); the channel of the transistor comprising first and second channel portions (L1, L2), a dopant concentration in the first channel portion (L1) being higher than in the second channel portion (L2).

2. The one-time programmable memory cell (1) according to claim 1, wherein the drain of the transistor (201) is connected to the data storage element (202) and the source of the transistor is connected to the memory cell selection element (200), and wherein the second channel portion (L2) is immediately adjacent to the drain (152) of the transistor.

3. A one-time programmable memory cell (1) according to claim 1 or claim 2, wherein the transistor (201) further comprises a gate (51), and the source, the gate and the drain are arranged next to each other in a length direction of the transistor, and wherein the first and second channel portions (L1, L2) extend along the length direction of the transistor respectively over a first and a second length.

4. A one-time programmable memory cell (1) according to claim 3, wherein the first length is equal to or greater than one-third of the second length.

5. A one-time programmable memory cell (1) according to claim 3 or claim 4, wherein the first length is equal to or less than three times the second length.

6. A one-time programmable memory cell (1) according to any one of claims 3 to 5, wherein the first length is 50% greater than the second length.

7. A one-time programmable memory cell (1) according to any one of claims 3 to 6, further comprising a lightly doped source region (21) extending between the source and the gate of the transistor.

8. A one-time programmable memory cell (1) according to any preceding claim, wherein said drain (152) and said source (151) comprise respective n-doped regions, and the first channel portion (L1) comprises a p-doped region.

9. A one-time programmable memory cell (1) according to any preceding claim, wherein the transistor (201) is formed on a substrate (400) having a substrate dopant polarity and a substrate dopant concentration, and wherein the second channel portion (L2) has a substrate dopant polarity and a dopant concentration being substantially equal to the substrate dopant polarity and the substrate dopant concentration.

10. A one-time programmable memory cell (1) according to any preceding claim, wherein the first channel portion (L1) is adjacent to the second channel portion (L2).

11. A one-time programmable memory cell (1) according to any preceding claim, wherein the memory cell selection element (200) comprises an additional transistor.

12. A one-time programmable memory cell (1) according to claim 11, wherein an operating voltage of the additional transistor is less than or equal to 1.2 V.

13. A one-time programmable memory cell (1) according to claim 11 or claim 12, wherein the data storage element (202) is configured to be programmable by applying a programming voltage, the programming voltage being greater than an operating voltage of the additional transistor, and wherein the programming voltage applied to the additional transistor would damage the additional transistor.

14. A one-time programmable memory cell (1) according to any preceding claim, wherein the one-time programmable memory cell (1) does not include a lightly doped drain region extending between the drain (151) and the gate (51) of the transistor (201).

15. A one-time programmable memory cell (1) according to any preceding claim, wherein the data storage element (202) is a capacitor formed on a substrate (400), the capacitor comprising:

16.

17.

18. a source (152) provided in the substrate; a gate oxide layer (300) formed on the substrate; and a top plate (52), for connection to a data pin, provided above the gate oxide layer, wherein the one-time programmable memory cell (1) does not include a lightly doped source region extending between the capacitor source and the capacitor gate oxide layer. A method of programming or reading the memory cell according to any one of the preceding claims, the method comprising: applying a selection voltage to the selection element of the memory cell; applying a blocking voltage to the gate of the transistor, and applying a programming or reading voltage to the data storage element to program or read the selected memory cell, wherein the blocking voltage is higher than the selection voltage and lower than the programming voltage. A memory device comprising the memory cell of any one of claims 1 to 15. Memory device comprising: a first, a second, a third and a fourth memory cell according to any one of the preceding claims, the memory cell selection element of each memory cell further comprising a respective additional transistor comprising a gate; a shared data line for applying a programming or reading voltage, the shared data line being connected to the data storage element of each memory cell; a clamp line for applying a clamp voltage, the clamp line being connected to the gate of the transistor of each memory cell; a first and a second selection line, the first selection line being connected to the additional transistor of the first memory cell and to the additional transistor of the third memory cell, the second selection line being connected to the additional transistor of the second memory cell and to the additional transistor of the fourth memory cell, and a first and a second word line, the first word line being connected to the gate of the additional transistor of the first memory cell and to the gate of the additional transistor of the second memory cell, the second word line being connected to the gate of the additional transistor of the third memory cell and to the gate of the additional transistor of the fourth memory cell, and wherein the device is arranged such that at least one of the four memory cells can be selected for programming or reading by applying a voltage to at least one of the select and word lines.

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