Electrochemical charge storage device

Abstract

One aspect of the invention relates to an electrochemical storage device comprising an ionic transistor and an ionic capacitor electrically connected in series. Figure to be published with the abstract: Figure 4f

Description

Title of the invention: Electrochemical charge storage device TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of charge storage components, in particular electrochemical charge storage components.

[0002] In particular, the invention relates to an electrochemical charge storage device that can be used in neuromorphic circuits. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] The use of artificial intelligence algorithms for a wide range of applications has exploded in recent years. These algorithms often require so-called neuromorphic architectures, which aim to mimic the synaptic processing that occurs in the human brain. Thus, neuromorphic architectures (or circuits) are electronic circuits designed to emulate the behavior of biological neurons and neural networks.

[0004] Neuromorphic architectures, such as IBM™ Resistive Processing Units (RPUs), are based in part on resistive memory devices that use a cross-element array to achieve good performance in terms of memory density, energy efficiency and speed, by reducing data movement during computation and taking advantage of multi-level analog states. Such resistive processing units can accelerate the training of deep neural networks using little energy. It is indeed possible to reproduce the operation of a biological neuron by using an array of resistive memories associated with respective synaptic weights.

[0005] Existing devices based on conductive filaments or phase-change materials suffer from excessive write noise. In these devices, it is difficult to reduce the noise and lower the switching voltage while ensuring long-term data retention, which represents a significant limitation in terms of accuracy, energy efficiency, and scalability of these devices. To implement efficient neuromorphic systems, it is therefore preferable to use resistive memory elements that switch using a different mechanism than that used in filament-forming or phase-change devices.

[0006] This is why, recently, a new category of components has been studied for these neuromorphic applications: the ionic transistor, which can be used as synaptic transistor. The operation of the ionic transistor is based on the movement of ions between the source and the drain, which makes it possible to modify the conductance value of the transistor. Such a transistor is notably described in the article by Nguyen et al. "An Ultralow Power LixTiO2-Based Synaptic Transistor for Scalable Neuromorphic Computing", published in Advanced Electronic Materials in 2022.

[0007] The ionic transistor can advantageously be in a plurality of non-volatile states (several tens), each state corresponding to a respective conductance value. In the context of neuromorphic applications, the conductance values ​​of the transistor correspond to the different synaptic weight values. However, there is a need to easily read these synaptic weight values, in order to use them in neuromorphic applications. Summary of the invention

[0008] The invention provides a solution to the problem mentioned above, by proposing an electrochemical charge storage device (or simply hereinafter "electrochemical storage device") comprising an ionic transistor and an ionic capacitor connected in series. Ionic transistors can be placed in a multitude of conductance levels, and require a very small amount of energy to switch from one conductance level to another. In addition, ionic capacitors have large capacitance densities. This property makes it possible to connect them in series with ionic transistors. Putting an ionic transistor and an ionic capacitor in series effectively simulates synaptic connections and the simulation of the membrane potential of neurons, which makes it a viable approach for the design of complex and powerful neuromorphic systems.

[0009] Furthermore, it is possible to manufacture, on the same substrate, an ionic transistor and an ionic capacitor in series, by pooling a large part of the manufacturing steps of the two components. This makes it possible to obtain a compact device whose manufacture is relatively simple and inexpensive.

[0010] One aspect of the invention thus relates to an electrochemical charge storage device comprising an ionic transistor and an ionic capacitor,

[0011] the ionic transistor comprising: • a layer forming a reservoir of ions, called a reservoir layer; • a source electrode in contact with a part of the reservoir layer; • a drain electrode in contact with another portion of the reservoir layer, the drain electrode and the source electrode being physically separated from each other, the source electrode and the drain electrode each being made of an electrically conductive material; and • a gate electrode in an electrically conductive material, the gate electrode being separated from the reservoir layer by an ionically conductive layer in an ionically conductive and dielectric material, the ionically conductive layer being in contact with the source electrode and with the drain electrode;

[0012] the ionic capacity comprising two electrodes, each of the two electrodes being in an electrically conductive material, the ionic capacity comprising an ionic conductive layer separating the two electrodes of the ionic capacity, the ionic conductive layer of the ionic capacity being in an ionic conductive and dielectric material;

[0013] wherein the ionic transistor and the ionic capacitor are electrically connected in series.

[0014] The reservoir layer is a layer in a material comprising ions of a certain type (for example Li+). The reservoir layer may be in a material called “ion insertion material”, or “insertion compound” or “ion intercalation material”, i.e. a material which allows the penetration of a certain type of ions, without altering its properties. In the following, the reservoir layer is also called “channel layer” or “ion insertion material layer”. It is noted that, above, an “ionic conductive material” designates a material which conducts the same ions as those of the reservoir layer.

[0015] When the ionic capacitance has a "stacked" structure on the substrate (in the sense that the electrodes extend along a direction that corresponds to the main direction of the substrate), the terminology "top electrode / bottom electrode" can be used for the electrodes of the ionic capacitance. The bottom electrode corresponds to the electrode closest to the substrate, while the top electrode corresponds to the electrode furthest from the substrate.

[0016] By "electrically connected in series" it is meant that one of the electrodes of the capacitor is connected to one of the electrodes (hereinafter referred to as the "bottom electrode" for the sake of simplification) among the source electrode and the drain electrode of the transistor. Thus, the source electrode of the transistor, the channel of the transistor, the drain electrode of the transistor and the bottom electrode of the capacitor are connected. In other words, the output current of the transistor corresponds to the input current in the capacitor.

[0017] By connecting an ionic transistor and an ionic capacitor in series, it is possible to read the value of the conductance of the ionic transistor (and therefore the synaptic weights, in a neuromorphic system) from the charging time of the ionic capacitor. It is noted that the use of an ionic capacitor is important. For example, it is not possible to replace it with a dielectric capacitor due to the large range of possible conductance values ​​of the ionic transistor, as this would lead to degradation of the dielectric capacitor. In addition, the construction of a circuit connecting an ionic transistor and an ionic capacitor can be advantageously simplified because these components use common layers of materials. Thus, certain manufacturing steps can be shared.

[0018] It is noted that the ionic transistor (or synaptic transistor) and the ionic capacitance (or ionic capacitor, or ionic supercapacitor) are two components known from the state of the art. However, in the state of the art, the ionic capacitance is used as a full-fledged electrochemical storage element and is not connected in series to an ionic transistor to be able to read the conductance values ​​thereof.

[0019] In embodiments of the invention, the ionic conductive layer of the ionic transistor and the ionic conductive layer of the ionic capacitor are made of the same ionic conductive and dielectric material.

[0020] This property advantageously makes it possible to mutually deposit the ionic conductive layer of the ionic transistor and the ionic conductive layer of the ionic capacitor. In particular, these two ionic conductive layers can be formed from the same layer deposited and structured on the surface of a substrate on which the source electrode, the channel and the drain electrode of the transistor as well as the lower electrode of the ionic capacitor are mounted.

[0021] For example, the ionic conductive and dielectric material may be a lithium phosphorus oxynitride LiPON, a lithium silicon phosphorus oxynitride LiSiPON, a lithium germanium phosphorus sulfide LGPS, a lithium lanthanum zirconium oxide LiLaZrxOy or a lithium lanthanum tantalum oxide LiLaTaOx.

[0022] LiPON can be used for an ionic transistor and an ionic capacitor operating on the basis of lithium Li+ ions (i.e., the operation of which is based on the circulation of Li+ ions). In these embodiments, the channel of the ionic transistor can be made of a material for inserting Li+ ions, for example a transition metal oxide capable of intercalating Li+ ions. Of course, the invention applies to other charge-carrying ions, for example Na+, H+, K+, Cu+ ions, etc.

[0023] The electrically conductive material in which the electrodes of the ionic capacitor and / or the source, drain or gate electrodes of the ionic transistor are made may be, for example, one of: titanium (Ti), tungsten (W), molybdenum (Mo), nickel (Ni) or platinum (Pt).

[0024] The reservoir layer may be made, for example, from one of the following materials: titanium dioxide (TiO2), lithium cobalt dioxide (LiCoO2), lithium niobate (LiNbOx), tungsten trioxide (WO3), vanadium oxide (VOX), oxide nickel (NiOx), manganese oxide (MnOx) - and generally transition metal oxides, molybdenum disulfide (MoS2), graphene.

[0025] In embodiments, the reservoir layer and the ionic conductive layer of the ionic transistor are made of the same ionic conductive and dielectric material.

[0026] In embodiments, the ionic conductive layer of the ionic transistor and the ionic conductive layer of the ionic capacitor may have the same thickness.

[0027] Thus, these two ionic conductive layers can be formed by depositing a single layer of constant thickness and structuring it in two distinct parts, one corresponding to the ionic conductive layer of the ionic transistor and the other part corresponding to the ionic conductive layer of the ionic capacitor.

[0028] Advantageously, the ionic transistor and the ionic capacitor can be located on the same substrate, in a monolithic manner.

[0029] By "located on the same substrate", it is understood that the ionic transistor and the ionic capacitor are integrated on the same substrate plate. This allows cointegration of the two components in parallel, with shared manufacturing steps. In particular, at least some layers are derived from the same deposited and structured layer of material. It should be noted that "substrate" means the raw substrate (i.e. a Si wafer for example) but also a raw substrate on which one or more semiconductor or insulating layers would be deposited. By "monolithic" is meant "in one piece." In other words, the ionic transistor and the ionic capacitor are integrated on the same substrate and form a unit.

[0030] For example, the ionic transistor and the ionic capacitor can be mounted on the same level of the substrate.

[0031] In particular, the substrate may comprise, on a first level, CMOS type components, and, on a second level, the ionic transistor and the ionic capacitance. For example, the manufacturing of the ionic transistor and the ionic capacitance may be done in “Back End Of Line” on a substrate integrating CMOS, subject to compliance with maximum temperatures of the order of 450°C.

[0032] In embodiments, the substrate may include a recess, wherein at least a portion of the ionic capacitance is accommodated in the recess. The recess may be a blind hole.

[0033] This makes it possible to increase the exchange surface between the lower and upper electrodes of the ionic capacity, and therefore the value of the capacity.

[0034] In these embodiments, one of the electrodes of the ionic capacitor, called the lower electrode, extends along an inner surface of the recess, the ionic conductive layer of the ionic capacitor at least partially covers the electrode lower electrode of the ionic capacitance and the other electrode of the ionic capacitance, called the upper electrode, at least partially covers the ionic conductive layer of the ionic capacitance.

[0035] In embodiments, the source electrode of the ionic transistor, the drain electrode of the ionic transistor and one of the electrodes, called the lower electrode, of the ionic capacitor may be made of the same electrically conductive material and have the same thickness.

[0036] This property makes possible a simplified manufacture of these electrodes by deposition and structuring of the same layer of electrically conductive material.

[0037] In particular, the lower electrode of the ionic capacitor and one of the drain electrode and the source electrode of the ionic transistor may be common.

[0038] By "common", it is understood that the device comprises a "continuous" layer (i.e. without discontinuities, for which there is no interruption) which plays the role of both drain / source electrode of the ionic transistor and lower electrode of the ionic capacitor. For example, one of the ends of the continuous layer corresponds to the drain or source electrode of the transistor, and the other end to the lower electrode of the capacitor.

[0039] Furthermore, the gate electrode of the ionic transistor and the other electrode, called the upper electrode, of the ionic capacitor may be made of the same electrically conductive material. For example, this electrically conductive material may be (but is not obligatory) the same material as that of the source electrode of the ionic transistor, the drain electrode of the ionic transistor and the lower electrode of the ionic capacitor.

[0040] In particular, the gate electrode of the ionic transistor and the upper electrode of the ionic capacitor may have the same thickness. Thus, these two electrodes may be formed from a deposition and structuring of a single layer of this electrically conductive material.

[0041] In some embodiments, the device may include a plurality of ionic transistors connected in parallel, each ionic transistor of the plurality of ionic transistors being connected in series with the ionic capacitor.

[0042] By "connected in parallel" it is understood that the transistors have a common source electrode and a common drain electrode.

[0043] Another aspect of the invention relates to a circuit comprising an electrochemical storage device as defined above, the circuit further comprising a comparator block connected in series to an output of the ionic capacitor, the comparator block being configured to trigger a signal when a voltage across the ionic capacitor reaches a reference voltage value.

[0044] In embodiments, the comparator block comprises an operational amplifier receiving, on one input, the voltage across the ionic capacitance and, on another input, the reference voltage value, the signal being triggered when the voltage across the ionic capacitance reaches the reference voltage value, the signal corresponding to a response of an artificial synapse.

[0045] Furthermore, the circuit may comprise means for determining a time taken by the ionic capacitor for the voltage across its terminals to reach the reference voltage.

[0046] It is thus possible to determine the charging time of the ionic capacitance as a function of the time elapsed between the generation of a current flowing between the ionic transistor and the ionic capacitance and the triggering of the event, and to deduce therefrom an (approximate) value of the conductance of the ionic transistor, this charging time corresponding to a synaptic weight.

[0047] Another aspect of the invention relates to a method for manufacturing an electrochemical charge storage device as defined above. This method successively comprises: • depositing, on a substrate, a first layer of electrically conductive material, and structuring said first layer so as to obtain a first part of the first layer and a second part of the first layer having no contact points, the first part of the first layer corresponding to one electrode among a source electrode and a gate electrode of the ionic transistor, the second part of the first layer corresponding to the other electrode among the source electrode and the drain electrode of the ionic transistor and to a first electrode among the two electrodes of the ionic capacitor; • deposition of the reservoir layer, the reservoir layer being in contact with the source electrode and the drain electrode of the ionic transistor; • deposition of an ionic conductive layer in an ionic conductive and dielectric material, and structuring of the ionic conductive layer so as to obtain a first part of the ionic conductive layer and a second part of the ionic conductive layer having no contact point, the first part covering the reservoir layer and being in contact with the source electrode and the drain electrode of the ionic transistor, the second part at least partially covering the first electrode of the ionic capacitor; and • deposition of a second layer of electrically conductive material, and structuring of said second layer so as to obtain a first part of the second layer and a second part of the second layer having no contact points, the first part of the second layer covering partially the first part of the ionic conductive layer and having no contact point with the first part of the first layer and the second part of the first layer, the second part of the second layer at least partially covering the second part of the ionic conductive layer and having no contact point with the second part of the first layer, the first part of the second layer corresponding to the gate electrode of the ionic transistor, the second part of the second layer corresponding to a second electrode among the two electrodes of the ionic capacitor, the second electrode being distinct from the first electrode.

[0048] It is thus possible to manufacture an electrochemical storage device monolithically on the same substrate, by pooling certain steps to manufacture both the elements making up the ionic transistor and the elements making up the ionic capacitor. This is made possible by the fact that the ionic transistor and the ionic capacitor are composed of layers of similar materials. This results in simplicity of manufacture, and a compact electrochemical storage device suitable for neuromorphic applications.

[0049] In particular, the deposition of at least one layer among the first layer of electrically conductive material, the ionically conductive layer and the second layer of electrically conductive material may be a conformal deposition.

[0050] By “conformal deposition” is meant a deposit conforming to the surface on which the layer of material is formed and having the same thickness over its entire deposition surface.

[0051] Thus, a single layer can be deposited and then structured to form several elements of the electrochemical storage device according to the invention.

[0052] Finally, the invention also relates to a method for storing charges using an electrochemical storage device as defined above, comprising: • applying a voltage to the gate electrode of the ionic transistor, so as to set a predefined conductance value for the ionic transistor; and • generate a current flowing between the ionic transistor and the ionic capacitor, an intensity value of the output current of the ionic transistor corresponding to an input value of the input current of the ionic capacitor.

[0053] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0054] Other characteristics and advantages of the invention will appear on reading the description, which can be read in conjunction with the figures. These figures are presented for information purposes only and in no way limit the invention.

[0055] [Fig. 1a], [Fig. 1b] Figures 1a and 1b represent a state-of-the-art ionic transistor.

[0056] [Fig.2] [Fig.2] represents a state-of-the-art ionic capacity.

[0057] [Fig.3] [Fig.3] represents an example of a neuromorphic system comprising an electrochemical storage element according to an embodiment of the invention.

[0058] [Fig.4a], [Fig.4b], [Fig.4c], [Fig.4d], [Fig.4e], [Fig.4f] Figures 4a to 4f illustrate steps of a method of manufacturing an electrochemical storage element according to an embodiment of the invention.

[0059] [Fig.5] [Fig.5] represents an example of a flowchart of a method of manufacturing an electrochemical storage element according to an embodiment of the invention.

[0060] [Fig.6] [Fig.6] represents an example of a flowchart of a charge storage method using an electrochemical storage element according to an embodiment of the invention. DETAILED DESCRIPTION

[0061] [Fig. 1a] represents an ionic transistor 1 according to the state of the art.

[0062] The ionic transistor 1 is an analog transistor mounted on a substrate 10, in particular made of silicon Si, covered with a layer 11 of dielectric material (for example, silicon dioxide SiO2), which comprises a channel 14 of variable electrical conductivity, a source electrode 13 (also called simply "source") and a drain electrode 12 (also called simply "drain"). It is noted that in certain embodiments the assembly formed by the substrate 10 and the layer 11 of dielectric can be replaced by a single layer of dielectric material. The drain 12 and the source 13 are separated from each other by the channel 14, so that the drain 12 and the source 13 have no physical contact point. For example, the drain 12 and the source 13 can be deposited on two portions of a surface of the layer 11 of dielectric material, the two portions of the surface of the layer 11 of dielectric material being spaced from each other by, for example, a few tens of nanometers.The drain 12 and the source 13 are in an electrically conductive material. The channel 14 is in an ion insertion material. It is noted that the source and drain electrodes may be interchanged (in particular, in [Fig.1a], the electrode 12 may represent the source and the electrode 13 may represent the drain).

[0063] The ionic transistor 1 further comprises a layer 15 of a material which is both ionic and dielectric, separating the channel 14 from an electrode 16 called the gate, positioned on the upper surface of the layer 15 of material which is both ionic and dielectric conductor. The gate electrode 16 (also called simply "gate") is made of an electrically conductive material. The layer 15 therefore allows the transport of ions between the channel 14 and the gate electrode 16, but blocks the transport of electrons. It is understood that the layer 15 is conductive for the same ions as the ion insertion material making up the channel 14. For example, if the channel 14 is in a material allowing the intercalation of Li+ ions, the material of the layer 15 is conductive for the Li+ ions.

[0064] The ionic transistor 1 can be manufactured by successively depositing (and structuring) the layers which compose it (deposition of the layers forming the drain 12 and the source 13, then deposition of the layer 14 forming the channel, then deposition of the layer 15 of ionic and dielectric conductive material, and finally deposition of the layer 16 forming the gate electrode 16), for example by a lithography process (photolithography or electronic lithography).

[0065] The channel 14 is in an ion insertion material, the electrical conductivity of which depends on its oxidation level. For example, the channel may be in an inert material such as lithiated components such as LixCoO2, LixNiO2, LixMn2O4, LixV2O5, Lix WO3, LixM03, LixTi50i2, where x is the fraction of lithium in the component.

[0066] In a non-limiting manner, the channel 14 may comprise LiCoO2, the layer 15 of ionic and dielectric conductive material may comprise lithium phosphorus oxynitride (LiPON), which is a material that can conduct Li+ ions from the channel 14.

[0067] It is noted that other layers may be added to the ionic transistor 1, for example an interlayer of an ion insertion material located between the channel layer 14 and the layer 15 of ionic and dielectric conductive material. Furthermore, it is noted that the structure of the ionic transistor may differ from the example shown in [Fig.1a]. For example, according to certain embodiments, the channel layer 14 may completely cover the drain 12 and the source 13, as in application US 10,429,343 for example.

[0068] The oxidation level of channel 14 can be modified by applying a voltage VG applied between gate 16 and source 13. When a voltage VG is applied between gate 16 and source 13, this induces a migration of the ions between gate 16 and channel 14, which has the effect of modifying the electrical conductance of channel 14 between source 13 and drain 12, and therefore the logic state of the transistor, a logic state being associated with a respective electrical conductance value of the transistor. The different (normalized) conductance values ​​of the ionic transistor as a function of the voltage applied between gate 16 and source 13 are shown in [Fig.lb]. By conductance of the ionic transistor is meant the electrical conductance of channel 14.

[0069] To obtain the curve of [Fig.lb], successive voltage pulses were applied between the gate 16 and the source 13. In the example of [Fig.lb], each voltage pulse has an amplitude of ±100 mV and a width of 0.1 second. These values ​​are provided as an example and are not exhaustive. The curve of [Fig.lb] represents the variation of the conductance of the transistor (on the ordinate) as a function of the voltage pulse number n (on the abscissa). To obtain the curve of [Fig.lb], 50 successive pulses of negative amplitude were applied (increasing part of the curve, called the potentiation phase), then 50 successive pulses of positive amplitude were applied (decreasing part of the curve, called the depression phase).

[0070] It appears from [Fig. 1b] that the conductance of channel 14 can be reversibly modified according to the voltage VG applied between gate 16 and source 13. Furthermore, the variation in the conductance value is linear during the application of a constant non-zero voltage value. It increases linearly when a negative amplitude voltage pulse is applied, and it decreases linearly when a positive amplitude voltage pulse is applied. Furthermore, the application of a positive amplitude voltage pulse “cancels out” the effects of applying a voltage pulse of the same duration and opposite amplitude (and vice versa), in the sense that it returns the conductance value to the initial value.

[0071] It is thus possible to modify the conductance of the ionic transistor 1 of [Fig. 1a] by adjusting the value of the voltage VG applied between the gate 16 and the source 13. Once the ionic transistor has a certain conductance value, a voltage VSD is applied between the source 13 and the drain 12 and a current flows, the value of the current intensity being fixed by the conductance value of the transistor.

[0072] The different conductance values ​​associated with the different current pulse numbers correspond to logic states (or "conductance states"). Each logic state is non-volatile, and the transition from one logic state to the next state requires very low energy (e.g., an amount of energy per active surface of the order of fj / pm2). Furthermore, as shown in [Fig.lb], a large number (several tens) of logic states can be achieved in potentiation and depression in a controlled manner (via the applied voltage VG), with, as mentioned above, a response linearity that is a function of the conductance range considered.

[0073] It is noted that the transition speed between two successive logic states of the ionic transistor depends partly on the thickness of the channel layer 14 (the thickness corresponding to the dimension along the y axis in [Fig.1a]): the thinner the channel layer 14, the higher the transition speed between two successive logic states. The thickness of the channel layer 14 can thus be fixed, for example, between 1 and 500 nm.

[0074] The transition speed between two successive logic states also depends in part on the thickness of the layer 15 of ionic and dielectric conductive material: the thinner the layer 15 of ionic and dielectric conductive material, the higher the transition speed between two successive logic states. The thickness of the layer 15 of ionic and dielectric conductive material can thus be fixed, for example, between 1 and 200 nm.

[0075] As detailed above, the ionic transistor is an analog transistor allowing several dozen states (which is currently difficult to obtain from dielectric transistors and with resistive memories), which makes it a component of choice for reproducing the functioning of synapses, which, in the human brain, allow neurons to be connected to each other. In the human brain, neurons start to activate when the synapses have totaled a certain number of electrical impulses, which is made possible by a transistor with several dozen states.

[0076] Furthermore, the ionic transistor exploits the same electrochemical reaction as a synapse, which gives it excellent energy efficiency, of the same order of magnitude as a human brain synapse.

[0077] These properties make the ionic transistor a component particularly suitable for neuromorphic applications.

[0078] [Fig.2] represents an ionic capacity 2 (also called supercapacitor) according to the state of the art.

[0079] An ionic capacitor is an electrochemical storage component, of the supercapacitor type, composed of materials exclusively in solid form. An ionic capacitor can be charged and discharged by connecting it to an electrical circuit. Charge storage is achieved through changes in the materials that make up the ionic capacitor during charging and discharging. Indeed, when a voltage is applied to the terminals of the ionic capacitor, ion depletions / concentrations occur at the two ionic conductor / electrode interfaces.

[0080] As shown in [Fig.2], an ionic capacitor 2 typically comprises a substrate 20 covered with a first layer 21 of dielectric. The substrate 20 is a raw substrate (i.e., untreated), or it may have already undergone treatment so that other electronic components or layers are already present thereon. In the example of [Fig.2], the substrate 20 and the dielectric layer 21 of [Fig.2] are crossed by a cavity covered with a layer 22 of electrically conductive material. The cavity is here a blind hole whose bottom is located at the level of the substrate 20, close to the lower surface of the substrate 20. This layer 22 of electrically conductive material at least partially covers the “free” surface 21a of the first layer 21 of dielectric (i.e., the surface 21a which is not against the substrate 20 and which is not along the formed cavity) on either side of the cavity. The layer 22 of electrically conductive material forms one of the electrodes of the ionic capacity 2, called here the bottom electrode. The layer 22 of electrically conductive material is covered (at least partially) with a layer 23 of a material that is both ionic and dielectric (ionic dielectric). This layer 23 of ionic conductor is covered (at least partially) with a layer 24 of electrically conductive material, which forms the other electrode of the ionic capacity 2, called the top electrode. The lower electrode 22 and the upper electrode 24 are therefore electrically isolated from each other by the layer 23, which nevertheless allows the ions to circulate between the two electrodes 22 and 24. A charging voltage Vc then appears between the input and the output of the ionic capacity 2..

[0081] It is noted that the example shown in [Fig.2] is not limiting and that other configurations are possible. For example, in certain configurations, the cavity only passes through the first dielectric layer 21. Furthermore, the shape of the cavity is not limiting, and can be replaced by a pore in a porous dielectric layer 21, as described in application EP3570307.

[0082] In the example of [Fig.2], the lower electrode 22, the ionic dielectric layer 23 and the upper electrode 24 of the ionic capacitor 2 are arranged according to a MIM (metal - insulator - metal) structure in which the insulator is an ion-conducting dielectric (ionic dielectric), but other configurations are possible, for example a MOIM (metal - oxide - ionic dielectric - metal) configuration in which an oxide layer is intercalated between the lower electrode and the ionic dielectric layer, as in application EP3570307.

[0083] The presence of the cavity in the assembly formed by the substrate 20 and the dielectric layer 21 of [Fig.2] is not obligatory, but it advantageously makes it possible to increase the effective surface area for accumulation of charges between the two electrodes 22 and 24. Furthermore, it is noted that the ionic capacity 2 can be formed according to a planar or three-dimensional configuration, a three-dimensional configuration advantageously making it possible to increase the effective surface area for accumulation of charges between the two electrodes per unit of geometric surface area on the substrate, and therefore to increase the capacity density of the ionic capacity 2 (by acting solely on the geometry of the ionic capacity).

[0084] The application of a voltage between the lower electrode 22 and the upper electrode 24 induces two distinct physical phenomena: on the one hand, the establishment of a double electrochemical layer between the ionic conductor 23 and the two electrodes 22 and 24 (appearance of an ionic capacitance), and on the other hand, the dielectric polarization of the ionic conductor 23 (appearance of a dielectric capacitance). The combination of these two phenomena gives the ionic capacity a very high power density per unit area, of the order of a few tens of pF / mm2, that is to say several orders of magnitude higher than the power densities of MOS or MIM type dielectric components.

[0085] [Fig.3] represents an example of a neuromorphic system comprising a electrochemical storage element according to one embodiment of the invention.

[0086] The electrochemical storage element 36 of [Fig. 3] comprises a resistive element 30 and a capacitive element 34 connected in series. The resistive element 30 comprises a single ionic transistor or several ionic transistors 32a, 32b, ..., 32n connected in parallel (in the sense that each transistor has a common source and drain), as shown in [Fig. 3]. Each ionic transistor 32a, 32b, ..., 32n models a synapse and is associated with a respective conductance value that corresponds to a respective synaptic weight, which can be stored in the capacitor 34 (along with the other synaptic weights of the other transistors). A voltage Vb V2, ..., Vn is applied between the gate and the source of each of the ionic transistors 32a, 32b, ..., 32n so as to vary their conductance values. When a voltage Vin is applied between the source and the drain, this generates a current whose intensity is a function of the total conductance of the resistive element 30.

[0087] The connection, in series, of a resistive element 30 from ionic transistors 32a, 32b, ..., 32n and of a capacitive element 34 from at least one ionic capacitance has the following advantages. On the one hand, the resistive element can be in a plurality of non-volatile analog states (which correspond to different conductance values), the transition from one state to the other requiring a small amount of energy, which makes the resistive element 30 a component particularly suitable for neuromorphic applications. However, due to the wide range of conductance values ​​of the resistive element 30, it is necessary to have a capacitance which can accept large values ​​of quantities of charges (in coulombs) at its terminals without saturating or deteriorating.In this respect, the ionic capacitive element 34, which has a high capacitance density, is a storage component particularly suitable for receiving the output current from the resistive element 30. Furthermore, as detailed below with reference to Figures 4a to 4f, the resistive element 30 and the capacitive element 34 can be made from the same materials, which allows them to be manufactured on the same substrate with shared steps, from the same layers of materials, potentially without even adjusting the thicknesses.

[0088] When an input voltage Vin is applied between the source and the drain of the ionic transistor(s) 32a, 32b, ..., 32n of the resistive element 30, the resistive element 30 enters a certain analog state which corresponds to a certain conductance value, which induces a current at the input of the capacitive element 34. The element capacitive element 34 then charges, and the voltage across the terminals of the capacitive element 34 depends on the input current (therefore on the current delivered by the resistive element 30).

[0089] As mentioned above, the capacitive element 34 must be able to support a wide range of charge quantities without saturating or degrading, due to the wide range of conductance values ​​of the resistive element 30. For example, a dielectric capacitive element would not be able to provide such a function (or it would be necessary to use a large number of dielectric capacitors, which is not desirable for reasons of cost and size). Therefore, an ionic capacitive element is particularly suitable.

[0090] In the example of [Fig.3], a comparator circuit 38 is connected in series to the output of the electrochemical storage element 36. For example, the comparator circuit 38 comprises an operational amplifier configured to trigger an operation when the voltage across the capacitive element 34 reaches a predetermined threshold. In the example of [Fig.3], the comparator circuit 38 is a CMOS type analog sensor involving three Mb transistors M2, M3, but this is not limiting, any comparator circuit can be used.

[0091] An assembly such as that shown in [Fig. 3] can be used for neuromorphic applications. Each ionic transistor 32a, 32b, ..., 32n corresponds to a respective synapse. The ionic transistors 32a, 32b, ..., 32n are in fact particularly suitable for acting as artificial synapses, since they have variable conductances depending on the voltage applied to them as input, and their states are non-volatile, which makes it possible to reproduce the synaptic characteristic called "spike timing dependent plasticity" (STDP), according to which the more the synapse is stimulated, the more learning improves. The capacitive element 34 simulates the action potential of a biological neuron, which ensures the separation of electrical charges across the cell membrane. The assembly of [Fig.3] thus makes it possible to reproduce the functioning of a neuron, by triggering an action (via the comparator circuit 38) when a certain activation threshold of the artificial neuron is reached (here, when the capacity of the capacitive element 34 reaches a certain value), in a manner similar to the action potential of the neuron of the human brain.

[0092] In other words, the operation of the electrochemical storage element 36 can therefore comprise the following steps, represented in [Fig.6]: • writing step: an electrical signal (voltage Vj, ..., Vn or current) is applied (step 610) between the source and the gate of each ionic transistor 32a, ..., 32n so that it enters a given conductance state; • reading step: an electrical signal (voltage Vin or current) is applied (step 620) between the source and the drain of each ionic transistor 32a, ..., 32n, which generates a current, called “read current”, which is transmitted to the capacitive element 34, allowing charge storage proportional to the read current.

[0093] It is noted that the electrochemical storage element 36 can be seen as a series-connected RC circuit. The associated time constant is therefore approximately equal to RxC, where R denotes the value of the resistance of the resistive element 30 (and therefore, for a single transistor 32a, the inverse of the conductance value of the transistor) and C the value of the capacitance of the capacitive element 34. It is thus possible, from the charging time of the capacitive element 34, to determine the value of the resistance (or the conductance) of the resistive element 30, and therefore the synaptic weight. The charging time can be determined for example by measuring the time between the generation of an input current of the capacitive element 34 and the triggering of the event by the comparator circuit 36.

[0094] As mentioned previously, the electrochemical storage element 36 has the advantage of being able to be produced on the same substrate, by deposition of successive layers, as now described with reference to Figures 4a to 4L

[0095] Figures 4a to 4f illustrate steps of a method for manufacturing an electrochemical storage element according to an embodiment of the invention. The flowchart of this manufacturing method is shown in [Fig.5].

[0096] In a first step 510 ([Fig.5]) of the method, an electrically insulating layer can be deposited on a substrate. This step is illustrated in [Fig.4a].

[0097] As shown in [Fig.4a], an electrically insulating layer 41 (for example made of a dielectric material) is formed on a substrate 40, for example by a full-plate deposition method. The substrate 40 may be a plate of semiconductor material. In certain embodiments, this plate integrates one or more components such as conventional transistors or microsystems. In particular, the integration of the storage device of the present invention may be carried out in the “Back End Of Line”, that is to say after the production of the CMOS level and in higher levels, in the same way as the contacts. It is noted that the ionic conductive layer 41 may constitute the substrate on its own (in certain embodiments therefore, there may be only one dielectric layer 41 which replaces the two layers 40 and 41 of Figures 4a to 4f).

[0098] The dielectric layer 41 may be composed of one or more materials providing electrical insulation, for example an oxide, a nitride, an oxynitride, or any material or combination of materials capable of acting as chemical and electrical passivation between the substrate 40 and the memory element.

[0099] In a non-limiting embodiment, the substrate 40 may be a silicon wafer and the layer 41 may be a silicon oxide layer.

[0100] Furthermore, during the first step 510 of the method shown in [Fig.5], the assembly composed of the substrate and the ionic conductive layer can be structured to form a recess intended to receive the ionic capacity. This structuring is shown in [Fig.4b].

[0101] As shown in [Fig.4b], the “substrate 40 / dielectric layer 41” assembly can be structured to create an opening 42 (or “cavity” or “groove”) perpendicular to the surface plane of the dielectric layer 41 and the substrate 40. This structuring is carried out through the dielectric layer 41 and the substrate 40, and stops in the substrate volume without passing through it. In the example of [Fig.4b], the opening 42 is a blind hole in the dielectric layer 41 which passes through a portion of the substrate 40, and the bottom of which is located near the lower surface of the substrate 40. It is noted that depending on the embodiments, the opening 42 can pass through the substrate to a variable depth, or even pass through only all or part of the dielectric layer 41 (and therefore not pass through the substrate 40).In some embodiments, the structuring may be performed by a photolithography technique (typically comprising deposition of a resin layer by spin coating on the “substrate 40 / dielectric layer 41” assembly, exposure through a mask and development of the exposed resin) followed by plasma etching.

[0102] As mentioned with reference to [Fig.2], the presence of the opening 42 is not obligatory, but it advantageously makes it possible to increase the effective surface area for accumulation of charges between the two electrodes 43b and 47b.

[0103] Referring again to [Fig.5], during a step 520, a first layer of an electrically conductive material can be deposited on the surface of the substrate, and structured in two parts having no contact points, one acting as a source electrode to the ionic transistor, and the other comprising both a drain electrode and the lower electrode of the ionic capacitor.

[0104] This step 520 is shown in [Fig.4c]: a layer 43 of electrically conductive material is formed on a portion of the surface of the dielectric layer 41 and at the opening 42 if applicable. The layer 43 of electrically conductive material comprises two portions 43a, 43b separated by a space 44, so that the two portions 43a, 43b of the layer of electrically conductive material 43 have no contact points with each other and are not electrically connected. In the example of [Fig.4c], the part 43b of the layer 43 of electrically conductive material covers a part of the unstructured surface of the “substrate 40 / dielectric layer 41” assembly (i.e. the part of the surface of the “substrate 40 / dielectric layer 41” assembly which is not at the level of the opening 42) as well as the walls and the bottom of the opening 42. As described below, portion 43a acts as a "source" of the ionic transistor of the storage component, and portion 43b acts as both a "drain" of the ionic transistor of the storage component and a lower electrode of the ionic capacitance of the storage component. It is noted that the source and drain electrodes may be interchanged (in particular, electrode 43a may represent the drain and electrode 43b may represent the source).

[0105] The layer 43 of electrically conductive material can typically be produced by deposition over the entire surface of the structured “substrate 40 / dielectric layer 41” assembly of [Fig.4b] (including the walls and the bottom of the opening 42), then by structuring in order to produce the space 44 and to give the desired shape and dimensions to the different parts of the layer 43. For example, the layer 43 can be deposited by vacuum cathode sputtering, and the structuring can be provided by photolithography followed by dry etching.

[0106] In certain embodiments, the deposition of the layer 43 of electrically conductive material may advantageously be a conformal deposition on the surface of the structured “substrate 40 / dielectric layer 41” assembly, i.e. its thickness is constant over the entire surface. This simplifies the manufacturing process of the electrochemical storage element, since a single layer can be deposited along the surface without the need to vary the thickness by adding additional layers.

[0107] In certain embodiments, the layer 43 may be a metallic layer of titanium having a thickness e (which corresponds to the dimension along the y axis in [Fig.4c], i.e. along the direction orthogonal to the surface of the substrate 40) of between 10 and 200 nm, for example equal to 100 nm.

[0108] Referring again to [Fig.5], in a step 530, a layer of an ion insertion material called a channel layer is deposited at the space between the source electrode and the drain electrode of the ionic transistor, so as to be in contact with both the source electrode and the drain electrode of the ionic transistor.

[0109] This step 530 is illustrated in [Fig.4d]: a layer 45 of an ion insertion material is formed and structured so as to cover the part of the layer 41 located at the space 34, as well as portions of the parts 43a and 43b of the layer 43, said portions including the ends of the parts 43a and 43b located at the space 44. As described below, this layer 45 constitutes the channel of the ion transistor of the storage component, and is therefore in contact with the source 43a, the drain 43b and the part of the layer 41 located at the space 44.

[0110] The channel 45 is composed of an ion insertion material for intercalating and de-intercalating ions under the application of an electric field and, thus, changing the electrical conductivity of the channel 45 depending on the intercalation rate. For example, the material composing the channel 45 may be a transition metal oxide, and more particularly a metal based on titanium dioxide nanoparticles (TiO2) having a size of approximately 10 nm, capable of intercalating lithium ions (Li+). The channel 45 may, for example, have a thickness of the order of a few nanometers to a few tens of nanometers.

[0111] Referring again to [Fig. 5], during a step 540, a layer of a material that is both ionically conductive and dielectric can be deposited on the surface of the element obtained at the end of step 530, then structured in two parts having no contact points. The first part covers the channel layer and is in contact with the source electrode and the drain electrode. The second part partially covers the lower electrode of the ionic capacitor.

[0112] This step 540 is illustrated in [Fig.4e]: a layer 46 of ionic and dielectric conductor is deposited and structured. The layer 46 is conductive for the same ions as the ion insertion material making up the channel 45. For example, if the channel 45 is in a material allowing the intercalation of Li+ ions, the material of the layer 46 is conductive for the Li+ ions.

[0113] The layer 46 of ionic and dielectric conductor comprises two portions 46a, 46b which have no contact points. One of the portions 46a covers the channel 45 so as to be in contact with the source 43a and the drain 43b of the ionic transistor of the electrochemical storage element. The other portion 46b covers a portion of the portion 43b of the layer 43 of electrically conductive material, said portion of the portion 43b of the layer 43 of electrically conductive material including the portion of the portion 43b of the layer 43 of electrically conductive material at the opening 42.

[0114] The layer 46 is composed of an ionic and dielectric conductive material, which allows the ions to circulate on the one hand between the source 43a and the drain 43b via the channel of the ionic transistor of the storage element, and on the other hand between the two electrodes 43b and 47b of the ionic capacity of the storage element, while ensuring electrical insulation between them. For example, this material may be a lithium phosphorus oxynitride (LiPON). The layer 46 may have a thickness of a few tens to a few hundreds of nm, for example 100 nm. In certain embodiments, this layer 46 is deposited by magnetron cathode sputtering. The structuring may be carried out by photolithography for example.

[0115] In certain embodiments, the deposition of the layer 46 of ionic and dielectric conductive material may advantageously be a conformal deposition on the surface of the element of [Fig.4d].

[0116] Finally, during a step 550 of [Fig.5], a layer of an electrically conductive material can be deposited on the surface of the element obtained at the end of step 540, then structured in two parts having no contact points. The first part partially covers the first part of the layer deposited in step 540 and is not in contact with either the source electrode or the drain electrode. This first part forms the gate electrode of the ionic transistor. The second part at least partially covers the second part of the layer deposited in step 540, and is not in contact with the lower electrode of the ionic capacitor. This second part forms the upper electrode of the ionic capacitor.

[0117] This step 550 is illustrated in [Fig.4f], in which a layer of an electrically conductive material is deposited on at least a portion of the layer 46. This layer comprises two portions 47a, 47b which have no contact points. The first portion 47a covers a portion of the surface of the portion 46a of the layer 46 and forms the gate of the ionic transistor of the storage element. The second portion 47b at least partially covers the portion 46b of the layer 46 and forms the upper electrode of the ionic capacitor of the storage element. In certain embodiments, the deposition of the layer 47 of electrically conductive material may advantageously be a conformal deposition on the surface of the element of [Fig.4e].

[0118] For example, the layer 47a, 47b may be a metallic layer of titanium having a thickness of 100 nm, deposited by vacuum sputtering. The structuring of the layer 47a, 47b may for example be carried out by photolithography and dry etching.

[0119] The above exemplary embodiments focus on a memory component operating on lithium Li+ ions, but it is entirely possible to use other charge-carrying ions, such as Na+, H+, K+, Cu+, etc.

[0120] The electrochemical storage element 400 of [Fig.4f] is shown in section on the (x, y) plane. In one or more embodiments, the channel width may be less than 200 nm, preferably less than 20 nm. The channel width corresponds to the dimension along the z axis (z being the third axis of an orthonormal (x, y, z) reference frame) of the channel 45 of the ionic transistor 420. The width of the ionic capacitance 420 (i.e. the dimension of the ionic capacitance 420 along the z axis) may be less than 2 pm, preferably less than 1 pm. The depth of the ionic capacitance 420 (i.e. its dimension along the y axis) may be greater than 2 pm, preferably greater than 5 pm.

[0121] The electrochemical storage element 400 obtained at the end of the different steps shown in [Fig.4a] to 4f comprises an ionic transistor 410 (of similar structure to the ionic transistor 1 shown in [Fig.1a]) and an ionic capacitor 410 (of similar structure to the ionic capacitor 2 shown in [Fig.2]) connected in series. Assuming that the ionic transistor 410 is in a given conductance state, when a voltage is applied between the source 43a and the drain 43b of the transistor ionic 410, this generates a current which is transmitted to the ionic capacitor 420 via the layer 43b which acts both as drain of the ionic transistor 410 and as lower electrode of the ionic capacitor 420, thus generating a storage of charges at the level of the ionic capacitor 420.

[0122] The ionic transistor 410 and the ionic capacitor 420 are produced monolithically on the same level of the substrate 40. As appears above, such an element can be manufactured by pooling certain manufacturing steps of the transistor and the ionic capacitor (deposition of the same layer for the two components and structuring).

[0123] The element 400 of [Fig.4f] is an example of an electrochemical storage element 36 as shown with reference to [Fig.3], in which the resistive element 30 comprises a single ion transistor 32a (the component 410) and in which the capacitive element 34 comprises a single ion capacitor 420. Of course, the storage element 400 of [Fig.4f] may be modified to comprise several ion transistors 410 in parallel. For example, in a 3D structure, a plurality of ion transistors such as the ion transistor 410 may be made in parallel and connected in series to an ion capacitor 420.

[0124] Of course, the present invention is not limited to the embodiments described above as examples. It extends to other variants. For example, other components may be intercalated between the ionic transistor and the ionic capacitance. The ionic transistor and / or the ionic capacitance may also comprise additional layers. For example, an intercalated layer in an ion insertion material dissociated from that of the ionic transistor may be implemented in the architecture of the ionic capacitance, so as to have a hybrid capacitance. For example, this intercalated layer may be inserted at the level of the ionic capacitance, between layer 43b and layer 46b of [Fig.4f], i.e. between the lower electrode and the ionic conductive layer of the ionic capacitance.Such an implementation allows to further increase the value of the capacitance density (in practice, this can be doubled in comparison with an isoarchitecture without an interlayer), as described for example in the article by V. Sallaz et al. “Hybrid All-Solid-State Thin-Film Micro-supercapacitor Based on a Pseudocapacitive Amorphous TiO2 Electrode”, ACS Appl. Energy Mater. 2023, 6, 1, 201-210. Such an interlayer can be obtained from the fabrication method of [Fig.5]: at step 530, the layer of ion insertion material can be deposited over the entire surface, and structured in two disjoint parts: one corresponding to the channel layer of the ion transistor, the other corresponding to the interlayer of the ion capacitor.

Claims

Claims

1. An electrochemical charge storage device (400) comprising an ionic transistor (410) and an ionic capacitor (420), the ionic transistor (410) comprising: - a layer (45) forming an ion reservoir, called a reservoir layer; - a source electrode (43a) in contact with a portion of the reservoir layer (45); - a drain electrode (43b) in contact with another portion of the reservoir layer (45), the drain electrode (43b) and the source electrode (43a) being physically separated from each other, the source electrode (43a) and the drain electrode (43b) each being made of an electrically conductive material;and - a gate electrode (47a) in an electrically conductive material, the gate electrode being separated from the reservoir layer by an ionic conductive layer (46a) in an ionic and dielectric conductive material, the ionic conductive layer (46a) being in contact with the source electrode (43a) and with the drain electrode (43b); the ionic capacity (420) comprising two electrodes (43b, 47b), each of the two electrodes (43b, 47b) being in an electrically conductive material, the ionic capacity (420) comprising an ionic conductive layer (46b) separating the two electrodes (43b, 47b) of the ionic capacity (420), the ionic conductive layer of the ionic capacity (420) being in an ionic and dielectric conductive material; wherein the ionic transistor (410) and the ionic capacitor (420) are electrically connected in series.;

2. Device (400) according to claim 1, wherein the ionic conductive layer (46a) of the ionic transistor (410) and the ionic conductive layer (46b) of the ionic capacitor (420) are made of the same ionic conductive and dielectric material.

3. The device (400) of claim 2, wherein the ionically conductive and dielectric material is a phosphorus oxynitride. lithium LiPON, lithium silicon phosphorus oxynitride LiSiPON, lithium germanium phosphorus sulfide LGPS, lithium lanthanum zirconium oxide LiLaZrxOy or lithium lanthanum tantalum oxide LiLaTaOx.

4. Device (400) according to one of the preceding claims, in which the reservoir layer (45) and the ionic conductive layer (46a) of the ionic transistor are made of the same ionic conductive and dielectric material.

5. Device (400) according to one of the preceding claims, in which the ionic conductive layer (46a) of the ionic transistor and the ionic conductive layer (46b) of the ionic capacitor have the same thickness.

6. Device (400) according to one of the preceding claims, in which the ionic transistor (410) and the ionic capacitor (420) are located on the same substrate (40, 41), in a monolithic manner.

7. Device (400) according to claim 6, wherein the ionic transistor (410) and the ionic capacitor (420) are located on the same level of the substrate (40, 41).

8. A device (400) according to claim 6 or 7, wherein the substrate (40, 41) comprises a recess (42), wherein at least a portion of the ionic capacitance (420) is housed in the recess (42).

9. Device (400) according to one of the preceding claims, in which the source electrode (43a) of the ionic transistor, the drain electrode (43b) of the ionic transistor and one of the electrodes, called the lower electrode (43b), of the ionic capacitor are made of the same electrically conductive material and have the same thickness.

10. The device (400) of claim 9, wherein the lower electrode (43b) of the ionic capacitor and one of the drain electrode and the source electrode of the ionic transistor are common.

11. Circuit comprising an electrochemical charge storage device (400) according to one of claims 1 to 10, the circuit further comprising a comparator block (38) connected in series to an output of the ionic capacitor (34), the comparator block (38) being configured to trigger a signal when a voltage across the ionic capacitor (34) reaches a reference voltage value.

12. A circuit according to claim 11, wherein the comparator block (38) comprises an operational amplifier receiving, on an input, the

13.

14. voltage across the ionic capacitance and, on another input, the reference voltage value, the signal being triggered when the voltage across the ionic capacitance reaches the reference voltage value, the signal corresponding to a response from an artificial synapse. A circuit according to claim 11 or 12, further comprising means for determining a time taken by the ionic capacitor (38) for the voltage across its terminals to reach the reference voltage. Method for manufacturing an electrochemical charge storage device according to one of claims 1 to 10, the method successively comprising: - depositing (520), on a substrate, a first layer of electrically conductive material, and structuring said first layer so as to obtain a first part of the first layer and a second part of the first layer having no contact points, the first part of the first layer corresponding to one electrode among a source electrode and a gate electrode of the ionic transistor, the second part of the first layer corresponding to the other electrode among the source electrode and the drain electrode of the ionic transistor and to a first electrode among the two electrodes of the ionic capacitor; - deposition (530) of the reservoir layer, the reservoir layer being in contact with the source electrode and the drain electrode of the ionic transistor; - depositing (540) an ionic conductive layer in an ionic conductive and dielectric material, and structuring the ionic conductive layer so as to obtain a first part of the ionic conductive layer and a second part of the ionic conductive layer having no contact point, the first part covering the reservoir layer and being in contact with the source electrode and the drain electrode of the ionic transistor, the second part at least partially covering the first electrode of the ionic capacitor; - deposition (550) of a second layer of electrically conductive material, and structuring of said second layer so as to obtain a first part of the second layer and a second part of the second layer having no contact points, the first part of the second layer partially covering the first part of the ionic conductive layer and having no contact points with the first part of the first layer and the second part of the first layer, the second part of the second layer at least partially covering the second part of the ionic conductive layer and having no contact points with the second part of the first layer, the first part of the second layer corresponding to the gate electrode of the ionic transistor, the second part of the second layer corresponding to a second electrode among the two electrodes of the ionic capacitor, the second electrode being distinct from the first electrode.

15. Manufacturing method according to the preceding claim, wherein the deposition of at least one layer among the first layer of electrically conductive material, the ionically conductive layer and the second layer of electrically conductive material is a conformal deposition.

16. A method of storing charges using an electrochemical storage device according to one of claims 1 to 10, comprising: - applying (610) a voltage to the gate electrode of the ionic transistor, so as to set a predefined conductance value for the ionic transistor; - generating (620) a current flowing between the ionic transistor and the ionic capacitor, an intensity value of the output current of the ionic transistor corresponding to an input value of the input current of the ionic capacitor.

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