Electrochemical charge storage device

Abstract

An electrochemical storage device comprising an ionic transistor and an ionic capacitor, the ionic transistor comprising a gate electrode, the ionic capacitor comprising two electrodes, the device further comprising a connection element adapted to connect the gate electrode of the ionic transistor to a first electrode among the two electrodes of the ionic capacitor. Figure to be published with the abstract: Figure 4f

Description

Title of the invention: Electrochemical charge storage device TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of storage components, in particular electrochemical charge storage components.

[0002] In particular, the invention relates to an electrochemical charge storage device that can be used in neuromorphic applications. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] The use of artificial intelligence algorithms for a wide range of applications has exploded in recent years. These algorithms often require so-called neuromorphic architectures, which aim to mimic the synaptic processing that occurs in the human brain. Thus, neuromorphic architectures (or circuits) are electronic circuits designed to emulate the behavior of biological neurons and neural networks.

[0004] Neuromorphic architectures, such as IBM™ Resistive Processing Units (RPUs), are based in part on resistive memory devices that use a cross-element array to achieve good performance in terms of memory density, energy efficiency and speed, by reducing data movement during computation and taking advantage of multi-level analog states. Such resistive memory devices can accelerate the training of deep neural networks using little energy. It is indeed possible to reproduce the operation of a biological neuron by using an array of resistive memories associated with respective synaptic weights.

[0005] Existing devices based on conductive filaments or phase-change materials suffer from excessive write noise. In these devices, it is difficult to reduce the noise and lower the switching voltage while ensuring long-term data retention, which represents a significant limitation in terms of accuracy, power efficiency, and scalability of these devices. To implement efficient neuromorphic systems, it is therefore preferable to use resistive memory elements that switch using a different mechanism than that used in filament-forming or phase-change devices.

[0006] This is why, recently, a new category of components has been studied for these neuromorphic applications: the ionic transistor, which can be used as Synaptic transistor. The operation of the ionic transistor is based on the movement of ions between the source and the drain, which allows the conductance value of the transistor to be modified. Such a transistor is notably described in the article by Nguyen et al. "An Ultralow Power LixTiO2-Based Synaptic Transistor for Scalable Neuromorphic Computing", published in Advanced Electronic Materials in 2022.

[0007] The ionic transistor can advantageously be in a plurality of states (several tens), each state corresponding to a respective conductance value. As for filamentary or phase-change resistive memories, these states are non-volatile: when a gate voltage (bias) is no longer applied to the ionic transistor, the latter retains its conductance value. However, for certain neuromorphic applications, it is desirable for the conductance value of the transistor to "relax" over time, i.e. to decrease over time, when no gate voltage is applied. Furthermore, this relaxation must be controllable.

[0008] The invention improves the situation. Summary of the invention

[0009] The invention provides a solution to the problem mentioned above, by proposing an electrochemical charge storage device (also called hereinafter "electrochemical storage device") comprising an ionic transistor and an ionic capacitor, in which the gate of the ionic transistor is connected, directly or indirectly, to one of the electrodes of the ionic capacitor. Due to the presence of the ionic capacitor, a relaxation of the conductance level of the transistor is in fact observed, when no voltage is applied to the gate. The value of the conductance of the transistor thus decreases, with a time constant which can be adjusted, in particular by applying a voltage to the electrodes of the ionic capacitor and by modulating the value of this voltage.This results in a device with a multitude of conductance levels, which requires a very small amount of energy to move from one conductance level to another, and whose conductance relaxes over time. Such a device effectively simulates the behavior of a biological synapse, and is particularly interesting in the design of complex and powerful neuromorphic systems.

[0010] Furthermore, it is possible to manufacture such a device on the same substrate, by pooling a large part of the manufacturing steps of the ionic transistor and the ionic capacitor. This makes it possible to obtain a compact device whose manufacture is relatively simple and inexpensive.

[0011] One aspect of the invention thus relates to an electrochemical charge storage device comprising an ionic transistor and an ionic capacitor,

[0012] the ionic transistor comprising: • a layer forming a reservoir of ions, called a reservoir layer; • a source electrode in contact with a part of the reservoir layer; • a drain electrode in contact with another portion of the reservoir layer, the drain electrode and the source electrode being physically separated from each other, the source electrode and the drain electrode each being made of an electrically conductive material; and • a gate electrode in an electrically conductive material, the gate electrode being separated from the reservoir layer by an ionically conductive layer in an ionically conductive and dielectric material, the ionically conductive layer being in contact with the source electrode and with the drain electrode;

[0013] the ionic capacity comprising two electrodes, each of the two electrodes being in an electrically conductive material, the ionic capacity comprising an ionic conductive layer separating the two electrodes of the ionic capacity, the ionic conductive layer of the ionic capacity being in an ionic conductive and dielectric material;

[0014] the device further comprising a connection element capable of connecting the gate electrode of the ionic transistor to a first electrode among the two electrodes of the ionic capacitor.

[0015] In other words, the gate electrode of the ionic transistor is capable of being connected to one of the two electrodes of the ionic capacitor.

[0016] The reservoir layer is a layer in a material comprising ions of a certain type (for example Li+). The reservoir layer may be in a material called “ion insertion material”, or “insertion compound” or “ion intercalation material”, i.e. a material which allows the penetration of a certain type of ions, without altering its properties. In the following, the reservoir layer is also called “channel layer” or “ion insertion material layer”. It is noted that, above, an “ionic conductive material” designates a material which conducts the same ions as those of the reservoir layer.

[0017] The connection element may be any electronic component or any element capable of connecting, at least at a given moment, the gate electrode of the ionic transistor to the first electrode of the ionic capacitor. For example, the connection element may be an element made of an electrically conductive material, such as a conductive via or a layer made of a conductive material (it is noted that when nothing is specified, “conductive” means “electrically conductive”), which makes it possible to connect the ionic transistor and the ionic capacitor in a simple manner. The connection element may, in other embodiments, be a component which makes it possible to control the instants during which the gate of the ionic transistor is connected to the first electrode the ionic capacitance, like a switch or multiplexer.

[0018] The “first electrode” here designates the electrode of the ionic capacitor which can be connected, via the connection element, to the gate electrode. This terminology is used here for the sake of simplification of reading. It is understood that the gate electrode of the ionic transistor can be connected to any of the electrodes of the ionic capacitor.

[0019] It is noted that the terms "gate", "source", "drain" may be used instead of the terms "gate electrode", "source electrode", "drain electrode", respectively, for the sake of simplification. Also, the term "terminal" may be used instead of "electrode" for the ionic capacitance.

[0020] In the absence of an ionic capacitance connected to the gate of the ionic transistor, the latter remains in a non-volatile state when no voltage is applied to its gate. This means that when the ionic transistor is in a state corresponding to a certain conductance value, this value remains substantially constant when a gate current is no longer applied. By connecting the gate of the ionic transistor to one of the electrodes of the ionic capacitance, a partial "discharge" of the ionic transistor occurs in the ionic capacitance, which results in a decrease in the conductance value of the ionic transistor over time, called here "relaxation of the conductance state of the ionic transistor". This property is of particular interest in the context of neuromorphic applications, because it more faithfully reproduces the behavior of biological synapses.

[0021] Furthermore, the production of such a device can be advantageously simplified because the ionic transistor and the ionic capacitor use similar layers of materials. Thus, certain manufacturing steps can be shared, as detailed below.

[0022] When the ionic capacitor has a "stacked" structure on the substrate (in the sense that the electrodes extend along a direction that corresponds to the main direction of the substrate), the terminology "top electrode / bottom electrode" can be used. The bottom electrode corresponds to the electrode closest to the substrate, while the top electrode corresponds to the electrode furthest from the substrate.

[0023] In one or more embodiments, one of the source electrode and the drain electrode of the ionic transistor is connected to a second electrode of the two electrodes of the ionic capacitor, the second electrode being distinct from the first electrode.

[0024] Here, the “second electrode” designates the other electrode of the ionic capacity (i.e., the one which is not intended to be connected, via the connection element, to the electrode gate of the ionic transistor). For example, the second electrode may be the top electrode and the first electrode may be the bottom electrode of the ionic capacitor.

[0025] In one or more embodiments, the connection element is an element capable of connecting, directly or indirectly, the gate electrode of the ionic transistor to the first electrode of the ionic capacitor.

[0026] By "directly" it is understood that there is no intermediate component other than the connection element between the ionic transistor and the ionic capacitor. Conversely, "indirectly" indicates the presence of an intermediate component between the ionic transistor and the ionic capacitor, in addition to the connection element.

[0027] In one or more embodiments, the connecting element may be one of a layer of electrically conductive material, a conductive via, a switch, or a multiplexer.

[0028] When the connection element is a layer of electrically conductive material or a conductive via, the same voltage can be applied to the gate of the ionic transistor and to the terminals of the ionic capacitor, which makes it possible both to place the ionic transistor in a given conductance state and to modify the capacitance value of the ionic capacitor. These two actions are therefore carried out in a mutualized manner.

[0029] When the connection element is a switch or a multiplexer, it is possible to place the ionic transistor in a given conductance state on the one hand and / or to charge the ionic capacitance on the other hand. These two actions are therefore carried out separately (or offset), which offers more freedom in controlling the relaxation of the ionic transistor. In particular, this makes it possible to introduce a controlled delay on the relaxation (i.e. to control the moment at which the conductance value of the ionic transistor is desired to begin to decrease) and to control the relaxation speed of the conductance state of the ionic transistor. Schematically, the relaxation speed depends partly on the capacitance value of the ionic capacitance: the higher it is, the slower the relaxation. The relaxation speed also depends partly on the conductance value of the ionic transistor: the higher it is, the faster the relaxation.Furthermore, it is possible to interrupt or suspend the relaxation by interrupting or suspending the connection between the gate of the ionic transistor and the first electrode of the ionic capacitor.

[0030] In one or more embodiments, the device further comprises the ionic conductive layer of the ionic transistor and the ionic conductive layer of the ionic capacitor are common.

[0031] By “common”, it is understood that the device comprises a “continuous” ionic conductive layer (i.e. without discontinuities, for which there is no interruption) which plays both the role of ionic conductive layer of the ionic transistor and of ionic conductive layer of ionic capacity.

[0032] In other terms, according to these embodiments, the same ionic conductive layer connects the source and the drain of the ionic transistor and separates the two electrodes of the ionic capacitor. This makes it possible to pool the deposition of such a layer during the manufacture of a device according to the invention.

[0033] For example, the ionic conductive and dielectric material may be a lithium phosphorus oxynitride LiPON, a lithium silicon phosphorus oxynitride LiSiPON, a lithium germanium phosphorus sulfide LGPS, a lithium lanthanum zirconium oxide LiLaZrxOy or a lithium lanthanum tantalum oxide LiLaTaOx.

[0034] LiPON can be used for an ionic transistor and an ionic capacitor operating on the basis of lithium Li+ ions (i.e., the operation of which is based on the circulation of Li+ ions). In these embodiments, the channel of the ionic transistor can be made of a Li+ ion insertion material, for example a transition metal oxide capable of intercalating Li+ ions. Of course, the invention applies to other charge-carrying ions, for example Na+, H+, K+, Cu+ ions, etc.

[0035] The electrically conductive material in which the electrodes of the ionic capacitor and / or the source, drain or gate electrodes of the ionic transistor are made may be, for example, one of: titanium (Ti), tungsten (W), molybdenum (Mo), nickel (Ni) or platinum (Pt).

[0036] The reservoir layer can be made, for example, from one of the following materials: titanium dioxide (TiO2), lithium cobalt dioxide (LiCoO2), lithium niobate (LiNbOx), tungsten trioxide (WO3), vanadium oxide (VOX), nickel oxide (NiOx), manganese oxide (MnOx) - and generally transition metal oxides, molybdenum disulfide (MoS2), graphene.

[0037] In some embodiments, the gate electrode of the ionic transistor and said first electrode of the ionic capacitor may be common.

[0038] By "common", it is understood that the device comprises a "continuous" layer (i.e. without discontinuities, for which there is no interruption) of electrically conductive material which acts both as the gate electrode of the ionic transistor and as the first electrode of the ionic capacitor. For example, one of the ends of the continuous layer corresponds to the gate electrode of the transistor, and the other end to the lower electrode of the capacitor.

[0039] In these embodiments, it is therefore the same layer of electrically conductive material which acts as gate electrode, connection element and first electrode of the ionic capacity. This allows simplified manufacture of the device, but also a more compact device.

[0040] In certain alternative or complementary embodiments of the preceding ones, the source electrode of the ionic transistor, the drain electrode of the ionic transistor and the second electrode of the ionic capacitor may be made of the same electrically conductive material and have the same thickness.

[0041] The electrically conductive material may be the same as that of the gate electrode of the ionic transistor and the first electrode of the ionic capacitor, but this is not mandatory.

[0042] In particular, if the electrode, among the drain electrode and the source electrode, of the ionic transistor connected to the second electrode of the ionic capacitor is called the connection electrode of the ionic transistor, then the connection electrode of the ionic transistor and the second electrode of the ionic capacitor may be common.

[0043] In other words, the device comprises a “continuous” layer (i.e. without discontinuities) which acts both as a connection electrode of the ionic transistor and as a second electrode of the ionic capacitor. For example, one end of the continuous layer corresponds to the connection electrode of the transistor, and the other end to the second electrode of the capacitor.

[0044] In other words, the same layer of electrically conductive material can serve both as a connection electrode (source or drain) of the ionic transistor and as a second electrode of the ionic capacitor.

[0045] In embodiments, the ionic transistor and the ionic capacitor may be formed on a single substrate, monolithically.

[0046] By "formed on the same substrate", it is understood that the ionic transistor and the ionic capacitor are integrated on the same substrate plate. This allows cointegration of the two components in parallel, with shared manufacturing steps. In particular, at least some layers are derived from the same deposited and structured layer of material. It should be noted that by substrate, we mean the raw substrate (i.e. a Si wafer for example) but also a raw substrate on which one or more semiconductor or insulating layers would be deposited. By "monolithic" is meant "in one piece." In other words, the ionic transistor and the ionic capacitor are integrated on the same substrate and form a unit.

[0047] For example, the ionic transistor and the ionic capacitor may be mounted on the same level of the substrate.

[0048] In particular, the substrate may comprise, on a first level, CMOS type components, and, on a second level, the ionic transistor and the ionic capacitance. For example, the manufacturing of the ionic transistor and the ionic capacitance may be done in “Back End Of Line” on a substrate integrating CMOS, subject to compliance with maximum temperatures of the order of 450°C.

[0049] In embodiments, the substrate may include a recess, wherein at least a portion of the ionic capacitance is accommodated in the recess.

[0050] This makes it possible to increase the exchange surface between the lower and upper electrodes of the ionic capacity, and therefore the value of the capacitance of the ionic capacity.

[0051] In these embodiments, the second electrode (lower electrode) of the ionic capacitor extends along an inner surface of the recess, the ionic conductive layer of the ionic capacitor at least partially covers the second electrode of the ionic capacitor, and the first electrode (upper electrode) of the ionic capacitor at least partially covers the ionic conductive layer of the ionic capacitor.

[0052] In embodiments, the ionic capacitor further comprises an interlayer in an ion reservoir material, the interlayer separating the ionic conductive layer of the ionic capacitor and the electrode, of the two electrodes of the ionic capacitor, other than the first electrode.

[0053] Such an implementation makes it possible to further increase the value of the capacitance density (in practice, this can be doubled in comparison with an isoarchitecture without an interlayer).

[0054] Another aspect of the invention relates to a neuromorphic processing circuit of the “differential pair integrator” type comprising an electrochemical charge storage device as defined above.

[0055] A circuit of the “differential pair integrator” type, or “differential pair in-tegrator” in English (also called “diff-pair integrator”) is an analog artificial synapse described for example in the article by G. Indiveri et al. “Neuromorphic Silicon neuron circuits”, Frontiers in Neuroscience, published on May 31, 2011, or in the article by M. Payvand et al. “Self-organization of an inhomogeneous memristive hardware for sequence learning”, Nat Commun 13, 5793 (2022). It is possible to replace the ionic transistors of these circuits with charge storage devices according to the invention, to induce a relaxation of the conductance state of the ionic transistors and thus get closer to the behavior of biological synapses. In addition, the capacitors connected to the transistors can ensure the storage of charges for the other blocks of the circuit.

[0056] Another aspect of the invention relates to a method of manufacturing an electrochemical charge storage device as defined above, the method successively comprising: • depositing, on a substrate, a first layer of electrically conductive material, and structuring said first layer so as to obtain a first part of the first layer and a second part of the first layer having no contact points, the first part of the first layer corresponding to one electrode among a source electrode and a gate electrode of the ionic transistor, the second part of the first layer corresponding to the other electrode among the source electrode and the drain electrode of the ionic transistor and to an electrode of the ionic capacitor; • deposition of the reservoir layer, the reservoir layer being in contact with the first part of the first layer and with the second part of the first layer; • deposition of an ionic conductive layer in an ionic conductive and dielectric material, the ionic conductive layer at least partially covering the first part of the first layer, the entire reservoir layer and at least partially the second part of the first layer; and • deposition of a second layer of electrically conductive material at least partially covering the ionic conductive layer, the second layer of electrically conductive material having no physical contact point with the first layer of electrically conductive material, the second layer of electrically conductive material forming a gate electrode of the ionic transistor and another electrode of the ionic capacitor.

[0057] It is thus possible to manufacture an electrochemical storage device monolithically on the same substrate, by pooling certain steps to manufacture both the elements making up the ionic transistor and the elements making up the ionic capacitor. This is made possible by the fact that the ionic transistor and the ionic capacitor are composed of similar material layers. This results in simplicity of manufacture, and a compact electrochemical storage device suitable for neuromorphic applications.

[0058] In particular, the deposition of at least one layer among the first layer of electrically conductive material, the ionically conductive layer and the second layer of electrically conductive material may be a conformal deposition.

[0059] By “conformal deposition” is meant a deposit conforming to the surface on which the layer of material is formed and having the same thickness over its entire deposition surface.

[0060] Prior to the above steps, the method may comprise: structuring the substrate to form a recess in the substrate, in which the depositions of the first layer of electrically conductive material, the ionically conductive layer and the second layer of electrically conductive material are made successively on the substrate thus structured.

[0061] Thus, a single layer can be deposited and then structured to form several elements of the electrochemical energy storage device according to the invention.

[0062] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0063] Other characteristics and advantages of the invention will appear on reading the description, which can be read with reference to the figures. These figures are presented for information purposes only and in no way limit the invention.

[0064] [Fig. 1a], [Fig. 1b] Figures 1a and 1b represent a state-of-the-art ionic transistor.

[0065] [Fig.2a], [Fig.2b] Figures 2a and 2b represent an ionic capacity of the state of the technique.

[0066] [Fig.3a] [Fig.3a] represents an example of an electronic assembly allowing a relaxation of the conductance value of an ionic transistor according to an embodiment of the invention.

[0067] [Fig.3b] [Fig.3b] represents an equivalent modeling of the electronic assembly of [Fig.3a].

[0068] [Fig.4a], [Fig.4b], [Fig.4c], [Fig.4d], [Fig.4e], [Fig.4f] Figures 4a to 4f illustrate steps of a method of manufacturing a storage element according to an embodiment of the invention.

[0069] [Fig.5] [Fig.5] represents an example of a flowchart of a method of manufacturing a storage element according to an embodiment of the invention.

[0070] [Fig.6] [Fig.6] represents an example of a flowchart of a method of using a storage element according to an embodiment of the invention.

[0071] [Fig.7] [Fig.7] represents several curves illustrating the relaxation of the normalized conductance of the ionic transistor as a function of time, for several values ​​of the ionic capacitance.

[0072] [Fig.8] [Fig.8] represents an example of a storage element according to another embodiment of the invention. DETAILED DESCRIPTION

[0073] [Fig. 1a] represents an ionic transistor 1 according to the state of the art.

[0074] The ionic transistor 1 is an analog transistor mounted on a substrate 10, in particular made of silicon Si, covered with a layer 11 of dielectric material (for example, silicon dioxide SiO2), which comprises a channel 14 of variable electrical conductivity, a source electrode 13 (also simply called “source”) and a drain electrode 12 (also simply called “drain”). It is noted that in certain embodiments the assembly formed by the substrate 10 and the layer 11 of dielectric can be replaced by a single layer of dielectric material. The drain 12 and source 13 are separated from each other by channel 14, so that drain 12 and source 13 have no physical contact points. For example, drain 12 and source 13 may be deposited on two portions of a surface of layer 11 of dielectric material, the two portions of the surface of layer 11 of dielectric material being spaced apart from each other by, for example, a few tens of nanometers. Drain 12 and source 13 are in an electrically conductive material. Channel 14 is in an ion insertion material. It is noted that the source and drain electrodes may be interchanged (in particular, in [Fig.1a], electrode 12 may represent the source and electrode 13 may represent the drain).

[0075] The ionic transistor 1 further comprises a layer 15 of a material that is both ionically conductive and dielectric, separating the channel 14 from an electrode 16 called the gate, positioned on the upper surface of the layer 15 of material that is both ionically conductive and dielectric. The gate electrode 16 (also simply called the "gate") is made of an electrically conductive material. The layer 15 therefore allows the transport of ions between the channel 14 and the gate electrode 16, but blocks the transport of electrons. It is understood that the layer 15 is conductive for the same ions as the ion insertion material making up the channel 14. For example, if the channel 14 is made of a material allowing the intercalation of Li+ ions, the material of the layer 15 is conductive for the Li+ ions.

[0076] The ionic transistor 1 can be manufactured by successively depositing (and structuring) the layers which compose it (deposition of the layers forming the drain 12 and the source 13, then deposition of the layer 14 forming the channel, then deposition of the layer 15 of ionic and dielectric conductive material, and finally deposition of the layer 16 forming the gate electrode 16), for example by a lithography process (such as photolithography or electronic lithography).

[0077] The channel 14 is in an ion insertion material, the electrical conductivity of which depends on its oxidation level. For example, the channel may be in an inert material such as lithiated components such as LixCoO2, LixNiO2, LixMn2O4, LixV2O5, Lix WO3, LixM03, LixTi5Oi2, where x is the fraction of lithium in the component.

[0078] In a non-limiting manner, channel 14 may comprise LiCoO2, layer 15 of ionic and dielectric conductive material may comprise lithium phosphorus oxynitride (LiPON), which is a material that can conduct Li+ ions from channel 14.

[0079] It is noted that other layers may be added to the ionic transistor 1, for example an interlayer of an ion insertion material located between the channel layer 14 and the layer 15 of ionic and dielectric conductive material. Furthermore, it is noted that the structure of the ionic transistor may differ from the example shown in [Fig.la]. For example, in some embodiments, the channel layer 14 can completely cover the drain 12 and the source 13, as in application US 10,429,343 for example.

[0080] The oxidation level of channel 14 can be modified by applying a voltage VG applied between gate 16 and source 13. When a voltage VG is applied between gate 16 and source 13, this induces a migration of the ions between gate 16 and channel 14, which has the effect of modifying the electrical conductance of channel 14 between source 13 and drain 12, and therefore the logic state of the transistor, a logic state being associated with a respective electrical conductance value of the transistor. The different (normalized) conductance values ​​of the ionic transistor as a function of the voltage applied between gate 16 and source 13 are shown in [Fig.lb]. By conductance of the ionic transistor is meant the electrical conductance of channel 14.

[0081] To obtain the curve of [Fig.lb], successive voltage pulses were applied between the gate 16 and the source 13. In the example of [Fig.lb], each voltage pulse has an amplitude of ±100 mV and a width of 0.1 second. These values ​​are provided as an example and in a non-limiting manner. The curve of [Fig.lb] represents the variation of the conductance of the transistor (on the ordinate) as a function of the voltage pulse number n (on the abscissa). To obtain the curve of [Fig.lb], 50 successive pulses of negative amplitude were applied (increasing part of the curve, called the potentiation phase), then 50 successive pulses of positive amplitude were applied (decreasing part of the curve, called the depression phase).

[0082] It appears from [Fig. 1b] that the conductance of channel 14 can be reversibly modified according to the voltage VG applied between gate 16 and source 13. Furthermore, the variation in the conductance value is linear during the application of a constant non-zero voltage value. It increases linearly when a negative amplitude voltage pulse is applied, and it decreases linearly when a positive amplitude voltage pulse is applied. Furthermore, the application of a positive amplitude voltage pulse “cancels out” the effects of applying a voltage pulse of the same duration and opposite amplitude (and vice versa), in the sense that it returns the conductance value to the initial value.

[0083] It is thus possible to modify the conductance of the ionic transistor 1 of [Fig. 1a] by adjusting the value of the voltage VG applied between the gate 16 and the source 13. Once the ionic transistor has a certain conductance value, a voltage VSD is applied between the source 13 and the drain 12 and a current flows, the value of the current intensity being fixed by the conductance value of the transistor.

[0084] The different conductance values ​​associated with the different current pulse numbers correspond to logic states (or "conductance states"). Each logic state is non-volatile, and the transition from one logic state to the next state requires a very low energy (for example, an amount of energy per active surface of the order of fj / pm2). Furthermore, as appears in [Fig.lb], a large number (several tens) of logic states can be reached in potentiation and depression in a controlled manner (by means of the applied voltage VG), with, as mentioned above, a response linearity which is a function of the conductance range considered.

[0085] It is noted that the transition speed between two successive logic states of the ionic transistor depends partly on the thickness of the channel layer 14 (the thickness corresponding to the dimension along the y axis in [Fig.1a]): the thinner the channel layer 14, the higher the transition speed between two successive logic states. The thickness of the channel layer 14 can thus be fixed, for example, between 1 and 500 nm.

[0086] The transition speed between two successive logic states also depends in part on the thickness of the layer 15 of ionic and dielectric conductive material: the thinner the layer 15 of ionic and dielectric conductive material, the higher the transition speed between two successive logic states. The thickness of the layer 15 of ionic and dielectric conductive material can thus be fixed, for example, between 1 and 200 nm.

[0087] As detailed above, the ionic transistor is an analog transistor allowing several dozen states (which is currently difficult to obtain from dielectric transistors and with resistive memories), which makes it a component of choice for reproducing the functioning of synapses, which, in the human brain, allow neurons to be connected to each other. In the human brain, neurons start to activate when the synapses have totaled a certain number of electrical impulses, which is made possible by a transistor with several dozen states.

[0088] Furthermore, the ionic transistor exploits the same electrochemical reaction as a synapse, which gives it excellent energy efficiency, of the same order of magnitude as a human brain synapse.

[0089] These properties make the ionic transistor a particularly suitable component for neuromorphic applications. However, a limitation remains for these transistors: the time constant, which generally defines the relaxation of a logic state of the transistor over time and without bias (i.e. when no gate voltage is applied). Since each logic state is non-volatile, the time constant is not adaptable or controllable, which reduces the field of applications for these components.

[0090] [Fig.2a] represents an ionic capacity 2 (also called supercapacitor) according to the state of the art.

[0091] An ionic capacitor is an electrochemical energy storage component, of the supercapacitor type, composed of materials exclusively in solid form. An ionic capacitor can be charged and discharged by connecting it to an electrical circuit. Energy storage is achieved through changes in the materials that make up the ionic capacitor during charging and discharging. Indeed, when a voltage is applied to the terminals of the ionic capacitor, ion depletions / concentrations occur at the two ionic conductor / electrode interfaces.

[0092] As shown in [Fig.2a], an ionic capacitor 2 typically comprises a substrate 20 covered with a first layer 21 of dielectric. The substrate 20 is a raw substrate (i.e. untreated), or it may have already undergone treatment so that other electronic components or layers are already present on it. In the example of [Fig.2a], the substrate 20 and the layer 21 of dielectric of [Fig.2a] are crossed by a cavity covered with a layer 22 of electrically conductive material. The cavity is here a blind hole whose bottom is located at the level of substrate 20, close to the lower surface of the substrate 20. This layer 22 of electrically conductive material at least partially covers the “free” surface 21a of the first layer 21 of dielectric (i.e. the surface 21a which is not against the substrate 20 and which is not along the formed cavity) on either side of the cavity.The layer 22 of electrically conductive material forms one of the electrodes of the ionic capacity 2, called here the bottom electrode. The layer 22 of electrically conductive material is covered (at least partially) with a layer 23 of a material that is both ionic and dielectric (ionic dielectric). This layer 23 of ionic conductor is covered (at least partially) with a layer 24 of electrically conductive material, which forms the other electrode of the ionic capacity 2, called the top electrode. The bottom electrode 22 and the top electrode 24 are therefore electrically insulated from each other by the layer 23, which nevertheless allows the ions to circulate between the two electrodes 22 and 24.

[0093] It is noted that the example shown in [Fig.2a] is not limiting and that other configurations are possible. For example, in certain configurations, the cavity only passes through the first dielectric layer 21. Furthermore, the shape of the cavity is not limiting, and can be replaced by a pore in a porous dielectric layer 21, as described in application EP3570307.

[0094] In the example of [Fig.2a], the lower electrode 22, the ionic dielectric layer 23 and the upper electrode 24 of the ionic capacitor 2 are arranged according to a MIM (metal - insulator - metal) structure in which the insulator is an ion-conducting dielectric (ionic dielectric), but other configurations are possible, for example a MOIM (metal - oxide - ionic dielectric - metal) configuration. in which an oxide layer is intercalated between the lower electrode and the ionic dielectric layer, as in application EP3570307.

[0095] The presence of the cavity in the assembly formed by the substrate 20 and the dielectric layer 21 of [Fig.2a] is not obligatory, but it advantageously makes it possible to increase the effective surface area for accumulation of charges between the two electrodes 22 and 24. Furthermore, it is noted that the ionic capacity 2 can be formed according to a planar or three-dimensional configuration, a three-dimensional configuration advantageously making it possible to increase the effective surface area for accumulation of charges between the two electrodes per unit of geometric surface area on the substrate, and therefore to increase the capacity density of the ionic capacity 2 (by acting solely on the geometry of the ionic capacity).

[0096] The application of a voltage Vc between the lower electrode 22 and the upper electrode 24 induces two distinct physical phenomena: on the one hand, the establishment of a double electrochemical layer between the ionic conductor 23 and the two electrodes 22 and 24 (appearance of an ionic capacitance), and on the other hand, the dielectric polarization of the ionic conductor 23 (appearance of a dielectric capacitance). The combination of these two phenomena gives the ionic capacitance a very high power density per unit area, of the order of a few tens of pF / mm2, i.e. several orders of magnitude higher than the power densities of MOS or MIM type dielectric components.

[0097] Furthermore, as shown in [Fig.2b], the value of the ionic capacitance of the capacitor 2 is variable and depends on the voltage Vc applied to the terminals thereof (i.e. between the two electrodes 22 and 24). When the voltage applied to the terminals of the ionic capacitor 2 increases, the value of the capacitance decreases over time, from a so-called "nominal" value to a capacitance value of the order of 10% of the nominal value. Furthermore, the ionic capacitor 2 self-discharges when no voltage is applied to its terminals. In this sense, the state of charge of the ionic capacitor 2 can be considered volatile.

[0098] [Fig.3a] represents an example of an electronic assembly allowing a relaxation of the conductance value of an ionic transistor according to an embodiment of the invention.

[0099] The assembly of [Fig.3a] comprises an ionic transistor 310 and an ionic capacitor 320, in which the gate G of the ionic transistor 310 is connected to an electrode Ei of the ionic capacitor 320. Furthermore, in the example of [Fig.3a], the drain D of the ionic transistor 310 is connected to the other electrode E2 of the ionic capacitor 320. It is noted that the drain and the source are interchangeable. Thus, it is possible to connect the source S of the ionic transistor 310 to the other electrode E2 of the ionic capacitor 320 (the gate G of the ionic transistor 310 always being connected to the electrode Ei of the ionic capacity 320). In the case of an ionic capacity having a “U-shaped” structure as in [Fig.2a], the electrodes El and E2 can correspond interchangeably to the upper electrode and the lower electrode of the ionic capacity.

[0100] In the example of [Fig.3a], the same voltage is applied to the gate G of the ionic transistor 310 and to the terminals of the ionic capacitor 320. It is thus possible to place the ionic transistor 310 in a given conductance state, and at the same time to modify the value of the capacitance of the ionic capacitor 320. It is noted that this is not obligatory.

[0101] For example, the ionic transistor 310 and the ionic capacitor 320 may be separated by an intermediate device, such as a multiplexer or a switch, which allows the gate G of the ionic transistor 310 to be connected to the electrode Ei of the ionic capacitor 320 only at a given time. Such an intermediate device makes it possible to control when the gate G of the ionic transistor 310 is connected to one of the electrodes of the ionic capacitor 320 (and thus to allow that at other times, the gate G of the ionic transistor 310 is not connected to an electrode of the ionic capacitor 320). Thus, it is possible to place the ionic transistor 310 in a certain conductance value and / or the ionic capacitor 320 in a certain capacitance value before connecting the gate G of the ionic transistor 310 to one of the electrodes of the ionic capacitor 320.This allows the ability to maintain the ionic transistor in a certain non-volatile state, and to control the instant at which this state is desired to begin to relax. In other words, this introduces an additional delay for the relaxation of the conductance value of the ionic transistor 310.

[0102] Furthermore, the time constant representative of the relaxation speed of the value of the conductance of the transistor depends partly on the conductance of the ionic transistor 310 and the value of the ionic capacitance. Also, by modifying the conductance value of the ionic transistor 310 and / or the value of the ionic capacitance 320 (before connecting the gate of the ionic transistor 310 to one of the electrodes of the ionic capacitance 320), it is possible to modulate this time constant, and therefore the relaxation speed of the conductance of the ionic transistor 310.

[0103] In one or more embodiments, the operation of the electrochemical charge storage element 36 can therefore comprise the following steps, shown in [Fig.6]: • writing step: • a first electrical signal (voltage or current) is applied (step 610) between the source and the gate of the ionic transistor 310 so that the latter enters a given conductance state; and • a second electrical signal (voltage or current) is applied (step 620) between the two electrodes of the ionic capacity 320; • reading step: the source or the drain of the ionic transistor 310 is connected to one of the electrodes of the ionic capacitor 320, while the gate of the ionic transistor 310 is connected to the other electrode of the ionic capacitor 320 (step 630).

[0104] As mentioned above, the first electrical signal and the second electrical signal may be the same, as in the diagram of [Fig.3a] (current IJ. The first electrical signal and the second electrical signal may also be two different electrical signals applied independently to the ionic transistor 310 on the one hand (first electrical signal), and to the ionic capacitor 320 on the other hand (second electrical signal). When the two electrical signals are different, they may be applied simultaneously or not (in the latter case, they may be applied at two distinct instants in time or during two distinct time intervals, which may or may not overlap).

[0105] [Fig.3b] represents a simplified model of an electrical diagram equivalent to the electronic assembly of [Fig.3a]. In this model, the ionic transistor comprises a variable resistor Rv, as well as a resistor RT and a capacitor CT, the resistor RT and the capacitor CT both being connected to the gate G via one of their terminals, and to the drain D via the other of their terminals. The resistance RT corresponds to the ionic resistance of the transistor, due to the migration of ions from the gate to the channel. The capacitor CT corresponds to the geometric capacity of the ionic transistor, i.e. the “dielectric” capacity of the ionic transistor 310.

[0106] By connecting the gate of the ionic transistor 310 to an electrode of the ionic capacitor 320, a partial “discharge” of the ionic transistor 310 to the ionic capacitor 320 occurs. This results in a relaxation of the conductance value of the ionic transistor 310, as shown in [Fig.7].

[0107] The curves in [Fig.7] were obtained by simulation, using the approximate equivalent modeling of [Fig.3b], once the ionic transistor is in a given conductance state (and no gate voltage is applied). More precisely, several sets of curves are shown in [Fig.3b] (each set of curves being represented by the same type of line, for example a solid line, a broken line, a series of more or less close points, an alternation of one or more dashes and one or more points, etc.). Each set of curves corresponds respectively to the same nominal value of total capacitance, the total capacitance being the sum of the capacitances of the capacitance CT of the ionic transistor and the ionic capacitance Cb. To obtain the different curves of the same set of curves, the value of the ionic capacitance Ci was modulated by applying one or more voltage values ​​across the ionic capacitance (as explained above with reference to [Fig.2b], the capacitance value of the ionic capacitance varies depending on the voltage applied across the ionic capacitance).

[0108] The curves in [Fig.7] illustrate the relaxation of the conductance of the ionic transistor over time: the value of the conductance decreases with time. Thus, it appears that the connection of an electrode of an ionic capacity to the gate of the ionic transistor induces a volatility of the conductance state of the ionic transistor.

[0109] Furthermore, the curves in [Fig.7] illustrate the fact that the relaxation speed depends on the value of the total capacitance. It is thus possible to play on the value of the total capacitance (in particular by modulating the value of the ionic capacitance by applying a voltage across the terminals of the ionic capacitance) to modify the relaxation speed of the conductance of the ionic transistor.

[0110] As mentioned previously, the ionic transistor and the ionic capacitor are two components which use common layers in their operation (in particular the ion-conducting active layers 15 and 23 and the layers forming the electrodes 12, 13, 16, 22, 24). This makes it possible to produce a storage element having the characteristics of the circuit of [Fig.3a] by cointegration of an ionic transistor and an ionic capacitor on the same substrate, in which certain manufacturing steps of the two components are shared.

[0111] It is thus possible to produce a storage element having the same characteristics as the circuit shown in [Fig.3a] by depositing successive layers, as now described with reference to Figures 4a to 4f.

[0112] Figures 4a to 4f illustrate steps of a method of manufacturing a storage element according to an embodiment of the invention. The flowchart of this manufacturing method is shown in [Fig.5].

[0113] In a first step 510 ([Fig.5]) of the method, an electrically insulating layer can be deposited on a substrate. This step is illustrated in [Fig.4a].

[0114] As shown in [Fig.4a], an electrically insulating layer 41 (for example made of a dielectric material) is formed on a substrate 40, for example by a full-plate deposition process. The substrate 40 may be a wafer of semiconductor material. In certain embodiments, this wafer integrates one or more components such as conventional transistors or microsystems. In particular, the integration of the storage device of the present invention may be done in the “Back End Of Line”, that is to say after the production of the CMOS level and in higher levels, in the same way as the contacts. It is noted that the ionic conductive layer 41 may constitute the substrate on its own (in certain embodiments therefore, there may be only one dielectric layer 41 which replaces the two layers 40 and 41 of Figures 4a to 4f).

[0115] The dielectric layer 41 may be composed of one or more materials providing electrical insulation, for example an oxide, a nitride, an oxynitride, or any material or combination of materials capable of acting as chemical and electrical passivation between the substrate 40 and the memory element.

[0116] In a non-limiting embodiment, the substrate 40 may be a silicon wafer and the layer 41 may be a silicon oxide layer.

[0117] Furthermore, during the first step 510 of the method shown in [Fig.5], the assembly composed of the substrate and the ionic conductive layer can be structured to form a recess intended to receive the ionic capacity. This structuring is shown in [Fig.4b].

[0118] As shown in [Fig.4b], the “substrate 40 / dielectric layer 41” assembly can be structured to create an opening 42 (or “cavity” or “groove”) perpendicular to the surface plane of the dielectric layer 41 and the substrate 40. This structuring is carried out through the dielectric layer 41 and the substrate 40, and stops in the substrate volume without passing through it. In the example of [Fig.4b], the opening 42 is a blind hole in the dielectric layer 41 which passes through a portion of the substrate 40, and the bottom of which is located near the lower surface of the substrate 40. It is noted that depending on the embodiments, the opening 42 can pass through the substrate to a variable depth, or even pass through only all or part of the dielectric layer 41 (and therefore not pass through the substrate 40).In some embodiments, the structuring may be performed by a photolithography technique (typically comprising deposition of a resin layer by spin coating on the “substrate 40 / dielectric layer 41” assembly, exposure through a mask and development of the exposed resin) followed by plasma etching.

[0119] As mentioned with reference to [Fig.2a], the presence of the opening 42 is not obligatory, but it advantageously makes it possible to increase the effective surface area for accumulation of charges between the two electrodes 43b and 47b.

[0120] Referring again to [Fig.5], during a step 520, a first layer of an electrically conductive material can be deposited on the surface of the substrate, and structured in two parts having no contact points, one acting as a source electrode to the ionic transistor, and the other comprising both a drain electrode and the lower electrode of the ionic capacitor.

[0121] This step 520 is shown in [Fig.4c]: a layer 43 of electrically conductive material is formed on a portion of the surface of the dielectric layer 41 and at the opening 42 where appropriate. The layer 43 of electrically conductive material comprises two parts 43a, 43b separated by a space 44, so that the two parts 43a, 43b of the layer of electrically conductive material 43 have no contact points with each other and are not electrically connected. In the example of [Fig.4c], the portion 43b of the layer 43 of electrically conductive material covers a portion of the unstructured surface of the “substrate 40 / dielectric layer 41” assembly (i.e. the portion of the surface of the “substrate 40 / dielectric layer 41” assembly which is not at the level of the opening 42) as well as the walls and the bottom of the opening 42. As described below, the portion 43a plays the role of “source” of the ionic transistor of the storage component, and the portion 43b plays both the role of “drain” of the ionic transistor of the storage component and the lower electrode of the ionic capacitance of the storage component. It is noted that the source and drain electrodes may be interchanged (in particular, electrode 43a may represent the drain and electrode 43a may represent the source).

[0122] The layer 43 of electrically conductive material can typically be produced by deposition over the entire surface of the structured “substrate 40 / dielectric layer 41” assembly of [Fig.4b] (including the walls and the bottom of the opening 42), then by structuring in order to produce the space 44 and to give the desired shape and dimensions to the different parts of the layer 43. For example, the layer 43 can be deposited by vacuum cathode sputtering, and the structuring can be provided by photolithography followed by dry etching.

[0123] In certain embodiments, the deposition of the layer 43 of electrically conductive material may advantageously be a conformal deposition on the surface of the structured “substrate 40 / dielectric layer 41” assembly, i.e. its thickness is constant over the entire surface. This simplifies the manufacturing process of the electrochemical energy storage element, since a single layer can be deposited along the surface without the need to vary the thickness by adding additional layers.

[0124] In certain embodiments, the layer 43 may be a metallic layer of titanium having a thickness e (which corresponds to the dimension along the y axis in [Fig.4c], i.e. along the direction orthogonal to the surface of the substrate 40) of between 10 and 200 nm, for example equal to 100 nm.

[0125] Referring again to [Fig.5], in a step 530, a layer of an ion insertion material called a channel layer is deposited at the space between the source electrode and the drain electrode of the ionic transistor, so as to be in contact with both the source electrode and the drain electrode of the ionic transistor.

[0126] This step 530 is illustrated in [Fig.4d]: a layer 45 of an ion insertion material is formed and structured so as to cover the part of the layer 41 located at the space 34, as well as portions of the parts 43a and 43b of the layer 43, said portions including the ends of the parts 43a and 43b located at the space 34. space 44. As described below, this layer 45 constitutes the channel of the ionic transistor of the storage component, and is therefore in contact with the source 43a, the drain 43b and the part of the layer 41 located at the level of the space 44.

[0127] The channel 45 is composed of an ion insertion material making it possible to intercalate and de-intercalate ions under the application of an electric field and, thus, to change the electrical conductivity of the channel 45 depending on the intercalation rate. For example, the material composing the channel 45 may be a transition metal oxide, and more particularly a metal based on titanium dioxide nanoparticles (TiO2) having a size of approximately 10 nm, capable of intercalating lithium ions (Li+). The channel 45 may, for example, have a thickness of the order of a few nanometers to a few tens of nanometers.

[0128] Referring again to [Fig.5], during a step 540, a layer of a material that is both ionically conductive and dielectric can be deposited on the surface of the element obtained at the end of step 530.

[0129] This step 540 is illustrated in [Fig.4e]: a layer 46 of ionic and dielectric conductor is deposited on the surface and structured. The layer 46 is conductive for the same ions as the ion insertion material making up the channel 45. For example, if the channel 45 is in a material allowing the intercalation of Li+ ions, the material of the layer 46 is conductive for the Li+ ions.

[0130] The ionic and dielectric conductor layer 46 is in contact with the source 43a and the drain 43b, allowing ions to flow between these two electrodes 43a, 43b via the channel 45. The ionic conductor layer 46 covers a portion of the part 43b of the layer 43 of electrically conductive material, said portion of the part 43b of the layer 43 of electrically conductive material including the portion of the part 43b of the layer 43 of electrically conductive material at the opening 42. The layer 46 is “continuous” (in the sense that it does not have a “hole” or interruption) from a point of contact with the source 43a and the part of the layer 43b located on the other side of the opening 42 with respect to the channel 45. The ionic conductor layer 46 therefore forms both the ionic conductor layer of the ionic transistor and the ionic conductive layer of the ionic capacity.Layer 46 therefore allows ions to circulate both between the electrodes of the ionic transistor and between the electrodes of the ionic capacitor.

[0131] The layer 46 is composed of an ionic and dielectric conductive material, which allows the ions to flow both between the source 43a and the drain 43b of the ionic transistor of the storage element, and between the two electrodes 43b and 47b of the ionic capacitor of the storage element, while ensuring electrical insulation between the different electrode pairs. For example, this material may be a lithium phosphorus oxynitride (LiPON). The layer 46 may have a thickness of a few tens to a few hundreds of nm, for example 100 nm. In certain embodiments, this layer 46 is deposited by magnetron sputtering. The structuring can be carried out by photolithography for example.

[0132] In certain embodiments, the deposition of the layer 46 of ionic and dielectric conductive material may advantageously be a conformal deposition on the surface of the element of [Fig.4d].

[0133] Finally, during a step 550 of [Fig.5], a layer of an electrically conductive material can be deposited on the surface of the element obtained at the end of step 540, then structured.

[0134] This step 550 is illustrated in [Fig.4f], in which a layer 47 of an electrically conductive material is deposited on at least a portion of the layer 46. After possible structuring, this layer is advantageously “continuous” from a zone of the ionic conductive layer 46 located at the channel 45 to a zone of the ionic conductive layer 46 located on the other side of the opening 42 relative to the channel 45. This layer 46 forms both the gate of the ionic transistor and the upper electrode of the ionic capacitor. In certain embodiments, the deposition of the layer 47 of electrically conductive material may advantageously be a conformal deposition on the surface of the element of [Fig.4e].

[0135] For example, layer 47 may be a titanium metal layer having a thickness of 100 nm, deposited by vacuum sputtering. The structuring of layer 47 may for example be carried out by photolithography and dry etching.

[0136] The above exemplary embodiments focus on a memory component operating on lithium Li+ ions, but it is entirely possible to use other charge-carrying ions, such as Na+, H+, K+, Cu+, etc.

[0137] The electrochemical energy storage element 400 of [Fig.4f] is shown in section on the (x, y) plane. In one or more embodiments, the channel width may be less than 200 nm, preferably less than 20 nm. The channel width corresponds to the dimension along the z axis (z being the third axis of an orthonormal (x, y, z) reference frame) of the channel 45 of the ionic transistor 420. The width of the ionic capacitance 420 (i.e. the dimension of the ionic capacitance 420 along the z axis) may be less than 2 pm, preferably less than 1 pm. The depth of the ionic capacitance 420 (i.e. its dimension along the y axis) may be greater than 2 pm, preferably greater than 5 pm.

[0138] The electrochemical storage element 400 obtained at the end of the different steps shown in [Fig.4a] to 4f comprises an ionic transistor 410 (of similar structure to the ionic transistor 1 shown in [Fig.1a]) and an ionic capacitor 410 (of similar structure to the ionic capacitor 2 shown in [Fig.2a]), in which: • the gate electrode of the ionic transistor 410 and the upper electrode of the ionic capacity 420 are connected (and here, formed in the same layer 47 of electrically conductive material), and • the drain electrode of the ionic transistor 410 and the lower electrode of the ionic capacitor 420 are connected (and here, formed in the same layer 43b of electrically conductive material).

[0139] As mentioned previously, the drain 43b and the source 43b of the ionic transistor 410 are interchangeable. Also, in the diagram of [Fig.4f], the electrode 43a could correspond to the drain, and the electrode 43b could correspond to the source of the transistor.

[0140] The ionic transistor 410 and the ionic capacitor 420 are produced monolithically on the same level of the substrate 40. As appears above, such an element can be manufactured by pooling certain manufacturing steps of the transistor and the ionic capacitor (deposition of the same layer for the two components and structuring).

[0141] Of course, the element 400 of [Fig.4f] is not an example of an electrochemical storage element as presented with reference to [Fig.3a]. The invention is not limited to this example. For example, the ionic transistor and the ionic capacitor may be two components manufactured separately on two distinct substrates and connected according to the diagram of [Fig.3a], with or without the presence of an intermediate connection element (for example a multiplexer or a switch). According to certain embodiments, other components may be interposed between the ionic transistor and the ionic capacitor. The ionic transistor and / or the ionic capacitor may also comprise additional layers. For example, an interposed layer in an ion insertion material dissociated from that of the ionic transistor may be implemented in the architecture of the ionic capacitor, so as to have a hybrid capacitor.For example, this interlayer can be inserted at the ionic capacitance, between layer 43b and layer 46 of [Fig.4f], i.e. between the lower electrode and the ionic conductive layer of the ionic capacitance. Such an implementation makes it possible to further increase the value of the capacitance density (in practice, this can be doubled in comparison with an isoarchitecture without interlayer), as described for example in the article by V. Sallaz et al. “Hybrid All-Solid-State Thin-Film Micro-supercapacitor Based on a Pseudocapacitive Amorphous TiO2 Electrode”, ACS Appl. Energy Mater. 2023, 6, 1, 201-210. Such an interlayer can be obtained from the fabrication method of [Fig.5]: in step 530, the ion insertion material layer can be deposited over the entire surface, and structured in two disjointed parts: one corresponding to the channel layer of the ion transistor, the other corresponding to the interlayer of the ion capacitor.

[0142] Furthermore, even if the ionic transistor 410 and the ionic capacitance 420 of the element 400 of [Fig.4f] are on the same substrate level, it is possible to superimpose the ionic transistor and the ionic capacitance on two different levels vertically relative to the plane of the substrate to increase the integration density of the electrochemical storage element. [Fig.8] represents such an example of a device. In the example of [Fig.8], the ionic transistor is produced on a lower substrate layer 81a and the ionic capacitance is produced on an upper substrate layer 81b, the layers 81a and 81b being separated by a layer 82 of dielectric material. The gate 83 of the ionic transistor is connected to the lower electrode 84 of the ionic capacitance.

Claims

Claims

1. Electrochemical charge storage device (400) comprising an ionic transistor (410) and an ionic capacitor (420), the ionic transistor comprising: - a layer (45) forming an ion reservoir, called a reservoir layer; - a source electrode (43a) in contact with a portion of the reservoir layer (45); - a drain electrode (43b) in contact with another portion of the reservoir layer (45), the drain electrode (43b) and the source electrode (43a) being physically separated from each other, the source electrode (43a) and the drain electrode (43b) each being made of an electrically conductive material;and - a gate electrode (47) in an electrically conductive material, the gate electrode being separated from the reservoir layer by an ionic conductive layer (46) in an ionic and dielectric conductive material, the ionic conductive layer (46) being in contact with the source electrode (43a) and with the drain electrode (43b); the ionic capacitor (420) comprising two electrodes (43b, 47), each of the two electrodes (43b, 47) being in an electrically conductive material, the ionic capacitor (420) comprising an ionic conductive layer (46) separating the two electrodes (43b, 47) of the ionic capacitor (420), the ionic conductive layer of the ionic capacitor (420) being in an ionic and dielectric conductive material; the device further comprising a connection element capable of connecting the gate electrode of the ionic transistor to a first electrode (47) among the two electrodes of the ionic capacitor.;

2. The device (400) of claim 1, wherein one of the source electrode and the drain electrode of the ionic transistor is connected to a second electrode (43b) of the two electrodes of the ionic capacitor, the second electrode (43b) being distinct from the first electrode (47).

3. Device (400) according to one of claims 1 and 2, in which the connection element is an element capable of connecting, directly or indirectly, the gate electrode of the ionic transistor to the first electrode of the ionic capacitor.

4. Device (400) according to one of the preceding claims, in which the connection element is one of a layer of an electrically conductive material, a conductive via, a switch or a multiplexer.

5. Device (400) according to one of the preceding claims, wherein the ionic conductive layer (46) of the ionic transistor and the ionic conductive layer (46) of the ionic capacitor are common.

6. Device (400) according to one of the preceding claims, wherein the gate electrode (47) of the ionic transistor and said first electrode (47) of the ionic capacitor are common.

7. Device (400) according to one of the preceding claims in combination with claim 2, in which the source electrode (43a) of the ionic transistor, the drain electrode (43b) of the ionic transistor and the second electrode (43b) of the ionic capacitor are made of the same electrically conductive material and have the same thickness.

8. The device (400) of claim 7, wherein the electrode (43b), among the drain electrode and the source electrode, of the ionic transistor connected to the second electrode of the ionic capacitor is called the connection electrode of the ionic transistor, wherein the connection electrode of the ionic transistor and the second electrode (43b) of the ionic capacitor are common.

9. Device (400) according to one of the preceding claims, in which the ionic transistor (410) and the ionic capacitor (420) are formed on the same substrate (40, 41), in a monolithic manner.

10. Device (400) according to claim 9, wherein the ionic transistor (410) and the ionic capacitor (420) are located on the same level of the substrate (40, 41).

11. A device (400) according to claim 9 or 10, wherein the substrate (40, 41) comprises a recess (42), wherein at least a portion of the ionic capacitor (420) is housed in the recess.

12. Device (400) according to one of the preceding claims, wherein the ionic capacity (420) further comprises an interlayer in an ion reservoir material, the interlayer separating the ionic conductive layer (46) of the ionic capacity and the electrode (43b), among the two electrodes of the ionic capacity, other than the first electrode.

13. Neuromorphic processing circuit of the “differential pair integrator” type comprising an electrochemical charge storage device according to one of claims 1 to 12.

14. A method of manufacturing an electrochemical charge storage device according to one of claims 1 to 12, the method successively comprising: - depositing (520), on a substrate, a first layer of electrically conductive material, and structuring said first layer so as to obtain a first part of the first layer and a second part of the first layer having no contact points, the first part of the first layer corresponding to one electrode among a source electrode and a gate electrode of the ionic transistor, the second part of the first layer corresponding to the other electrode among the source electrode and the drain electrode of the ionic transistor and to an electrode of the ionic capacitor; - depositing (530) the reservoir layer, the reservoir layer being in contact with the first part of the first layer and with the second part of the first layer;- depositing (540) an ionic conductive layer in an ionic conductive and dielectric material, the ionic conductive layer at least partially covering the first part of the first layer, the entire reservoir layer and at least partially the second part of the first layer; and - depositing (550) a second layer of electrically conductive material at least partially covering the ionic conductive layer, the second layer of electrically conductive material having no physical contact point with the first layer of electrically conductive material, the second layer of electrically conductive material forming a gate electrode of the ionic transistor and another electrode of the ionic capacitor.;

15. Manufacturing method according to the preceding claim, in which the deposition of at least one layer among the first layer of material electrically conductive, the ionically conductive layer and the second layer of electrically conductive material is a conformal deposit.

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