Frequency detection pixel
Patent Information
- Application Number
- FR2023008798
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-08-18
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2043-08-18
Abstract
Description
Title of invention: Frequency detection pixel Technical field
[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, to a pixel for detecting a frequency of a light signal received by this pixel. Prior art
[0002] Many known integrated circuits comprise at least one known pixel used to detect, or measure, a frequency of a light signal received by this pixel. Such circuits or pixels are for example used with frequency detection methods of the frequency modulated continuous wave (FMCW) type.
[0003] However, these pixels and circuits known for detecting the frequency of a received light signal have drawbacks.
[0004] For example, the photoconversion which takes place in these pixels to obtain a photocurrent at the frequency of the received signal is interfered with by photonic noise, and the useful part, or useful signal, of the photocurrent obtained is drowned in the noisy part of this photocurrent.
[0005] For example, when these frequency detection pixels are used to detect the frequency of infrared signals and are further arranged in a matrix of pixels used to detect visible light, these frequency detection pixels take the place of pixels for detecting visible light. This has a negative impact on the quality of the two-dimensional image obtained by means of the visible light detection pixels. Summary of the invention
[0006] There is a need to overcome all or part of the disadvantages of the circuits and / or pixels known for the frequency detection of a light signal, for example on the basis of an FMCW type method.
[0007] One embodiment overcomes all or part of the drawbacks of the circuits and / or pixels known for the frequency detection of a light signal, for example on the basis of an FMCW type method.
[0008] One embodiment provides a pixel comprising a first node, a second node configured to receive a first DC potential, and a plurality of acquisition channels each comprising: a photodiode adapted to detect radiation in a first wavelength range; a capacitive element coupling the photodiode to the first node; and a resistive element coupling a first terminal of the photodiode to the second node.
[0009] According to one embodiment, in each channel, the capacitive element has an electrode connected to the first node, and another electrode connected to the photodiode, for example to the first terminal of the photodiode.
[0010] According to one embodiment, the pixel further comprises a switch coupling the first node to a node configured to receive a second DC potential.
[0011] According to one embodiment, in each channel, the photodiode is a non-pinched photodiode.
[0012] According to one embodiment, the pixel comprises a read circuit having an input coupled, preferably connected, to the first node.
[0013] According to one embodiment, the pixel comprises a reading circuit having an input coupled, for example connected, to the first terminal of the photodiode of one of the channels of the pixel.
[0014] According to one embodiment, the reading circuit is configured to provide a binary signal in a first state if a voltage on the first node is greater than a threshold, and in a second state if the voltage on the first node is less than the threshold, the threshold being, for example, determined at least in part by the first potential.
[0015] According to one embodiment, the pixel comprises a reading circuit having an input connected to the second node, the reading circuit being configured to provide the first potential to the second node.
[0016] According to one embodiment, the reading circuit is further configured to convert a current on its input into a voltage, and to provide a binary signal in a first state if said voltage is greater than a threshold, and in a second state if said voltage is less than the threshold, the threshold being, for example, determined at least in part by the first potential.
[0017] According to one embodiment: the pixel comprises a first semiconductor region doped with a first conductivity type, adapted to detect radiation in a second wavelength range, for example visible, and extending from a first face, the first face being intended to receive radiation in the first and second wavelength ranges; the photodiode of each channel includes: - a second doped semiconductor region of the first conductivity type, corresponding to the first terminal of the photodiode and extending from a second face parallel to the first face, and - a third semiconductor region doped with the second conductivity type and sandwiched between the first region and the second region; the pixel comprises a vertical transfer gate extending from the second face to the first region, the transfer gate electrically isolating the photodiodes of the pathways from each other and being in contact with each second region.
[0018] According to one embodiment, the vertical transfer grid comprises a conductive core and an insulating sheath, the conductive core corresponding to the first node of the pixel.
[0019] According to one embodiment, the pixel further comprises: an additional reading circuit and a circuit configured to: selectively coupling and decoupling the first electrode of the photodiode from each channel of the second node; and selectively coupling and decoupling the first electrode of the photodiode of each channel of the additional readout circuit.
[0020] One embodiment provides a sensor comprising a plurality of pixels as described above. Brief description of the drawings
[0021] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0022] [Fig.l] represents an example of a pixel for the frequency detection of a light signal;
[0023] [Fig.2] represents an example of an embodiment of a pixel for the frequency detection of a light signal;
[0024] [Fig.3] represents an example of an alternative embodiment of a pixel for the frequency detection of a light signal;
[0025] [Fig.4] represents an example of an alternative embodiment of a part of the pixel of [Fig.3];
[0026] [Fig.5] represents a partial, three-dimensional sectional view of an exemplary embodiment of a pixel for the frequency detection of a light signal and for the acquisition of another light signal;
[0027] [Fig.6] represents a top and partial view of the pixel of [Fig.5]; and
[0028] [Fig.7] represents, schematically and at least partly in the form of circuits, the pixel of figures 5 and 6. Description of the embodiments
[0029] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various known circuits, systems and applications in which one or more frequency detection pixels may be provided have not been detailed, the embodiments and variants described here being compatible with these known circuits, systems and applications.
[0031] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0033] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0034] [Fig. 1] represents an example of a pixel PIX1 for the frequency detection of a light signal SIGL.
[0035] The pixel PIX1 comprises a photodiode PD. The photodiode PD is a non-pinned photodiode, or, in other words, is not a pinned photodiode.
[0036] The photodiode PD has its cathode K coupled to a node 100 configured to receive a bias potential Vdd. More particularly, the pixel PIX1 comprises a resistive element R coupling the cathode K of the photodiode PD to the node 100. The anode of the photodiode PD is coupled, for example connected, to a node 102 configured to receive a reference potential Vss. The potential Vdd is, for example, positive. The potential Vdd is greater than the potential Vss.
[0037] The pixel PIX1 further comprises a reading circuit LECT. The circuit LECT1 has an input coupled, preferably connected, to the cathode K of the photodiode PD.
[0038] In operation, the photodiode PD of the pixel PIX1 receives the light signal SIGL and converts it into a photocurrent Iph. This current Iph is converted, by the resistive element R, into a voltage Vph available on the cathode K of the photodiode PD. The circuit LECT1 receives the voltage Vph and provides a binary output signal OUT1. The circuit LECT1 is configured so that the signal OUT1 is in a first binary state when the voltage Vph is greater than a threshold, for example equal to the direct current (DC) voltage present on the cathode K of the photodiode PD, and in a second binary state when the voltage Vph is lower than this threshold.
[0039] As the photocurrent evolves at the same frequency as the SIGL signal, the voltage Vph includes an alternating component (AC from the English "Alternative Current") at the frequency of the signal, and the signal OUT1 is then a periodic binary signal at the frequency of the SIGL signal.
[0040] However, the above operation does not take into account the photonic noise in the photodiode PD. This photonic noise results in a noise component in the photocurrent Iph, itself resulting in a noise component in the voltage Vph. This noise in the voltage Vph results in unwanted switching of the signal OUT1, which then no longer oscillates at the frequency that the pixel PIX1 was intended to detect or measure.
[0041] A pixel is proposed here comprising several acquisition channels each comprising a standard (or non-pinched) photodiode. The photodiodes of the pixel are connected to each other by capacitive coupling elements. Each photodiode of the pixel provides a signal having a useful component at the frequency of the light signal received by the pixel. As the photonic noise is different in each of the photodiodes of the pixel, the coupling capacitances allow averaging of this photonic noise, from which it follows that the noise component in the signal provided by the photodiodes of the pixel is reduced compared to the useful component of this signal.
[0042] [Fig.2] represents an example of an embodiment of a pixel PIX2 for the frequency detection of a light signal SIGL.
[0043] The pixel PIX2 comprises a node 200 configured to receive a bias potential Vdd2. In the example of [Fig.2], the potential Vdd2 is received by the node 200. As in the pixel PIX1, the potential Vdd2 is a DC potential.
[0044] The pixel PIX2 further comprises a node 202.
[0045] The pixel PIX2 comprises N CHi acquisition channels, with N an integer greater than or equal to 2, and i an integer index ranging from 1 to N. In the example of [Fig.2], the pixel PIX2 includes N=2 acquisition channels CHI and CH2.
[0046] Each channel CHi comprises a photodiode PDi. Thus, in the example of [Fig.2], the channel CHI comprises a photodiode PDI and the channel CH2 comprises a photodiode PD2.
[0047] Each photodiode PDi is a non-pinched photodiode.
[0048] Each channel CHi further comprises a resistive element, for example a resistor, Ri. Thus, in the example of [Fig.2], the channel CHI comprises an element RI and the channel CH2 comprises an element R2.
[0049] In each channel CHi, the cathode Ki (Kl and K2 in [Fig.2]) of the photodiode PDi of this channel CHi is coupled to the node 200 by the resistive element Ri of this channel CHi. In the example of [Fig.2], in each channel CHi, the element Ri has a terminal connected to the cathode Ki of the photodiode PDi and another terminal connected to node 200.
[0050] In each channel CHi, the anode of the photodiode PDi is coupled, for example connected, to a node 201 configured to receive a reference potential Vss. The potential Vss is a DC potential. The potential Vdd2 is, for example, positive. The potential Vdd2 is greater than the potential Vss.
[0051] Each channel CHi also comprises a capacitive element, for example a capacitor, Cci. Thus, in the example of [Fig.2], the channel CHI comprises an element Ccl and the channel CH2 comprises an element Cc2.
[0052] In each channel CHi, the capacitive element Cci couples the cathode Ki of the photodiode PDi to the node 202 of the pixel PIX2. For example, in each channel CHi, the element Cci has one terminal (or electrode) connected to the cathode Ki of the photodiode PDi of the channel CHi, and another terminal (or electrode) connected to the node 202. Preferably, the elements Cci all have substantially equal capacitance values, for example equal.
[0053] In pixel PIX2, when the SIGL signal is received by the photodiodes PDi of pixel PIX2, each photodiode PDi provides a photocurrent Iphi (Iphl and Iph2 in [Fig.2]) converted into a voltage Vphi (Vphl and Vph2 in [Fig.2]) on the cathode Ki of the photodiode PDi. In each PDi channel, the photocurrent Iphi and the corresponding voltage Vphi each comprise a similar or identical useful component in all the channels CHi and a different noise component in each channel CHi. This results from the fact that the photodiodes PDi are subjected to the same incident signal SIGL but the photonic noise is different from one photodiode to another.
[0054] Furthermore, when the node 202 is left floating, the capacitive elements Cci coupling the photodiodes PDi together impose, by capacitive coupling, a common inertia on all the voltages Vphi. This results in the similar components in all the channels CHi, i.e. the useful signal, being preserved, while the noise components will be reduced. In other words, the capacitive elements Cci implement an averaging function which tends to reduce the noise components of the channels CHi and to bring their voltages Vphi back to their average value which corresponds to the useful signal which is at the frequency of the signal SIGL.
[0055] According to one embodiment, the pixel PIX2 comprises a circuit for initializing the node 202 to an initialization potential Vrst. The initialization circuit is configured to set the node 202 to the potential Vrst before an acquisition phase, or frequency detection phase, then to leave the node 202 floating during this acquisition phase. The potential Vrst is, for example, chosen so that, when the node 202 is floating, the voltage V on the node 202 can follow the variations of the useful components of the voltages Vphi without clipping. For example, in [Fig.2], the potential Vrst can be chosen to be substantially equal, for example equal, to the average of the potentials Vdd2 and Vss.
[0056] The initialization circuit comprises a switch IT1, for example a MOS (Metal Oxide Semiconductor) transistor. The switch IT1 couples the node 202 to a node 204 configured to receive, at least during an initialization phase prior to a frequency detection phase, the potential Vrst. By way of example, the switch IT1 comprises a conduction terminal coupled, preferably connected, to the node 202, and another conduction terminal coupled, preferably connected, to the node 204. The switch IT1 is controlled by a signal RST. The signal RST is, for example, provided by a control circuit of the pixel PIX2, this control circuit being for example part of the pixel PIX2 or of a more complex circuit or system comprising the pixel PIX2.
[0057] The pixel PIX2 comprises a reading circuit LECT2. The circuit LECT2 is configured to provide a binary signal OUT2 at the frequency of the signal SIGL from a signal (voltage or current) present on a node of the pixel PIX2. More particularly, the circuit LECT2 has an input coupled or connected to a node of the pixel PIX2 on which a signal at the frequency of the signal SIGL is available, and an output configured to provide the signal OUT2.
[0058] For example, the signal OUT2 is a binary signal in a first binary state when the input signal of the circuit LECT2 is greater than a threshold, and in a second binary state when the input signal of the circuit LECT2 is less than this threshold. For example, the value of this threshold is determined by a DC component of the input signal of the circuit LECT2, so that the signal OUT2 is at the frequency of the signal SIGL.
[0059] In the embodiment of [Fig.2], the circuit LECT2 has its input coupled, preferably connected, to the node 202. For example, in the example of [Fig.2], the circuit LECT2 comprises a comparator COMP having an input connected to the input of the circuit LECT2 and an output connected to the output of the circuit LECT2, the output of the comparator COMP providing the signal OUT2.
[0060] Although in the example of [Fig.2], the number N of CHi channels is equal to 2, the person skilled in the art will be able to provide pixels PIX2 comprising a number N of CHi channels strictly greater than 2.
[0061] [Fig.3] represents an example of an alternative embodiment of a PIX3 pixel for the frequency detection of a light signal.
[0062] The PIX3 pixel includes many elements in common with the PIX2 pixel, and only the differences between these two pixels are highlighted here.
[0063] In the example of [Fig.3], the pixel PIX3 comprises N=2 CHi channels.
[0064] The pixel PIX3 comprises a reading circuit LECT3 in place of the circuit LECT2 of the pixel PIX2. Like the LECT2 circuit, the LECT3 circuit is configured to provide a binary signal OUT3 at the frequency of the SIGL signal from a signal (voltage or current) present on a node of the pixel PIX3. More particularly, the LECT3 circuit has an input coupled or connected to a node of the pixel PIX3 on which a signal at the frequency of the SIGL signal is available, and an output configured to provide the signal 0UT3.
[0065] For example, the signal OUT3 is a binary signal in a first binary state when the input signal of the circuit LECT3 is greater than a threshold, and in a second binary state when the input signal of the circuit LECT3 is less than this threshold. For example, the value of this threshold is determined by a DC component of the input signal of the circuit LECT3, so that the signal OUT3 is at the frequency of the signal SIGL.
[0066] Compared to the embodiment of [Fig.2] where the circuit LECT2 of the pixel PIX2 has its input coupled, preferably connected, to the node 202, in the alternative embodiment of [Fig.3] the circuit LECT3 of the pixel PIX3 has its input coupled, preferably connected, to the node 200.
[0067] Thus, in the variant embodiment of [Fig. 3], with respect to the circuit LECT2, the circuit LECT3 is further configured to provide a DC bias potential to the node 200, or, in other words, to impose the DC potential of the node 200.
[0068] Furthermore, in the embodiment variant of [Fig. 3], the input of the circuit LECT3 receives the sum of the photocurrents Iphi supplied to the node 200 by the photodiodes PDi of the channels CHi of the pixel PIX3. The circuit LECT3 then compares the total current I that it receives to a threshold to determine the state of the signal OUT3. More particularly, the signal OUT3 is in a first binary state if the current I is greater than the threshold, and in a second binary state if the current I is less than the threshold. For example, the value of the current threshold is determined by a DC component of the current I, so that the signal OUT3 is at the frequency of the signal SIGL.
[0069] More particularly, in the example of [Fig.3], the circuit LECT3 implements a conversion of the current I that it receives on its input into a voltage VI, then it is this voltage VI which is compared to a voltage threshold to determine the state of the signal OUT3. For example, the value of this voltage threshold is determined by a DC component of the voltage VI, so that the signal OUT3 is at the frequency of the signal SIGL.
[0070] According to one embodiment, as illustrated in [Fig.3], the circuit LECT3 comprises a resistive element, for example a resistor, Res and a MOS transistor T connected in series between the input of the circuit LECT3 and a node 300 configured to receive a bias potential Vdd3. The transistor T and the resistive element Res are connected to each other on a node 302. The transistor T is connected between the input of the circuit LECT3 and node 302, the resistive element Res being connected between node 302 and node 300. For example, transistor T has one conduction terminal connected to node 302 and another conduction terminal connected to the input of circuit LECT3. For example, the resistive element Res has one terminal connected to node 302 and another terminal connected to node 300.
[0071] The transistor T is controlled by a continuous potential Vdc applied to its gate, so as to impose the continuous polarization potential of the node 200, or, in other words, so that the node 200 receives this continuous polarization potential. In other words, the transistor T is mounted in cascode and receives the cascode voltage Vdc on its gate.
[0072] The resistive element Res is configured to convert the current I received by the input of the circuit LECT3 into a voltage VI, in this example available on the node 302.
[0073] In this embodiment, the circuit LECT3 further comprises a circuit COMP, for example a comparator, configured to compare the voltage VI to the threshold and to provide the signal OUT3 based on the result of this comparison. For example, the circuit COMP has an input coupled, preferably connected, to the node 302, and an output coupled, preferably connected, to the output of the circuit LECT3 on which the signal OUT3 is available.
[0074] [Fig.4] represents an example of an alternative embodiment of a part of the pixel PIX3 of [Fig.3], and, more particularly, of the circuit LECT3.
[0075] In this variant, the circuit LECT3 comprises an operational amplifier AOP. The amplifier AOP has an input 404 coupled, preferably connected, to the input of the circuit LECT3, and another input 406 coupled, preferably connected, to a node 400 configured to receive a bias potential Vdd4. The output of the amplifier AOP is connected to a node 402 of the circuit LECT3. A resistor Rlect is connected between the input 404 of the amplifier AOP and the node 402 (output of the amplifier AOP). The amplifier AOP is connected as a summing circuit with the resistors Ri of the channels CHi of the pixel PIX3 (see [Fig. 3]). The amplifier AOP also makes it possible to impose a bias potential on the node 200 to which the input of the circuit LECT3 is coupled, preferably connected (see [Fig. 3]).The AOP amplifier converts the sum of the currents Iphi in the channels CHi of the pixel PIX3, i.e. the current I received by the input of the circuit LECT3, into a voltage VI available on the node 402.
[0076] In this alternative embodiment, as in [Fig. 3], the circuit LECT3 further comprises a circuit COMP, for example a comparator, configured to compare the voltage VI to the threshold and to provide the signal OUT3 based on the result of this comparison. For example, the circuit COMP has an input coupled, preferably connected, to the node 402, and an output coupled, preferably connected, to the output of the circuit LECT3 on which the signal OUT3 is available.
[0077] Embodiments and variants of a pixel having several channels CHi in each of which a photodiode PDi and a capacitive element Cci are provided coupling an electrode of the photodiode to a node 202 of the pixel have been described. The person skilled in the art is able, from the description given of these embodiments and variants, to implement this pixel. In particular, the person skilled in the art will be able to provide other implementations of the circuits LECT2 and LECT3 than those given as examples.
[0078] An implementation of the pixel PIX2 that the person skilled in the art will be able to adapt to the pixel PIX3 will now be described. This implementation is particularly suitable and advantageous when the pixel PIX2 is intended to be implemented in a pixel matrix of a sensor configured to detect light signal frequencies, for example infrared, and to acquire a two-dimensional image of a scene. An example of such an implementation will now be described in relation to FIGS. 5, 6 and 7.
[0079] [Fig. 5] represents a partial, three-dimensional sectional view of an exemplary embodiment of a PIX2 pixel for the frequency detection of a light signal, for example infrared, and for the acquisition of another light signal, for example visible. [Fig. 5] is taken in a section plane AA of [Fig. 6] which represents a partial top view of the PIX2 pixel.
[0080] In these figures 5 and 6, the circuit LECT2, the resistors Ri and the switch IT1 have not been shown so as not to overload the figures. In these figures, the number N of channels CHi of the pixel PIX2 is equal to 4, but the person skilled in the art will know how to adapt the description of figures 5 and 6 to pixels comprising any number N of channels greater than or equal to 2.
[0081] The pixel PIX2 comprises a portion of a silicon substrate extending in thickness (or height) between a face 500 (lower face in [Fig.5]) and a face 502 (upper face in [Fig.5]), the face 502 being the face shown in [Fig.6]. The face 500 is the face of the pixel PIX2 intended to receive light, that is to say both the light signal, for example infrared, of which the pixel PIX2 will detect the frequency and the light signal, for example visible, that the pixel PIX2 will integrate, for example to obtain a corresponding image pixel of a two-dimensional image of a scene.
[0082] The silicon substrate portion of the pixel PIX2 is delimited laterally by an insulation structure 506 extending through the entire thickness of the substrate, i.e. an insulation structure 506 extending from the surface 502 to the surface 500. Preferably, the structure 506 entirely surrounds the semiconductor substrate portion of the pixel PIX2.
[0083] The structure 506 is, for example, a capacitive deep trench insulation (CDTI). In this case, the structure 506 comprises a core of conductive material (not shown in Figures 5 and 6) coated with an insulating sheath (not shown in Figures 5 and 6) insulating the conductive core of silicon from the portion of the substrate of the PIX2 pixel.
[0084] As an alternative example, the structure 506 is a deep trench insulation (DTI). Preferably, in this alternative example, a layer (not illustrated in Figures 5 and 6) doped with a first conductivity type, the P type in the example of Figures 5 and 6, completely covers the sides of the structure 506.
[0085] The pixel PIX2 comprises a semiconductor region 508 doped with a second conductivity type, the N type in the example of FIGS. 5 and 6. The region 508 is, for example, a portion of a layer extending in thickness from the face 500. In other words, the region 508 extends from the face 500. The region 508 is delimited laterally by the structure 506 with which the region 508 is in contact. The region 508 has, for example, a substantially constant thickness, its thickness being measured in a direction orthogonal to the faces 500 and 502 of the pixel PIX2. The region 508 is configured to implement a pinned photodiode.
[0086] In this embodiment, the photodiode PDi (PDI, PD2, PD3 and PD4 in figures 5 and 6) of each channel CHi (not referenced in figures 5 and 6) comprises a semiconductor region 510 ([Fig.5]) doped with the second conductivity type, the N type in this example.
[0087] In each photodiode PDi, region 510 is preferably more heavily doped than region 508, or, in other words, the doping level of each region 510 is higher than the doping level of region 508. In this example, regions 510 are therefore more heavily doped with N type (N+) than region 508.
[0088] For each photodiode PDi, region 510 corresponds, in this example, to the cathode Ki (K1, K2, K3 and K4 in figures 5 and 6) of the photodiode PDi.
[0089] Each region 510 extends from the face 502 of the pixel PIX2. Preferably, the regions 510 all have the same thickness. For example, each region 510 corresponds to a portion of a doped layer of the second conductivity type having a face coincident with the face 502.
[0090] In this embodiment, the photodiode PDi of each channel CHi further comprises a semiconductor region 512 doped with the first conductivity type, the P type in this example. In [Fig.5], only the regions 512 of the photodiodes PD3 and PD4 are visible.
[0091] For each photodiode PDi, the region 512 corresponds, in this example, to the anode of the photodiode PDi. Thus, although this is not shown in Figures 5 and 6, the pixel PIX2 comprises means configured to apply the potential Vss to the regions 512.
[0092] By way of example, when the structure 506 is of the DTI type bordered by a doped layer of the same type as the regions 512, the pixel PIX2 comprises a doped region of the same type as the regions 512 which is flush with the surface 502 and which is in contact with this doped layer, so that by applying the potential Vss to this region, the potential Vss is also applied to the regions 512.
[0093] As an alternative example, when the structure 506 is of the CDTI type, the pixel PIX2 comprises a circuit configured to apply a bias potential to the conductive core of the structure 506 so that a doped layer of the same conductivity type as the regions 512 is formed along the walls of the structure 506, and the pixel PIX2 further comprises a doped region of the same type as the regions 512 which is flush with the surface 502 and which is in contact with this doped layer, so that by applying the potential Vss to this region, the potential Vss is also applied to the regions 512
[0094] In each photodiode PDi, region 512 is sandwiched between region 508 and region 510 of the photodiode PDi. In other words, in each photodiode PDi, region 512 extends in thickness from region 508 to region 510 of this photodiode PDi. In other words, in each photodiode PDi, region 512 has one face in contact with one face of region 508, and an opposite face in contact with region 510 of this photodiode PDi.
[0095] Preferably, the regions 512 all have the same thickness. For example, each region 512 corresponds to a portion of a doped layer of the first conductivity type resting on and in contact with the region 508.
[0096] The pixel PIX2 further comprises a vertical transfer gate VEGA. The gate VEGA extends vertically from the face 502 of the pixel PIX2 to the region 508, and preferably penetrates into the region 508 over only a portion of the thickness of the region 508. The gate VEGA electrically isolates the photodiodes PDi from each other. The gate VEGA is in contact with each of the regions 512. The gate VEGA comprises a conductive core (not shown in FIGS. 5 and 6) coated with an insulating sheath (not shown in FIGS. 5 and 6), the insulating sheath electrically insulating the conductive core from the silicon which borders the gate VEGA.
[0097] The conductive core of the VEGA gate corresponds, in this embodiment, to the node 202 of the pixel PIX2. Thus, advantageously, in this embodiment, the capacitive elements Cci (Ccl, Cc2, Cc3 and Cc4 in FIGS. 5 and 6) are implemented by the VEGA gate, and, more particularly, by the conductive core 202 of the VEGA gate which corresponds to a first electrode of the capacitive element Cci, the insulating sheath of the VEGA gate which corresponds to the insulating layer of the capacitive element, and by the region 510 of the corresponding photodiode PDi which corresponds to the second electrode of the capacitive element Cci. The capacitive elements Cci are shown schematically in Figures 5 and 6.
[0098] Thus, in the pixel PIX2 of figures 5 and 6, when: - light, for example visible, is received by face 500 of pixel PIX2, - the potential of the conductive core of the VEGA grid has been initialized to a value such that the VEGA grid is blocked, i.e. photogenerated charges in the pinched photodiode 508 cannot be transferred to the regions 510, - the conductive core of the VEGA grid is left floating, and - face 500 also receives the SIGL light signal, for example an infrared signal, then the pixel PIX2 integrates the light, for example visible, received in the region 508, and, at the same time, the light signal SIGL, for example infrared, is converted in each photodiode PDi into a corresponding photo-current Iphi (not referenced in figures 5 and 6). Due to the presence of the capacitive elements Cci coupling each photodiode PDi to the floating node 202, the pixel PIX2 implements the photonic noise reduction function in the photodiodes PDi. The reading circuit LECT2 of the pixel PIX2 (not shown in figures 5 and 6) can then read a signal at the frequency of the signal SIGL on the node 202.
[0099] After a phase of detection of the frequency of the SIGL signal during which light, for example visible, has been converted into photogenerated charges in the pinched photodiode 508, the charges accumulated in the region 508 can be read by applying a potential to the VEGA gate putting the latter in the on state. The accumulated charges are then transferred to the regions 510 where they can be read by an additional dedicated reading circuit.
[0100] During this photogenerated charge reading phase, although this is not illustrated in FIGS. 5 and 6, the regions 510 are electrically isolated from the node 200 ([Fig.2]) by a circuit configured for this purpose, while they are coupled to this node 200 by this same circuit during a phase of detecting the frequency of the light signal SIGL.
[0101] Furthermore, this circuit configured to selectively couple and decouple each of the regions 510 to the node 200 is also configured, during the reading phase of the charges accumulated in the region 508, to couple each of the regions 510 to a detection node ("sens node" in English) of the pixel PIX2, while this circuit is configured not to couple these regions 510 to the detection node during a frequency detection phase. An additional reading circuit configured to read the charges transferred to the detection node is connected to this detection node.
[0102] In other words, although not shown in Figures 5 and 6, the pixel PIX2 includes a circuit configured to selectively couple and decouple the regions 510 photodiodes PDi at node 200, for example at the corresponding resistor Ri which is connected to node 200, and for selectively coupling and decoupling the regions 510 of the detection node.
[0103] An exemplary embodiment of the pixel PIX2 where the readout circuits and the circuit configured to selectively couple and decouple the regions 510 of the photodiodes PDi to the node 200, and to selectively couple and decouple the regions 510 of the detection node, are detailed will now be described in relation to [Fig.7],
[0104] [Fig.7] represents, schematically and at least partly in the form of circuits, the pixel PIX2 of figures 5 and 6.
[0105] In this [Fig.7], the conductive core of the VEGA grid corresponding to node 202 is coupled to node 204 by switch IT1.
[0106] The pixel PIX2 comprises the circuit LECT2 having its input connected to the node 202 and its output providing the signal OUT2.
[0107] The pixel PIX2 comprises a detection node SN, and an additional reading circuit LECTSUP connected to the node SN. By way of example, the circuit LECTSUP comprises an initialization switch INIT of the node SN coupling the node SN to an initialization potential Vinit, a MOS transistor SF having its gate connected to the node SN and its drain connected to a bias potential Vsf, and a reading switch RD coupling the source of the transistor SF to a conductive reading line Vx. The operation of such a reading circuit, for example called a 3T circuit, is well known to the person skilled in the art. Furthermore, the person skilled in the art will be able to provide other examples of implementations of the circuit LECTSUP.
[0108] The pixel PIX2 further comprises an SEL circuit configured to selectively couple and decouple the region 510 of each of the photodiodes PDi to the node 200, and to selectively couple and decouple these regions 510 to the node SN. More particularly, the SEL circuit is configured, during a phase of transferring the photo-generated charges from the region 508 to the regions 510 and during a phase of reading these transferred charges, so that each region 510 is electrically coupled to the node SN by the SEL circuit and the SEL circuit electrically decouples each region 510 from the node 200, and, during a phase of detecting the frequency of the signal SIGL, to electrically couple each region 510 to the node 200 and to electrically decouple these regions 510 from the node SN.
[0109] As an example, for each channel CHi (CH1, CH2, CH3 and CH4 in [Fig.7]), the circuit SEL comprises a first switch coupling the region 510 of the photodiode PDi of this channel to the node 200, this first switch being for example in series with the resistor Ri of this channel CHi between the photodiode PDi of this channel CHi and the node 200, for example connected between this photodiode PDi and this resistor Ri. In addition, for example, for each channel CHi, the circuit SEL comprises a second switch coupling the region 510 of this channel CHi to the node SN. The first and second switches of the circuit SEL are, for example, controlled so that the first switches are blocked when the second switches are conducting, and so that the second switches are blocked when the first switches are conducting.
[0110] The person skilled in the art will be able to provide other implementations of the SEL circuit, for example using multiplexers.
[0111] During an initialization phase of the potential of the node 202 prior to a phase of frequency detection of the signal SIGL, the switch IT1 is put in the passing state by the signal RST, and the node 202 is then put at the potential Vrst of the node 204. Then the switch IT1 is put in the blocked state to leave the node 202 floating. During this initialization phase, preferably, the circuit SEL couples the regions 510 to the node 200 and decouples the regions 510 from the node SN.
[0112] During a following phase of detection of the frequency of the SIGL signal implemented simultaneously with a phase of integration of the light in the pinched photodiode 508 ([Fig.5]), the circuit SEL couples the regions 510 to the node 200 and decouples the regions 510 from the node SN. The circuit LECT2 then provides the signal OUT2 at the frequency of the SIGL signal.
[0113] During a following phase of transfer of the photogenerated charges from the region 508 ([Fig.5]) to the regions 510, the circuit SEL couples the regions 510 to the node SN and decouples the regions 510 from the node 200. Then the node SN is initialized to the initialization potential Vinit by the circuit LECTSUP. For example, the node SN is initialized to the potential Vinit by switching the switch INIT to the on state, then the switch INIT is switched to the off state so that the potential Vinit is stored on the node SN. Then, the transfer of charges to the node SN is implemented. For this, the switch IT1 is put in the on state so that the potential Vrst is applied to the node 202 (conductive core of the VEGA gate).The value of the potential Vrst is then chosen so that the VEGA gate is on, this value of the potential Vrst being, for example, different from that of the potential Vrst during the initialization phase of the core 202 prior to a frequency detection phase. More particularly, during the transfer phase, the value of the potential Vrst is chosen so that the gate is in the on state, whereas, during the initialization phase of the node 202, the value of the potential Vrst is chosen so that the VEGA gate remains blocked during the entire frequency detection phase. Setting the VEGA gate to the on state causes the transfer of charges from the region 508 to the node SN. The end of the charge transfer is caused by setting the VEGA gate to the off state. Setting the VEGA gate to the off state to complete the charge transfer is for example set to . works by switching the potential Vrst to a value suitable for switching the VEGA grid to the blocked state. Then, at the end of the transfer phase, the switch IT1 is switched to the blocked state.
[0114] Thus, a transfer phase successively comprises an initialization of the node SN, a setting of the gate VEGA to the on state, then a setting of the gate VEGA to the off state. Preferably, throughout the transfer phase, the circuit SEL maintains the regions 510 coupled to the node SN and the regions 510 decoupled from the node 200.
[0115] Following the transfer phase, during a reading phase of these transferred charges, the circuit SEL maintains the regions 510 coupled to the node SN and the regions 510 decoupled from the node 200. The circuit LECTSUP then reads the photogenerated charges which have been transferred into the regions 510. For the example of the LECTSUP circuit of [Fig.7], this reading phase comprises turning on the transistor RD.
[0116] For example, during a transfer phase, between the initialization of the regions 510 (therefore of the node SN) at the potential Vinit and the transfer of charges to the node SN, a phase of reading the initialization potential of the regions 510 (therefore of the node SN) can be provided, for example so as to implement a correlated double sampling (CDS). The reading of the node SN, and more particularly of the initialization potential of the node SN, is for example implemented by switching the switch RD to the on state.
[0117] For example, between the end of a phase of reading the transferred charges and the start of a simultaneous phase of integrating the light and detecting the frequency of the SIGL signal, the region 508 is emptied of the photogenerated charges present therein. For this, while the circuit SEL couples the regions 510 to the node SN and decouples the regions 510 from the node 200, the gate VEGA is put in the on state and the potential Vinit is applied to the regions 510. For the example of the LECTSUP circuit of [Fig. 7], this consists of setting the potential Vrst to a value suitable for making the gate VEGA on while the switch INIT is on, and, simultaneously, switching the switch INIT to the on state, so that the potential Vinit is applied to the regions 510, and therefore to the region 508 because the gate VEGA is on.
[0118] Although an example has been described in relation to [Fig.7] in which the LECT2 circuit is connected to the node 202, in another example not illustrated, this LECT2 circuit is coupled to the node 202 by a switch, so that, during a phase of transferring charges from the region 508 to the regions 510 and a phase of reading the transferred charges, this switch is put in the blocked state to electrically decouple the LECT2 circuit from the node 202.
[0119] An advantage of the pixel described in connection with Figures 5 to 7 is that, in a pixel array comprising a plurality of such pixels, when a pixel implements a frequency detection function, the resolution of a two-dimensional image captured by the pixel array is not affected since this pixel also implements, simultaneously with frequency detection, an integration of the visible light it receives.
[0120] Another advantage of the pixel described in relation to figures 5 to 7 is that the capacitive elements are directly integrated into the pixel, taking advantage of the presence of the VEGA transfer grid used for the transfer of photo-generated charges during the integration of the light corresponding to the acquisition of a two-dimensional image.
[0121] Although a pixel PIX2 has been described in relation to figures 5 to 7 in which the reading circuit LECT2 of the pixel is connected to the node 202, the person skilled in the art is able to adapt this description to the case of a pixel PIX2 in which the reading circuit LECT2 of the pixel is coupled, for example selectively, or connected to one of the regions 510 of the photodiodes PDi, and to the case of a pixel PIX3 in which the reading circuit LECT3 of the pixel is connected to the node 200.
[0122] Compared to the LECT2 circuit, the LECT3 circuit has the advantage that its bias potential Vdd3 ([Fig.3]) or Vdd4 ([Fig.4]) can be higher than the potential Vdd2 when these circuits are implemented with the pixel as described in relation to Figures 5, 6 and 7. Indeed, when the LECT2 circuit is connected to the node 202 of the pixel as described in relation to Figures 5, 6 and 7, that is to say to the conductive core of the VEGA grid, the threshold of the LECT2 circuit, for example of its comparator COMP, is determined so that the signal OUT3 is at the frequency of the SIGL signal, and, in addition, that the VEGA grid is in the blocked state, this threshold then being able to be zero, or even negative. This is not the case with the LECT3 circuit connected to the node 200.
[0123] Although not illustrated by a figure, one embodiment provides a sensor comprising a plurality of PIX2 or PIX3 pixels. For example, the sensor comprises a matrix of pixels. For example, a portion of the pixels of the matrix corresponds to PIX2 or PIX3 pixels, the other portion of the pixels of the matrix corresponding to pixels similar to the PIX2 and PIX3 pixels. These other pixels preferably have the same configuration of their VEGA gates to have the same pinched photodiode and capacitance characteristics on the SN node (although this is not essential) as the PIX2 or PIX3 pixels. Furthermore, these other pixels may be devoid of LECT2 and LECT3 circuits. These other pixels preferably comprise the SEL circuit, so as to have the same capacitance characteristics on the SN node (although this is not essential).Preferably, all the pixels of the matrix have the same dimensions in top view, which facilitates the implementation of the pixel matrix, and, in addition, reduces dispersions between pixels. Such a sensor then makes it possible to measure a frequency of the SIGL signal, preferably in the . infrared range, and, further, to acquire a two-dimensional image, for example a color image, by integrating light, for example visible, into the pinched photodiodes 508 of all the pixels of the matrix. Preferably, when the sensor is configured to acquire a color and two-dimensional image of a scene, the pixels PIX2 and PIX3 are configured to integrate blue light which penetrates less deeply into the silicon than red light and green light.
[0124] In the embodiments and variants described above, during a frequency detection phase of the SIGL signal, the node 202 is left floating after having been initialized to the potential Vrst, or, in other words, no potential is applied to the node 202 during a frequency detection phase.
[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.
[0126] In particular, examples of embodiments and variants have been described above in relation to Figures 2 to 7 in which, in each channel CHi, the capacitive element Cci of this channel CHi couples the cathode Ki of the photodiode PDi of the channel to the node 202, which corresponds, for example, to examples where the DC potential on the node 200 is greater than the potential Vss on the node 201. In other examples where the DC potential on the node 200 is less than the potential Vss, the photodiode PDi of each channel is connected in reverse of what has been described in relation to the figures, its anode then being on the side of the resistor Ri and its cathode on the side of the node 201, and the elements Cci then couple the anodes of the photodiodes PDi to the node 202. Taking the example of Figures 5 to 7, this amounts to reversing all the types of conductivity.
[0127] More generally, the person skilled in the art is able to adapt the examples described where the elements Cci couple the cathodes of the photodiodes PDi to the node 202 to examples where the elements Cci couple the anodes of the photodiodes Cci to the node 202.
[0128] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, with regard to the values of the different continuous potentials described above, the person skilled in the art is able, from the description given above, to choose these values to obtain the operation described.
Claims
Claims
1. Pixel comprising a first node (202), a second node (200) configured to receive a first DC potential and a plurality of acquisition channels (CH1, CH2) each comprising: a photodiode (PDI, PD2) adapted to detect radiation (SIGL) in a first wavelength range; a capacitive element (Ccl, Cc2) coupling the photodiode to the first node (202); and a resistive element (RI, R2) coupling a first terminal (Kl, K2) of the photodiode (PDI, PD2) to the second node (200).
2. Pixel according to claim 1, wherein, in each channel (CH1, CH2), the capacitive element (Ccl, Cc2) has an electrode connected to the first node, and another electrode connected to the photodiode (PDI, PD2), for example to the first terminal (Kl, K2) of the photodiode (PDI, PD2).
3. The pixel of claim 1 or 2, wherein the pixel further comprises a switch (IT1) coupling the first node (202) to a node (204) configured to receive a second DC potential (Vrst).
4. Pixel according to any one of claims 1 to 3, wherein, in each channel (CH1, CH2), the photodiode (PDI, PD2) is a non-pinched photodiode.
5. Pixel according to any one of claims 1 to 4, wherein the pixel (PIX2) comprises a read circuit (LECT2) having an input coupled, preferably connected, to the first node (202).
6. Pixel according to any one of claims 1 to 4, in which the pixel (PIX2) comprises a reading circuit (LECT2) having an input coupled, for example connected, to the first terminal (Kl, K2) of the photodiode (PDI, PD2) of one of the channels (CH1, CH2) of the pixel.
7. Pixel according to claim 5 or 6, wherein the reading circuit (LECT2) is configured to provide a binary signal (OUT2) in a first state if a voltage (V) on the first node (202) is greater than a threshold, and in a second state if the voltage (V) on the first node (202) is less than the threshold, the threshold being, for example, determined at least in part by the first potential.
8. A pixel according to any one of claims 1 to 4, wherein the pixel (PIX3) comprises a read circuit (LECT3) having an input connected to the second node (200), the read circuit being configured to provide the first potential to the second node.
9. Pixel according to claim 8, in which the reading circuit (LECT3) is further configured to convert a current (I) on its input into a voltage (VI) and to provide a binary signal (OUT3) in a first state if said voltage is greater than a threshold, and in a second state if said voltage is less than the threshold, the threshold being, for example, determined at least in part by the first potential.
10. Pixel according to any one of claims 1 to 9, wherein: the pixel comprises a first semiconductor region (508) doped with a first conductivity type, adapted to detect radiation in a second wavelength range, for example visible, and extending from a first face (500), the first face being intended to receive radiation in the first and second wavelength ranges; the photodiode (PDI, PD2) of each channel (CH1, CH2) comprises: - a second semiconductor region (510) doped with the first conductivity type, corresponding to the first terminal of the photodiode (PDI, PD2) and extending from a second parallel face (502) to the first face, and - a third semiconductor region (512) doped with the second conductivity type and sandwiched between the first region (508) and the second region (510);the pixel comprises a vertical transfer grid (VEGA) extending from the second face (502) to the first region (508), the transfer grid electrically isolating the photodiodes (PDI, PD2) of the channels (CH1, CH2) from each other and being in contact with each second region (512).;
11. A pixel according to claim 10, wherein the vertical transfer gate (VEGA) comprises a conductive core and an insulating sheath, the conductive core corresponding to the first node (202) of the pixel.
12. Pixel according to claim 10 or 11, wherein the pixel further comprises: an additional reading circuit (LECTSUP) and a circuit (SEL) configured to: selectively couple and decouple the first electrode (510, Kl, K2) of the photodiode (PDI, PD2) of each channel of the second node (200); and selectively couple and decouple the first electrode (510, Kl, K2) of the photodiode (PDI, PD2) of each channel of the additional reading circuit (LECTSUP).
13. A sensor comprising a plurality of pixels according to any one of claims 1 to 12.