Radio frequency communication device

Abstract

Radio Frequency Communication Device. Radio frequency communication device (100) comprising a clock signal generator (106) configured to deliver a clock signal, based on a time base common to a communication mode and a standby mode, from a first reference signal (LSE, LSI) and a second reference signal (HSE). Figure for abbreviation: Fig. 2

Description

Title of the invention: Radio frequency communication device technical field

[0001] This description relates generally to radio frequency communication devices and in particular to BLUETOOTH® type radio frequency communication devices. Previous technique

[0002] Many radio frequency communication devices operate according to the BLUETOOTH®, BLUETOOTH® LOW ENERGY, or IEEE 802.15.4 protocols. These protocols require several clock signals with different precisions depending on the operating mode, e.g. in communication or standby.

[0003] Current devices use complex embedded software to implement the use of the various clock signals. This is costly in terms of development costs as well as production costs and results in significant power consumption. Summary of the invention

[0004] There is a need to improve current radio frequency communication devices.

[0005] One embodiment overcomes all or part of the drawbacks of known radio frequency communication devices.

[0006] One embodiment provides a radio frequency communication device comprising a clock signal generator configured to deliver a clock signal, based on a time base common to a communication mode and a standby mode, from a first reference signal and a second reference signal.

[0007] According to one embodiment, the clock signal generator includes a storage circuit configured for: - in the communication mode, be driven by a communication mode clock signal derived from the second reference signal, and be incremented according to a communication mode parameter; and - in standby mode, be driven by a standby mode clock signal from the first reference signal, and be incremented according to a standby mode parameter.

[0008] According to one embodiment, the clock signal generator includes a calibration circuit configured to output a number of periods of the second reference signal for a given number of periods of the first reference signal; the output of the calibration circuit giving a possible value for the standby mode parameter.

[0009] According to one embodiment, the accumulator circuit comprises a modulo function calculation circuit and a register, the modulo function calculation circuit being configured to implement a modulo function between a current value of said register and a comparison parameter associated with said given number of periods of the first reference signal, the register being configured to: - in the communication mode, be driven by the communication mode clock signal and receive as input said communication mode parameter to which is added an output result from the modulo function calculation circuit; and - in standby mode, be driven by a standby mode clock signal proportional to the first reference signal, and receive as input said standby mode parameter to which is added the output result of the modulo function calculation circuit.

[0010] According to one embodiment, the accumulator circuit includes a counter configured to: - in communication mode, to be driven by the communication mode clock signal and by a control signal dependent on a comparison between the current value of the register and the comparison parameter; and - in standby mode, be controlled by the standby mode clock signal and by said control signal.

[0011] According to one embodiment, the counter is configured to increment when the current value of the register is greater than the comparison parameter.

[0012] According to one embodiment, the accumulator includes a loop counter configured to be reset when it reaches a value equal to the ratio between a frequency of the communication mode clock signal and the frequency of the clock signal to be obtained.

[0013] According to one embodiment, the counter includes a shift register.

[0014] According to one embodiment, the value of said parameter of the communication mode and / or said standby mode parameter is imposed.

[0015] According to one embodiment, the communication mode parameter is set to zero during a transition between standby mode and communication mode.

[0016] According to one embodiment, the communication mode parameter is set, in the communication mode, to the value of the comparison parameter divided by the ratio between the frequency of the communication mode clock signal and the clock signal frequency to be obtained.

[0017] According to one embodiment, the standby mode parameter is set to an initial value equal to 1000 times the number of periods of the first reference signal.

[0018] According to one embodiment, the standby mode clock signal has a frequency equal to twice the frequency of the first reference signal.

[0019] According to one embodiment, the frequency of the clock signal to be obtained is 32 kHz, the frequency of the communication mode clock signal is 4 MHz, and the frequency of the second reference signal is 32 MHz, and the frequency of the first reference signal is between 16 and 60 kHz.

[0020] According to one embodiment, the comparison parameter is equal to 2000 times the number of periods of the first reference signal, and the number of periods of the first reference signal is chosen between 32, 64 and 128.

[0021] According to one embodiment, the values ​​of counter 220 and those of register 218 give respectively the integer part and the decimal part of the time base.

[0022] According to one embodiment, the first and second reference signals have different frequency accuracies.

[0023] According to one embodiment, the device is of the BLUETOOTH®, BLUETOOTH® LOW ENERGY, or IEEE 802.15.4 type. Brief description of the drawings

[0024] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0025] [Fig.1] represents an example of the architecture of a radio frequency communication device;

[0026] [Fig.2] represents a radio frequency communication device according to one embodiment;

[0027] [Fig.3] represents a timing diagram of an operating mode of the radio frequency communication device of [Fig.2];

[0028] [Fig.4] represents a timing diagram of another operating mode of the radio frequency communication device of [Fig.2];

[0029] [Fig. 5] represents a summary table of one operating mode of the radio frequency communication device of [Fig. 2]; and

[0030] [Fig.6] represents a summary table of another operating mode of the radio frequency communication device of [Fig.2]. Description of the implementation methods

[0031] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the Different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0033] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0035] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0036] Fig. 1 represents an example of the architecture of a radio frequency communication device.

[0037] The device 100 includes a radio frequency (RF) transmit / receive circuit 112 comprising, for example, an antenna and, for example, an impedance matching circuit. The circuit 112 is connected, preferably via, for example, a bus 113, to a radio frequency controller 110 (RF CTRL) implementing the radio frequency communication protocol of the device 100. The device 100 further includes, for example, a control unit 116 (CPU) comprising one or more processors under the control of instructions stored in a system instruction memory (not shown). The device 100 includes, for example, one or more volatile or non-volatile memories 120 (MEM). Device 100 further includes, for example, a set 108 of blocks 102 (LSE HW), 104 (HSE HW), 106 (32k, wake-up HW) and 107 (Active Clock) for generating different clock signals.Block 102 is configured to provide a reference clock signal, for example using a crystal oscillator. The clock signal provided by block 102 is, for example, centered on 32768 kHz.

[0038] Block 104 is configured to provide another reference clock signal, for example using another crystal oscillator. The clock signal provided by block 104 is, for example, at 32 MHz. Block 107 is configured to provide a clock signal, for example using the clock signal provided by block 104. In one example, the frequency of the clock signal provided by block 107 is obtained by dividing the frequency of the signal from block 104. When the clock frequency re The frequency sought to power controller 110 is, for example, 32 kHz, the frequency from block 104 is, for example, 32 MHz and the output of block 107 is, for example, 4 MHz.

[0039] In one example, block 106 receives as input the signal from block 107 as well as the signal from block 102. Other clock signals (LSI) not shown in [Fig.1], for example from an internal oscillator (RCO32k), can also be used by block 106. Block 106 is configured for example to wake up device 100 according to planned or programmed events.

[0040] The controller 116, the volatile or non-volatile memory(ies) 120 (MEM), the block 108 and the radio frequency controller 110 can exchange, via one or more system buses 114, data, addresses and commands for example.

[0041] The device 100 can further integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, other processing units), not shown in [Fig.1].

[0042] Device 100 is, for example, of the BLUETOOTH®, BLUETOOTH® LOW ENERGY, or IEEE 802.15.4 type. These protocols define, for example, timed events based on a sleep mode and a communication mode. In sleep mode, the device wakes up periodically to check if another device is nearby. In communication mode, the device communicates with another nearby device. In the case of BLUETOOTH® LOW ENERGY, for example, events are defined with a resolution of 0.625 ms. This protocol further specifies that event scheduling is performed using a clock signal with an accuracy of 500 ppm in sleep mode and 40 ppm in communication mode. This is usually achieved using clock signals from different crystal oscillators, such as signals from blocks 102 and 104.

[0043] To be usable by block 110, clock signals require calibration, for example. This calibration is implemented to take place periodically or at the beginning of the communication mode, for example. However, this calibration is often intrusive and requires software resources that negatively impact the energy efficiency of the device.

[0044] Furthermore, the use of different clock signals based on different crystals for the different modes of the device 100 implies the implementation of several time bases. Complex software resources are then required to enable the use of these different time bases. This impacts the implementation complexity, production costs, and energy efficiency of the device 100.

[0045] The described embodiments provide that the radio frequency communication device includes a clock signal generator configured to deliver a clock signal, based on a common time base for communication mode and standby mode, from a first reference signal and a second reference signal.

[0046] This makes it possible to obtain a single time base for sleep and communication modes and to reduce energy consumption by reducing the use of software solutions for example.

[0047] Figure 2 represents the radio frequency communication device 100 according to one embodiment. More particularly, Figure 2 represents the architecture of block 106.

[0048] In the example shown, block 106 includes an NFrco node connecting block 102, or for example another block 210 (RCO32k) for providing a configurable clock signal (LSI), to a block 224 (2 Edges Process). Block 224 receives the signal from blocks 102 or 210, whose main frequency is denoted Frco, and then doubles this frequency, resulting in a frequency denoted 2Frco at the output of an N2Frco node of block 224. Block 224, for example, is included in block 106. The N2Frco node is connected, preferably connected, to a clock input of a register 218 (Register) and to a clock input of a counter 220 (32k counter) via a two-way switch 230. The switch 230 is configured to connect, in standby mode, the clock input of block 224 to register 218 and to counter 220 and, in communication mode, block 107 to the clock input of register 218 and to the clock input of counter 220.For example, switch 230 is controlled by block 110.

[0049] The 220 counter is for example of a size of 12 to 29 bits, for example 22 bits which covers a period called "advertising" of the BLUETOOTH® LOW ENERGY protocol of a duration of 128 seconds.

[0050] In one example, the counter 220 and / or the register 218 form a loop accumulator configured to be reset when the counter reaches a value equal to the ratio between a frequency of the communication mode clock signal (Active clock) and the frequency of the clock signal to be obtained.

[0051] In the example shown, block 106 further includes a calibration unit 204 (Calibration) which takes as input the clock signal (HSE) from block 104, as well as a parameter (W) corresponding to a given number of periods of the signal (LSE, LSI) from blocks 102 or 210. The calibration unit 204 starts, for example, when it receives a start signal (Start). The calibration unit 204 is configured, for example, to output a standby mode parameter (Mcalib) corresponding to a number of periods of the signal (HSE) from block 104 for the number W of periods of the signal from block 102 or 210 (LSE, LSI).

[0052] In the example shown, register 218 has a connected output, preferably connected to a modulo 202 function calculator circuit. The modulo 202 function calculator circuit is configured to provide on an output the result (R) of a modulo function between a current value (in) of the register and a comparison parameter (D) associated with the number W. The modulo operation is a binary operation that associates to two natural numbers the remainder of the Euclidean division of the first by the second.

[0053] The comparison parameter D is for example equal to 2000 times the number W for a frequency to be obtained of 32 kHz.

[0054] If the current value in of register 218 is greater than or equal to the comparison parameter D then the modulo function calculation circuit 202 is configured to send a control signal (En) to counter 220 which causes an increment of counter 220.

[0055] In the example shown, register 218 receives as input the data present at node M to which the result R is added. This addition is for example carried out with an adder circuit 214 connecting the output R of circuit 202, node M and the input of register 218.

[0056] The calibration unit 204 is connected, preferably linked, to the node M via a two-way switch 234. The switch 234 is, for example, controlled by the block 110. The two-way switch 234 is controlled so that, in communication mode (Active mode), a parameter of the communication mode (Mactive) is available on the node M and that, in standby mode, the standby mode parameter (Mcalib) is available on the node M.

[0057] In the example shown, the time base that we seek to obtain can serve as a basis for generating a clock signal with a center frequency of 32 kHz, which can be used, for example, for the BLUETOOTH® protocol. In this example, W is chosen, for example, from the values ​​32, 64, or 128; the output frequency of block 104 is 32 MHz; that of blocks 210 or 102 is 32.768 kHz; and the frequency from block 107 is 4 MHz.

[0058] The value available at node M can also be imposed, for example by block 110, depending on the transition from standby mode to communication mode or vice versa, and / or depending on the number of periods of the 2Frco signal after detection of the transition between standby and communication modes. For example, the value available at node M is set to zero between the second rising edge of the 2Frco signal following detection of the transition to communication mode and the first rising edge of the signal from block 107 (Active Clock). Then, the Mactive value, and therefore the value available at node M, is set, for example, to 2048, which corresponds to the value of the comparison parameter D, for example 256000 for a W value of 128, divided by the ratio between the frequency of the signal from block 107 and the frequency of the signal from block 107. 107 (4 MHz) by the desired frequency (32 kHz). When standby mode is implemented, the value available at node M is the Mcalib value from calibration circuit 204.

[0059] In an example where the signal from block 102 is used in standby mode, and the desired final frequency is 32 kHz, M is established at 32 x 106 x • H. It follows that M = x 32jt = = 312504- and D = 640004, where k = 1, 2, 4.

[0060] In an example where the accuracy of the signal from block 102 is better than that of block 107 then M is for example imposed at a value of 31250.

[0061] The value available at node M is, in the example shown, directly usable by the circuit 110 as soon as it is calculated by the calibration circuit 204.

[0062] In the example shown, the values ​​of counter 220 and register 218 respectively give the integer and decimal parts of the time base (TB) used to generate the desired clock signal. In this example, the integer part of the time base is coded on 22 bits and the decimal part is coded on 7 bits.

[0063] A person skilled in the art can use their knowledge to generate a clock signal from the generated time base. The implementation of [Fig. 2] allows the values ​​of the BLUETOOTH® LOW ENERGY protocol events, expressed with a resolution of 0.625 ms, to be used directly without processing.

[0064] The same time base TB is used for both modes, which eliminates the need for software calculations.

[0065] Figure 3 shows a timing diagram of an operating mode of the radio frequency communication device of Figure 2. More specifically, the 2Frco signal is shown, as well as the (Active mode) signal representing the mode in which the device is operating (low state: standby mode is engaged; high state: communication mode is active), the values ​​of counter 220 (32 kHz counter), and the signal from block 107 (4 MHz counter wrap-around) which activates the accumulator loop (the accumulator loops back on each rising edge). In the example shown, the seven most significant bits of the accumulator are illustrated.

[0066] Before a time tl, the value of counter 220 is at a number N, the standby mode is engaged, and the seven most significant bits of the accumulator correspond to a value for example of 56.

[0067] At time t1, the signal 2Frco expresses a rising edge, a time t2 corresponds to a rising edge of the following period and a time t3 corresponds to a rising edge of yet another subsequent period. From time t1 until time t3 the value of the Counter 220 is at N+1. Between time t1 and a time t2 when the device switches from standby mode to communication mode, the seven most significant bits of the accumulator correspond to a value of, for example, 10.

[0068] Between time t2 and time t3, the seven most significant bits of the accumulator correspond to a value for example of 88.

[0069] From time t3 until time t4, corresponding to the first rising edge of the signal linked to the accumulator loop, the value at node M is set to zero, meaning the counter is not incremented and remains at N+1. Furthermore, the seven most significant bits of the accumulator are incremented from 88 to 124. The value 124 corresponds to the division of the 4 MHz clock signal from block 107 by the frequency of the desired signal.

[0070] From time t4, which corresponds to a rising edge of the signal from block 107, the seven most significant bits of the accumulator return to 0 and then increment up to 124 at a time t5 while the counter 220 increments at N+2. The value present at node M is, from time t4, set to 2048 for example.

[0071] From time t5, which corresponds to a rising edge of the signal from block 107, the seven most significant bits of the accumulator return to 0 and then increment up to 124 while the counter 220 increments to N+3 and so on until the next mode change.

[0072] Implementing a programmable loopback equal to the longest time interval that must be implemented in the communication protocol simplifies the device. The generated events are thus synchronized with each other, thereby avoiding event collisions by design. The event dates remain unchanged during loopbacks. In the example of the BLUETOOTH® LOW ENERGY protocol, the events are periodic, and once the events are set up, they can be automatically rescheduled unless deactivated. Finally, concurrent modes can be easily implemented.

[0073] Figure 4 shows a timing diagram of another operating mode of the radio frequency communication device of Figure 2. The example in Figure 4 shows the same signals and values ​​as the example in Figure 3, but the example shown in Figure 4 illustrates the transition from communication mode (Active mode) to standby mode.

[0074] At a time t' 1, which corresponds to a rising edge of the signal (4 Mhz counter wrap around) from block 107, the counter 220 (32kHz counter) is incremented to go from a value Nl to a value N and the seven most significant bits of the accumulator are incremented from 0 up to a time t'2.

[0075] Shortly after time t' 1 a rising edge of the 2Frco signal occurs.

[0076] At a time t'la, subsequent to time t'1 and occurring before time t'2, the mode switches from communication mode to standby mode.

[0077] At time t'2, which corresponds to a rising edge of the 2Frco signal following the transition from communication mode to standby mode, the signal from block 107 is replaced by the 2Frco signal by the action of switch 230. The value on node M is also changed to Mcalib. At time t'2, the seven most significant bits of the accumulator have, for example, a value of 101.

[0078] Between time t'2 and a time t'3 which corresponds to the next rising edge of the 2Frco signal, the seven most significant bits of the accumulator are incremented and then remain stable at 102. The value of the counter 220 remains at N until time t'3.

[0079] At time t'3, the value of counter 220 is incremented by one and the seven most significant bits of the accumulator have, for example, a value of 56.

[0080] Figure 5 presents a summary table of one operating mode of the radio frequency communication device of Figure 2. More specifically, the table shows the counter value after successive clock cycles of the 2Frco signal and the lead relative to the theoretical signal that is to be obtained in standby mode. The values ​​in, R, and the result of the calculation in>D are also shown. In the example presented, the signal to be obtained is at 32 kHz, the Frco frequency is 20 kHz, and W=64, which gives M=102400 and D=128000.

[0081] The lead relative to the clock signal that we wish to obtain (of frequency called Fnom) is defined by the following equation:

[0082] [Math.l] Advance = (D -Reg J / D*l / Fnom

[0083] being the Reg value of the register of the previous line.

[0084] During a reset, all values ​​are zero.

[0085] After the first rising edge of the 2Frco signal, in is at 102400, Reg is at 1024000, the result of the calculation in>D is at 0, the value of the counter is at 0 and the advance is zero.

[0086] After the second rising edge of the 2Frco signal, in is at 204800, Reg is at 76800 (=in-D), the result of the calculation in>D is 1, so the value of the counter is incremented to 1 and the advance is calculated at 6.25 ps.

[0087] After the third rising edge of the 2Frco signal, in is at 179200 (=102400+76800), Reg is at 51200 (=179200-128000), the result of the calculation in>D is 1, so the value of the counter is incremented to 2 and the advance is calculated to be 12.5 ps.

[0088] After the fourth rising edge of the 2Frco signal, in is at 153600, Reg is at 25600 (=153600-128000), the result of the calculation in>D is 1, so the value of the counter is incremented to 3 and the advance is calculated to be 18.75 ps.

[0089] After the fifth rising edge of the 2Frco signal, in is at 128000, Reg is at 0 (=128000-128000), the result of the calculation in>D is 1, the value of the counter is therefore incremented to 4 and the advance is calculated at 25 ps.

[0090] After the sixth rising edge of the 2Frco signal, in is at 102400, Reg is at 102400, the result of the calculation in>D is 0, so the value of the counter is not incremented and the advance is calculated at 0 ps.

[0091] After the seventh rising edge of the 2Frco signal, in is at 204800, Reg is at 76800, the result of the calculation in>D is 1, so the value of the counter is incremented to 5 and the advance is calculated to 6.25 ps.

[0092] Fig. 6 represents a summary table of another operating mode of the radio frequency communication device of Fig. 2.

[0093] In particular, the table in [Fig.6] shows the same values ​​as the table in [Fig.5] except that in the example shown in [Fig.6], the signal we are trying to obtain is at 32 kHz, the frequency Frco is 40 kHz, W=64, which gives M=51200 and D=128000.

[0094] During a reset, all values ​​are set to zero.

[0095] After the first rising edge of the 2Frco signal, in is at 51200, Reg is at 51200, the result of the calculation in>D is at 0, the value of the counter is at 0 and the advance is zero.

[0096] After the second rising edge of the 2Frco signal, in is at 102400, Reg is at 102400, the result of the calculation in>D is 0, so the value of the counter is not incremented and the advance is calculated at 12.5 ps.

[0097] After the third rising edge of the 2Frco signal, in is at 153600, Reg is at 25600, the result of the calculation in>D is 1, so the value of the counter is incremented to 1 and the advance is calculated at 6.25 ps.

[0098] After the fourth rising edge of the 2Frco signal, in is at 76800, Reg is at 76800, the result of the calculation in>D is 0, the value of the counter is therefore not incremented and the advance is calculated at 37.5 ps.

[0099] After the fifth rising edge of the 2Frco signal, in is at 128000, Reg is at 0 (=128000-128000), the result of the calculation in>D is 1, so the value of the counter is incremented to 2 and the advance is calculated to 12.5 ps.

[0100] After the sixth rising edge of the 2Frco signal, in is at 51200, Reg is at 51200, the result of the calculation in>D is 0, so the value of the counter is not incremented and the advance is calculated at 62.5 ps.

[0101] After the seventh rising edge of the 2Frco signal, in is at 102400, Reg is at 102400, the result of the calculation in>D is 0, so the value of the counter is not incremented and the advance is calculated at 75 ps.

[0102] After the eighth rising edge of the 2Frco signal, in is at 153600, Reg is at 25600, the result of the calculation in>D is 0, so the value of the counter is incremented to 75 and the advance is calculated to be 6.25 ps.

[0103] In the examples in Figures 2, 5 and 6, the transition of the 220 counter takes place in advance of the clock signal that we want to obtain because the value 2Frco is always greater than 32 kHz if Frco is between 16 and 60 kHz.

[0104] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0105] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, with regard to the frequencies generated by blocks 102 or 210, which can be designed to generate frequencies other than 32768 kHz or 32 kHz. Furthermore, the device in [Fig. 2] can be used to generate other time bases to obtain clock signals other than 32 kHz.

Claims

Claims

1. Radiofrequency communication device (100) comprising a clock signal generator (106) configured to deliver a clock signal, based on a time base common to a communication mode and a standby mode, from a first reference signal (LSE,LSI) and a second reference signal (HSE).

2. Device (100) according to claim 1, wherein the clock signal generator (106) comprises an accumulator circuit configured to: - in the communication mode, be driven by a communication mode clock signal (Active clock) from the second reference signal (HSE), and be incremented according to a parameter of the communication mode (Mactive); and - in the standby mode, be driven by a standby mode clock signal (2Frco) from the first reference signal (LSI,LSE), and be incremented according to a parameter of the standby mode (Mcalib).

3. Device (100) according to claim 2, wherein the clock signal generator comprises a calibration circuit (204) configured to output a number of periods of the second reference signal (HSE) during a given number (W) of periods of the first reference signal (LSE, LSI); the output of the calibration circuit giving a possible value of the sleep mode parameter (Mcalib).

4. Device (100) according to claim 3, wherein the accumulator circuit comprises a modulo function calculation circuit (202) and a register (218), the modulo function calculation circuit being configured to implement a modulo function between a current value (in) of said register and a comparison parameter (D) associated with said given number (W) of periods of the first reference signal (LSE, LSI), the register being configured to: - in the communication mode, be driven by the communication mode clock signal (Active Clock) and receive as input said communication mode parameter (Mactive) to which is added an output result (R) of the modulo function calculation circuit; and - in the standby mode, be driven by a standby mode clock signal (2Frco) proportional to the first reference signal (LES, LSI), and receive as input said sleep mode parameter (Mcalib) to which is added the output result (R) of the modulo function calculation circuit (202).

5. Device (100) according to claim 4, wherein the accumulator circuit comprises a counter (220) configured to: - in the communication mode, be driven by the communication mode clock signal (Active clock) and by a control signal (En) depending on a comparison between the current value (in) of the register (218) and the comparison parameter (D); and - in the standby mode, be driven by the standby mode clock signal (2Frco) and by said control signal (En).

6. Device (100) according to claim 5, wherein the counter is configured to increment when the current value (in) of the register is greater than the comparison parameter (D).

7. Device (100) according to any one of claims 2 to 6, wherein the accumulator comprises a loop counter configured to be reset to zero when it reaches a value equal to the ratio between a frequency of the communication mode clock signal (Active Clock) and the frequency of the clock signal to be obtained.

8. A device (100) according to any one of claims 5 to 7, wherein the counter comprises a shift register.

9. Device (100) according to any one of claims 2 to 8, wherein the value of said communication mode parameter (Mactive) and / or said standby mode parameter (Mcalib) is imposed.

10. Device (100) according to claim 9, in which the communication mode parameter (Mactive) is set to zero when switching between the standby mode and the communication mode.

11. Device (100) according to claim 9 or 10 in its dependence on claim 4, in which the parameter of the communication mode (Mactive) is imposed, in the communication mode, at the value of the comparison parameter (D) divided by the ratio between the frequency of the communication mode clock signal (Active clock) and the frequency of the clock signal to be obtained.

12. Device (100) according to any one of claims 9 to 11, wherein the sleep mode parameter (Mcalib) is imposed at an initial value equal to 1000 times the number (W) of periods of the first reference signal (LSE, LSI).

13. Device (100) according to any one of claims 2 to 12, in in which the sleep mode clock signal (2Frco) has a frequency equal to twice the frequency of the first reference signal (LSI,LSE).

14. Device (100) according to any one of claims 1 to 13, wherein the frequency of the clock signal to be obtained is 32 kHz, the frequency of the communication mode clock signal (Active clock) is 4 MHz, and the frequency of the second reference signal (HSE) is 32 MHz, and the frequency of the first reference signal (LSE) is between 16 and 60 kHz.

15. Device (100) according to claim 14 in its dependence on claim 4, in which the comparison parameter (D) is equal to 2000 times the number (W) of periods of the first reference signal (LSE, LSI), and the number (W) of periods of the first reference signal (LSE, LSI) is chosen between 32, 64 and 128.

16. Device (100) according to any one of claims 5 to 15, in which the values ​​of the counter (220) and those of the register (218) respectively give the integer part and the decimal part of the time base.

17. Device (100) according to any one of claims 1 to 16, wherein the first (LSE,LSI) and second reference signals (HSE) have different frequency accuracies.

18. Device (100) according to any one of claims 1 to 17, wherein the device (100) is of the BLUETOOTH®, BLUETOOTH® LOW ENERGY, or IEEE 802.15.4 type.

Images