Architecture of a non-volatile memory

Abstract

Architecture of a non-volatile memory This description concerns a non-volatile memory (200) comprising: - a first area (202) comprising a first plurality of storage elements configured to store values ​​associated with a first plurality of neurons of a network; - a second area (202') comprising a second plurality of storage elements; - a control circuit (208), configured to apply, to a plurality of first read paths, one or more first input values, each first read path comprising one of the storage elements of the first plurality of elements; - a calculation circuit (212_1) configured to add currents supplied by the first paths to generate an output current;and a programming circuit configured to convert the output current into programming current, and to program a storage element of the second plurality of elements using said programming current. Figure for the abbreviation: Fig. 2;

Description

Title of the invention: Architecture of a non-volatile memory Technical field

[0001] The present description relates generally to non-volatile memories configured to perform calculations. In particular, the present description relates to a non-volatile memory configured to perform calculations between several layers of an artificial neural network. Prior art

[0002] The operation of neural networks generally requires the execution, by a processor, of advanced algorithms. The calculations, such as convolutions and / or matrix calculations, ordered during the execution of the algorithms then involve data transfers between a non-volatile and / or volatile memory and the processor. The transferred data are, for example, parameters of the neural network, such as weights. The intermediate results between successive calculations are, for example, stored temporarily in a volatile memory.

[0003] Each data transfer between the non-volatile memory and / or the volatile memory and the processor is costly in terms of time and energy consumption. This leads, for example, to latency times in the data processing by the neural network, as well as reduced performance in the data processing.

[0004] There is a need to improve the execution of controlled calculations when processing data by an artificial neural network. Summary of the invention

[0005] One embodiment provides a non-volatile memory comprising: - a first area comprising a first plurality of storage elements, configured to store weight values ​​associated with a first plurality of neurons of a neural network; - a second zone comprising a second plurality of storage elements; - a control circuit, configured to apply, to a plurality of first reading paths, one or more first input values, each first reading path comprising one of the storage elements of the first plurality of storage elements; - a first calculation circuit configured to add currents supplied by the first reading paths to generate a first output current; and - a programming circuit configured to convert the first output current into a first programming current, and to program a first storage element of the second plurality of storage elements using said first programming current.

[0006] According to one embodiment, the control circuit is further configured to apply, to a plurality of second read paths, one or more second input values ​​generated by reading the first of the second plurality of storage elements, each second read path comprising one of the storage elements of the first plurality of storage elements, the non-volatile memory further comprising - a second calculation circuit, configured to add currents supplied by the second reading paths to generate a second output current, the programming circuit being configured to convert the second output current into a second programming current, and to program another storage element of the first area of ​​the memory using said second programming current.

[0007] According to one embodiment, the control circuit is further configured to apply, to a plurality of third reading paths, one or more third input values ​​generated by reading the other storage element of the first area, each third reading path comprising one of the storage elements of the first plurality of storage elements, and wherein the first calculation circuit is further configured to add currents provided by the third reading paths to generate a third output current, the programming circuit being further configured to convert the third output current into a third programming current, and to reprogram the first storage element of the second plurality of storage elements using said third programming current.

[0008] According to one embodiment, the storage elements included in the first reading paths define the weights associated with an input layer of the neural network and in which the storage elements included in the third reading paths define the weights associated with another layer, or with an output layer, of the neural network.

[0009] According to one embodiment, the weights stored by the first plurality of storage elements define weights of neurons belonging to layers of odd parity, respectively of even parity, of the neural network and the weights stored by the second plurality of storage elements define weights of neurons belonging to layers of even parity, respectively of odd parity, of the neural network.

[0010] According to one embodiment, each storage element, among the first and second plurality of storage elements, belongs to a memory cell, each memory cell being connected to the control circuit via a line of word and a bit line, the control circuit being configured to enable or disable word lines and bit lines.

[0011] According to one embodiment, the first calculation circuit is configured to generate the first output value, based on the currents provided by the memory cells included in a read path among the first read paths.

[0012] According to one embodiment, the calculation circuit is further configured to apply compensation and / or threshold and / or offset and / or scaling effects, based on the currents provided by the memory cells included in a read path among the first read paths.

[0013] According to one embodiment, the storage elements and the other storage elements are programmable resistive elements.

[0014] According to one embodiment, the above memory further comprises a third calculation circuit configured to generate another output value, on the basis of currents supplied by one or more memory cells included in a reading path among the first reading paths and one or more first input values.

[0015] According to one embodiment, the first and third computation circuits are configured to generate the output values ​​based on one or more common cells in the plurality of first read paths, the common cells being duplicated in at least two sub-areas in the first area.

[0016] One embodiment provides a method comprising: - applying, by a control circuit to a plurality of first reading paths, one or more first input values, each first reading path comprising one of a first plurality of storage elements of a first area of ​​a non-volatile memory, the first plurality of storage elements being configured to store weight values ​​associated with a first plurality of neurons of a neural network; - adding, by a first calculation circuit, currents supplied by the first reading paths to generate a first output current; - converting, by a programming circuit, the first output current into a first programming current, and programming, by the programming circuit, a first storage element of a second plurality of storage elements of a second area of ​​the non-volatile memory using said first programming current.

[0017] According to one embodiment, the above method further comprises: - applying, by the control circuit to a plurality of second read paths, one or more second input values ​​generated by reading the first of the second plurality of storage elements, each second read path comprising one of the storage elements of the first plurality of storage elements, - adding, by a second calculation circuit, currents supplied by the second reading paths to generate a second output current; - converting, by the programming circuit, the second output current into a second programming current, and programming, by the programming circuit, another storage element of the first area of ​​the memory using said second programming current. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] schematically illustrates an artificial neural network and represents an example of operations performed by the artificial neural network;

[0020] [Fig.2] is a block diagram illustrating a non-volatile memory, according to an embodiment of the present description;

[0021] [Fig.3] illustrates a portion of the non-volatile memory, according to an embodiment of the present description;

[0022] [Fig.4] is a diagram illustrating a plurality of neurons implemented directly in the non-volatile memory, according to an embodiment of the present description;

[0023] [Fig.5A] illustrates calculations performed between a first and a second layer of the neural network, according to an embodiment of the present description;

[0024] [Fig.5B] illustrates calculations performed between the second and a third layer of the neural network, according to an embodiment of the present description;

[0025] [Fig.6] is a block diagram illustrating another non-volatile memory, according to an embodiment of the present disclosure;

[0026] [Fig.7A] illustrates calculations performed between the first and second layers of the neural network, according to an embodiment of the present description; and

[0027] [Fig.7B] illustrates calculations performed between the second and third layers of the neural network, according to an embodiment of the present description. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the pro- programming of resistive elements is known and within the reach of the person skilled in the art.

[0030] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when we refer to two elements connected (in English "coupled") between them, it means that these two elements can be connected or be linked by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "approximately", "sen "possibly", and "of the order of" mean within 10%, preferably within 5%.

[0033] [Fig.l] schematically illustrates an artificial neural network 100 and represents an example of operations performed by the artificial neural network 100.

[0034] The artificial neural network 100 comprises, for example, a layer 102 (LAYER A), a layer 104 (LAYER B) and a layer 106 (LAYER C). By way of example, the layers 102 and 106 are respectively an input layer and an output layer of the neural network 100. In the illustrated example, the layer 102 comprises four artificial neurons 108, 110, 112 and 114 respectively associated with weights A1, A2, A3 and A4. The layer 104 comprises three artificial neurons 116, 118 and 120 respectively associated with weights B1, B2 and B3. The layer 106 comprises three neurons 122, 124 and 126 respectively associated with weights C1, C2 and C3.

[0035] As an example, an input vector 128 is provided to the layer 102 of the neural network 100. The neural network 100 is then configured to generate an output vector 130 based on the input vector 128. As an example, the input vector 128 comprises data relating to an image, a video, or an audio track. As an example, the output vector 130 comprises, for example, probabilities of membership, of a target belonging to the image or the video, to categories, etc. In another example, the neural network 100 is configured to perform speech recognition, language processing, speech-to-text or text-to-speech conversion, translation, etc., based on an audio track.

[0036] In the example illustrated by Figure 1, the input vector 128 comprises four input values ​​INI, IN2, IN3 and IN4. As an example, the layer 102 is configured to perform a linear operation between the input vector 128 and the weights A1 to A4. As an example, the input value INI is provided to the neuron 104, configured to perform the multiplication A1 x INI. Similarly, each of the input values ​​IN2, IN3 or IN4 is provided to the neuron of weight A2, A3 or A4 corresponding and which is configured to generate the corresponding value IN'2= A2 x IN2, IN'3= A3 x IN3 or IN'4= A4 x IN4.

[0037] For example, neuron 108 is configured to transmit the value IN' 1 = A1 x INI to neurons 116 and 120 of layer 104. For example, neuron 116 also receives the values ​​IN'2 = A2 x IN2 and IN'3 = A3 x IN3. Neuron 116 is configured to generate a value IN” 1 = B1 x (IN' 1 + IN'2 + IN'3) and, for example, to transmit it to neuron 122 of layer 106.

[0038] In the example illustrated by FIG. 1, the neuron 120 is configured to generate a value IN” 3 based on the values ​​provided by the neurons 108 and 114. For example, the value IN”3 is equal to the linear combination B3 x (IN' l + IN'4). The neuron 120 is, for example, further configured to provide the value IN” 3 to the neurons 122, 124 and 126 of the layer 106.

[0039] In the example illustrated by Figure 1, the neuron 122 is configured to generate an output value 01. The output value is for example a component of the output vector 130. For example, the value 01 is equal to the linear combination Cl x (IN” 1 + IN” 2 + IN” 3), where the value IN” 2 is the value generated by the neuron 118, for example on the basis of the values ​​IN' 2 and IN' 3 and the weights B2 and B3. Similarly, the neurons 124 and 126 are respectively configured to generate output values ​​02 and 03, on the basis of the weights C2 and C3 and the values ​​IN' ' 1 to IN” 3 provided to them.

[0040] The artificial neural network 100 is therefore, for example, configured to perform operations of the multiply and add type (in English “Multiply and Accumulate” - MAC).

[0041] According to one embodiment, to avoid transfer times between a non-volatile memory storing the weights of the neurons, a volatile memory storing, for example, intermediate results such as the values ​​IN' 1 to IN'4 and IN' ' 1 to IN” 3 and a processor configured to perform the MAC operations, the MAC operations are directly performed in the non-volatile memory (in English “In Memory Computing” - IMC).

[0042] [Fig. 2] is a block diagram illustrating a non-volatile memory 200. For example, the non-volatile memory 200 implements a neural network similar to the neural network 100. For example, the neural network implemented in the non-volatile memory 200 is a convolutional neural network (CNN), a fully connected neural network (FCN), etc. For example, the neural network implemented in the non-volatile memory 200 is relatively small, comprising for example around ten layers.

[0043] According to one embodiment, the non-volatile memory 200 comprises two areas 202 (HALF-ARRAY 1) and 202' (HALF-ARRAY 2). The areas 202 and 202' each comprise, for example, a matrix of memory cells 203 and 203' (BITCELL ARRAY). By way of example, the memory cell matrices 203 and 203' each comprise a plurality of memory cells, or storage elements, addressable in rows and columns and via word lines and bit lines. The areas 202 and 202' each comprise a column decoder 204 and 204' (COLUMN DECODERS) and a row decoder 206 and 206' (WL DECODEURS). Each memory cell of matrices 203 and 203' is then addressable via decoders 204 and 206, and 204' and 206'. For example, each memory cell implements a neuron of neural network 100.

[0044] The memory 200 further comprises a control circuit 208 (CTRL CIRCUIT) configured to control, via a digital circuit 210 (DIGITAL CTRL), the decoders 204, 206, 204' and 206'. Following the control of the control circuit 208, the decoders 204 and 206, 204' and 206' then activate reading paths, comprising a memory cell, in the matrix 203 or 203'. A reading path corresponds, for example, to a synapse supplying a neuron, each neuron generally being supplied by several synapses.

[0045] According to one embodiment, the memory 200 further comprises at least one calculation circuit 212 (IMC). Although [Fig. 2] illustrates three circuits 212, the memory 200 may of course comprise a greater or lesser number of calculation circuits 212. In some cases, the memory 200 comprises a plurality of calculation circuits 212. Each circuit 212 is connected to a set of at least one read path in the matrix 203 and is configured to perform one or more calculations based on the intensity of the current at the output of all the read paths. Each calculation circuit 212 is further configured to generate a value, based on the currents at the output of all the read paths. Each calculation circuit 212 is further connected to another storage element (not illustrated in [Fig. 2]) included in the area 202' and is configured to store the generated value therein.Similarly, each circuit 212 is connected to a set of at least one read path in the matrix 203' and is configured to perform one or more calculations based on the intensity of the current at the output of the set of read paths.

[0046] As an example, the memory 200 is placed, by the control circuit 208, in operating modes among three operating modes. A calculation mode allows the memory to supply one or more reading paths and allows the calculation circuits 212 to perform one or more calculations. A programming mode allows the memory to program resistive elements (not illustrated in [Fig. 2]) following one or more calculations, by the calculation circuits 212. A reading mode allows the reading of the values ​​programmed in the resistive elements included in the memory 200.

[0047] Similarly, the non-volatile memory 200 comprises other calculation circuits 212, each connected to a set of read paths in the matrix 203'. These calculation circuits 212 are, in addition, configured to generate values ​​on the basis of the output currents of the set of read paths, and to store these values ​​in other storage elements (not illustrated in [Fig. 2]) included in the area 202.

[0048] Each matrix 203 and 203' comprises memory cells representing neurons of several layers of the neural network. In particular, each matrix 203 and 203' comprises neurons of layers of the same parity. In other words, if the matrix 203 comprises the neurons of the input layer, for example layer 102, i.e. the first layer, of the neural network 100, it also comprises the neurons of the third layer, for example layer 106, etc. of the neural network 100. The matrix 203 then comprises the second layer of the network, for example layer 104, and any other layer of even parity if there is one. In another example, the neurons of the input layer are included in the matrix 203'.

[0049] By way of example, the neural network implemented by the memory 200 is a network of relatively small size, comprising, for example, around ten layers, and for example comprising a total of at least 3 layers and at most 10 layers.

[0050] [Fig. 3] illustrates a portion of the non-volatile memory 200, according to an embodiment of the present description. In particular, [Fig. 3] illustrates in more detail a set of read paths 300, included in the matrix 203 and connected to a calculation circuit 212.

[0051] By way of example, the set of read paths 300 comprises resistive elements 302, 304 and 306 of different resistances encoding the weights of three neurons of a layer of the neural network. Each resistive element 302, 304 and 306 is respectively connected by its electrodes to the source, or to the drain, of a transistor 308, 310 and 312 and to a bit line BL1, BL2 and BL3 to which a read voltage (READ VOLT.) is applied. The resistive elements 302, 304 and 306 are for example respectively powered by the bit lines BL1, BL2 and BL3, via the read voltage. The transistors 308, 310 and 312 each have their gate respectively connected to a word line WL1, WL2 and WL3. Transistors 308, 310 and 312 are further connected to ground (GND) by their drain or source. For example, word lines WL1, WL2 and WL3 are distinct from each other.In another example, at least two resistive elements 302, 304 or 306 are connected to the same word line. The control circuit 208 is for example configured to control, via the digital circuit 210, the power supply of the word lines WL1, WL2. and WL3. For example, to control the power supply of the word lines, the control circuit 208 places the memory 200 in a calculation mode.

[0052] The control circuit 208 is further configured, via the digital circuit 210 and the decoder 206, to supply the output current of each resistive element 302, 304 and 306 to one of the calculation circuits 212. The calculation circuit 212 is for example configured to generate a current as a function of the output currents of the elements 302, 304 and 306. For example, the current generated by the circuit 212 is a function of a sum of the output currents of the elements 302, 304 and 306. For example, the calculation circuit 212 further comprises a current amplifier configured to amplify the sum of the output currents of the elements 302, 304 and 306. For example, the calculation circuit 212 is further configured to apply compensation and / or threshold and / or offset and / or scaling, based on the output currents of elements 302, 304 and 306.

[0053] The calculation circuit 212 is for example configured to supply the generated current to a programming circuit 313 (PROG. PATH). The programming circuit is, for example, included in the zone 202'.

[0054] For example, the programming circuit 313 comprises a current generator 314 (CURRENT GENERATOR). For example, a reference current value of the current generator 314 is equal to, or a function of, the current provided by the calculation circuit 212.

[0055] The programming circuit 313 further comprises, for example, a current mirror 316 (CURRENT MIRROR). For example, the current mirror 316 is connected to the current generator 314 and is configured to duplicate the current output from the current generator 314.

[0056] In other embodiments, circuit 314 is omitted, for example if current mirror 316 is configured to apply a gain between the current provided by computation circuit 212 and the current provided to storage element 318.

[0057] The current mirror 316 is further connected to another resistive element 318 and is configured to program this other resistive element 318 to a resistance value based on the current generated by the calculation circuit 212. For example, the current generator 314 is configured to generate a programming current based on the current provided by the calculation circuit 212. By way of example, the resistive element 318 is a multiple reprogrammable element, and the programming circuit 313 is configured to reprogram the resistive element 318 from a current resistance value to the new resistance value based on the programming current.

[0058] The resistive element 318 is connected by one of its electrodes to a reference voltage (HV VOLT.) and, by the other of its electrodes, to the source, or to the drain, of a transistor 320. By way of example, the reference voltage is applied to the resistive element 318 only when the control circuit 208 is in a programming state. The transistor 320 is for example connected to ground by its drain, or its source, and its gate is for example connected to a word line WL'. The word line WL' is for example controlled by the decoder 204'. The column decoder 206' is for example configured to select the correct column to be connected to the current mirror 316. The column decoder 206' is further configured to select the path connecting the cells.

[0059] The value to which the resistive element 318 is programmed corresponds for example to an input value for the next layer of the neural network. For example, in relation to [Fig.l], the resistive elements 302, 304 and 306 program, respectively, the weights of the neurons 108, 110 and 112.The bit lines BL1, BL2 and BL3 then provide, respectively, a current II, I2 and I3, depending on the states of the transistors 308, 310 and 312 and the resistive elements 302, 304 and 306. The set of reading paths 300 then corresponds to the combination of the neurons 108, 110 and 112 connected to the neuron 116 of the layer 104. The calculation circuit 212 is then, for example, configured to perform the layer operation between the layers 102 and 104. For example, the layer operation corresponds to the sum of the weight-input value products for the neurons 108, 110 and 112. The current generated by the calculation circuit encodes the input value IN' 1 + IN' 2 + IN' 3. The resistive element 318 is therefore configured to temporarily store the input value of the neuron 116 of the layer 104.In another example, the resistive elements 302, 304 and 306 encode, respectively, the weights of the neurons 116, 118 and 120 and the calculation circuit 212 is configured to generate a value corresponding to the value IN' ' 1+IN' '2+IN”3. For example, the calculation circuit 212 is a node connecting the bit lines of each reading path. In other cases, the calculation circuit 212 integrates other functions which modify the sum of the output currents of all the reading paths 300. The resistive element 318 is then configured to store the input value of neuron 122 of the layer 106.

[0060] The memory 200 therefore comprises a plurality of sets of reading paths, similar to the set 300, although the number of resistive elements differs from set of paths to another. Each set of paths is for example connected to a calculation circuit 212. Each circuit 212 is configured to provide a current used for programming a value, corresponding to an input value for one or more neurons of the following layer, in a resistive element similar to the element 318.

[0061] The value programmed in element 318 is supplied, in the form of current generated via current mirror 316 and current generator 314 to matrix 203' of [Fig.2], under the control of decoders 204' and by activating one or more word lines of matrix 203'.

[0062] [Fig. 4] is a diagram illustrating a plurality of neurons implemented directly in the non-volatile memory. In particular, [Fig. 4] illustrates an example of the structure of matrices 203 and 203'.

[0063] Each of the matrices 203 and 203' comprises a plurality of memory cells 400 addressable in rows and columns. All cells of the same row of the matrix 203 or 203' are for example connected to the same word line (WL1,..., WLN), N being an integer equal to the number of word lines, controlled by the decoder 204 or 204'. Similarly, all cells of the same column of the matrix 203 or 203' are connected to the same bit line (BL1, BL2, etc.) controlled by the decoder 206 or 206'. The decoders 206 or 206' are themselves connected to one or more calculation circuits 212.

[0064] The memory cells 400 each comprise a resistive element, similar to the resistive elements 302, 304 and 306 described in relation to [Fig. 3]. The resistive element of each cell 400 is connected by its electrodes to a bit line and to the source, or to the drain, of a transistor, similar to the transistors 308, 310 and 312 described in relation to [Fig. 3]. Each transistor is further connected to ground by its drain, or its source and is activated via its gate by the activation of one of the word lines.

[0065] Thus, when the control circuit 208 commands, for example, the activation of the word line WL1 and WL2 and the supply of the bit line BL2, memory cells 402 and 404, located in the first and second lines of the second column of the matrix 203 or 203' are supplied. The cells 402 and 404 then form, for example, a set of reading paths. By way of example, in relation to [Fig.l], the cells 402 and 404 form the set comprising the neurons 116 and 118 and supplying the values ​​IN”2 and IN”3 to the neuron 122 of the layer 106.

[0066] The person skilled in the art will know how to organize the memory cells of the matrices 203 and 203' so that the activation of the word and bit lines properly powers the desired memory cells. Indeed, for example, in order to power the cell on the first row and first column and the cell on the second row, second column, the word lines WL1 and WL2, as well as the bit lines BL1 and BL2 will be activated. Consequently, the cells on the first row, second column, and on the second row, first column, will also be powered and contribute to the current supplied to the calculation circuit 212.

[0067] [Fig.5A] illustrates calculations performed between layers 102 and 104 of the neural network 100, according to an embodiment of the present description. In particular, [Fig.5A] illustrates the implementation, by the non-volatile memory 200, of the operations between layers 102 and 104.

[0068] A control signal II, corresponding to the input value INI is supplied, via one of the word lines, for example WL1, to a memory cell 500 implementing neuron 108 (READ PATH A1). Control signal II is for example configured to control the gate of a transistor on one or more word lines. For example, control signal II is based on a voltage value. In another example, the control signal is a PWM (Pulse Width Modulation) type control signal based on a duty cycle. The resistive element of cell 500 has been programmed upstream to a value encoding weight A1. Similarly, signals 12, 13 and 14 are respectively supplied, via word lines, for example word line WL2, and word lines WL3 and WL4 (not shown), to memory cells 502, 504 and 506 implementing neurons 110 (READ PATH A2), 112 (READ PATH A3) and 114 (READ PATH A4). The resistive elements of cells 502, 504 and 506 were, respectively, programmed upstream to values ​​encoding the weights A2, A3 and A4.

[0069] The outputs of the memory cells 500, 502 and 504 are, for example, supplied to a calculation circuit 212_1. The calculation circuit 212_1 is then configured to generate an input value, based on the outputs of the cells 500, 502 and 504, for the memory cell implementing the neuron 116 and included in the matrix 203'. The generated value, encoding for example a signal I' 1, is then programmed in a resistive element 508 (PROG / ERASE I' 1) similar to the resistive element 318. The signal I' 1 is thus read and reused as an input to the word decoder 204.

[0070] Similarly, the outputs of the memory cells 502 and 504, and respectively of the cells 500 and 506 are, for example, supplied to a calculation circuit 212_2, and 212_3. The calculation circuit 212_2, respectively the circuit 212_3, is then configured to generate an input value, on the basis of the outputs of the cells 502 and 504, respectively of the cells 500 and 506, for the memory cell implementing the neuron 118, respectively 120 and included in the matrix 203'. The generated value, encoding for example a signal 1'2, respectively a signal 1'3, is then programmed in a resistive element 510 (PROG / ERASE 1'2), respectively 512 (PROG / ERASE 1'3). Signal 1'2, respectively signal 1'3, is thus read and reused as input to the word decoder 204.

[0071] The control circuit 208 is, for example, configured to, first of all, control the power supply of the set of reading paths formed by the cells 500, 502 and 504 and connected to the calculation circuit 212_1. Once the outputs of the cells 500, 502 and 504 are supplied to the calculation circuit 212_1, the control circuit 208 controls, for example in parallel, the power supply of the set of paths formed by the cells 502 and 504 and connected to the calculation circuit 212_2 and of the set of paths formed by the cells 514 and 518 and connected to the calculation circuit 212_3. Indeed, the parallel power supply of the two sets of paths is possible because these two sets of reading paths do not include a memory cell in common.

[0072] [Fig.5B] illustrates calculations performed between layers 104 and 106 of the neural network 100, according to an embodiment of the present description. In particular, [Fig.5B] illustrates the implementation, by the non-volatile memory 200, of the operations between layers 104 and 106, for example following the programming of the resistive elements 508, 510 and 512.

[0073] The signal I' 1 is supplied, via one of the bit lines of the area 202' to a memory cell 514 (READ PATH Bl) implementing the neuron 116. The resistive element of the cell 514 has been programmed, upstream, to a value encoding the weight BL. Similarly, the signals 1'2 and 1'3 are respectively supplied, via word lines of the area 202', to memory cells 516 (READ PATH B2) and 518 (READ PATH B3) implementing the neurons 118 and 120. The resistive elements of the cells 516 and 518 have been, respectively, programmed upstream to values ​​encoding the weights B2 and B3.

[0074] The outputs of the memory cells 514, 516 and 518 are, for example, supplied to a calculation circuit 212_4. The calculation circuit 212_4 is then configured to generate an input value, on the basis of the outputs of the cells 514, 516 and 518, for the memory cell implementing the neuron 122 and included in the matrix 203. The generated value, corresponding for example to a signal I” 1, is then programmed in a resistive element 522 (PROG / ERASE I” 1) similar to the resistive element 318. For example, the programming of the generated value is carried out following the deletion of a value already stored in the element 522. The signal F ' 1 is thus read and reused as input to the word decoder 204.

[0075] Similarly, the outputs of memory cells 516 and 518, and respectively of cells 514 and 518, are for example provided to a calculation circuit 212_5, and 212_6. The calculation circuit 212_5, respectively the circuit 212_6, is then configured to generate an input value, on the basis of the outputs of cells 516 and 518, respectively of cells 514 and 518, for the memory cell implementing the neuron 124, respectively 126, and included in the matrix 203. The generated value, encoding for example a signal I”2, respectively a signal I”3, is then programmed in a resistive element 524 (PROG / ERASE I”2), respectively 526 (PROG / ERASE I”3). The signal I”2, respectively the signal I”3, is thus read and reused as input to the word decoder 204.

[0076] The control circuit 208 is for example configured to firstly control the power supply of the set of paths formed by the cells 514, 516 and 518 and connected to the calculation circuit 212_4. The control circuit 208 is then configured to control the power supply of the set of paths formed by the cells 516 and 518 and connected to the calculation circuit 212_5, then the power supply of the set of paths formed by the cells 514 and 518 and connected to the calculation circuit 212_6. Each of the sets having at least one memory cell in common with one of the other sets, the power supply is carried out set after set.

[0077] [Fig. 6] is a block diagram illustrating a non-volatile memory 600, according to one embodiment of the present disclosure. In particular, the volatile memory 600 is similar to the non-volatile memory 200 except that the matrix 203 is replaced by, or includes, sub-matrices 602 (TILE 1), 604 (TILE 2) and 606 (TILE 3). Similarly, the matrix 203' is replaced by, or includes, sub-matrices 602' (TILE 1'), 604' (TILE 2') and 606' (TILE 3'). Although three sub-matrices are illustrated in [Fig. 6], more or less than three sub-matrices may replace, or be included in, the matrices 203 and 203'.

[0078] For example, each sub-array comprises the memory cells of a set of read paths. In another example, each sub-array comprises the memory cells of several sets of read paths having no memory cells in common. Thus, for example, the memory cell 500 is, for example, duplicated in the sub-array 602 and in the sub-array 606. Generally, each memory cell appearing in at least two sets of read paths is duplicated in sub-arrays.

[0079] The implementation in sub-matrices and the duplication of memory cells common to several sets of reading paths allows the power supply, and the provision of the outputs of each set of paths to the associated calculation circuit, in parallel.

[0080] [Fig.7A] illustrates an example of the calculations performed between the layers 102 and 104 of the neural network 100, according to an embodiment of the present description. In particular, [Fig.7A] illustrates the implementation, by the non-volatile memory 600, of the operations between the layers 102 and 104.

[0081] By way of example, the memory cell 500 is for example included in the sub-matrix 602, and is duplicated in a cell 500' included in the sub-matrix 606. Similarly, the cells 502 and 504 included in the sub-matrix 602 are duplicated in cells 502' and 504' included in the sub-matrix 604. The memory cell 506 being included in a single set of paths, it is, for example, not duplicated and is implemented only in the sub-matrix 606.

[0082] The power supply of the sets of paths and the supply of the outputs to the calculation circuits 212_1, 212_2 and 212_3 is then carried out in parallel.

[0083] [Fig.7B] illustrates an example of the calculations performed between the layers 104 and 106 of the neural network 100, according to an embodiment of the present description. In particular, [Fig.7B] illustrates the implementation, by the non-volatile memory 600 of the operations between the layers 104 and 106, for example following the programming of the resistive elements 508, 510 and 512.

[0084] For example, the memory cell 514 is included in the sub-matrix 602', and is duplicated in a cell 514' included in the sub-matrix 606'. Similarly, the cell 516 included in the sub-matrix 602' is duplicated in cells 516' included in the sub-matrix 604'. The memory cell 518 being common to the three sets of paths illustrated in relation to [Fig.5B], it is duplicated in a cell 518' included in the sub-matrix 604' and in a cell 518”, included in the sub-matrix 606'.

[0085] The power supply of the sets of paths and the provision of the outputs to the calculation circuits 212_4, 212_5 and 212_6 is then carried out in parallel.

[0086] An advantage of the described embodiments is that all of the calculations performed by the neural network are performed within the non-volatile memory. Thus, there is no latency time due to the transfer of data between a memory and a processor.

[0087] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0088] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the arrangement of the different memory cells, and in particular the programming of the resistive elements, is within the reach of the person skilled in the art.

Claims

Claims

1. Non-volatile memory (200, 600) comprising: - a first area (202) comprising a first plurality of storage elements (400) configured to store weight values ​​associated with a first plurality of neurons of a neural network; - a second area (202') comprising a second plurality of storage elements; - a control circuit (208), configured to apply, to a plurality of first reading paths (300), one or more first input values, each first reading path comprising one of the storage elements of the first plurality of storage elements (400); - a first calculation circuit (212_1) configured to add currents provided by the first reading paths to generate a first output current;and - a programming circuit (314, 316) configured to convert the first output current into a first programming current, and to program a first storage element of the second plurality of storage elements using said first programming current.;

2. The non-volatile memory of claim 1, wherein the control circuit (208) is further configured to apply, to a plurality of second read paths, one or more second input values ​​generated by reading the first of the second plurality of storage elements, each second read path comprising one of the storage elements of the first plurality of storage elements (400), the non-volatile memory (200, 600) further comprising - a second calculation circuit (212), configured to add currents provided by the second read paths to generate a second output current, the programming circuit (314, 316) being configured to convert the second output current into a second programming current, and to program another storage element of the first area (202) of the memory using said second programming current.

3. The non-volatile memory (200, 600) of claim 2, wherein the control circuit (208) is further configured to apply, at a plurality of third read paths, one or more third input values ​​generated by reading the other storage element of the first area, each third read path comprising one of the storage elements of the first plurality of storage elements, and wherein the first calculation circuit is further configured to add currents provided by the third read paths to generate a third output current, the programming circuit being further configured to convert the third output current into a third programming current, and to reprogram the first storage element of the second plurality of storage elements using said third programming current.

4. The non-volatile memory (200, 600) of claim 3, wherein the storage elements included in the first read paths (300) define the weights associated with an input layer (102) of the neural network (100) and wherein the storage elements included in the third read paths define the weights associated with another layer, or an output layer (106), of the neural network.

5. Non-volatile memory (200, 600) according to any one of claims 1 to 4, wherein the weights stored by the first plurality of storage elements (302, 304, 306) define weights of neurons belonging to layers (102, 106) of odd parity, respectively of even parity, of the neural network and the weights stored by the second plurality of storage elements define weights of neurons belonging to layers of even parity (104), respectively of odd parity, of the neural network.

6. The non-volatile memory (200, 600) of any one of claims 1 to 5, wherein each storage element (302, 304, 306), among the first and second plurality of storage elements, belongs to a memory cell (400), each memory cell being connected to the control circuit via a word line (WL1, WLN) and a bit line (BL1, BL2), the control circuit (208) being configured to activate or deactivate word lines and bit lines.

7. The non-volatile memory (200, 600) of any one of claims 1 to 6, wherein the first computation circuit (212_1) is configured to generate the first output value, based on the currents supplied by the memory cells (400) included in a read path among the first read paths.

8. Non-volatile memory (200, 600) according to any one of claims 1 to 7, wherein the calculation circuit (212) is further configured to apply compensation and / or threshold and / or offset and / or scaling effects, based on the currents provided by the memory cells included in a read path among the first read paths.

9. The non-volatile memory (200, 600) of any one of claims 1 to 8, wherein the storage elements (302, 304, 306) and the other storage elements (318) are programmable resistive elements.

10. A non-volatile memory (200, 400) according to any one of claims 1 to 9, further comprising a third calculation circuit (212_3) configured to generate another output value, based on currents supplied by one or more memory cells included in a read path among the first read paths and one or more first input values.

11. The non-volatile memory (600) of claim 10, wherein the first and third computation circuits (212_1, 212_3) are configured to generate the output values ​​based on one or more cells in common in the plurality of first read paths, the cells in common being duplicated in at least two sub-areas (602, 604, 606) in the first area (202).

12. A method comprising: - applying, by a control circuit (208) to a plurality of first read paths (300), one or more first input values, each first read path comprising one of a first plurality of storage elements (400) of a first area of ​​a non-volatile memory, the first plurality of storage elements (400) being configured to store weight values ​​associated with a first plurality of neurons of a neural network; - adding, by a first calculation circuit (212_1), currents provided by the first read paths to generate a first output current; - converting, by a programming circuit (314, 316), the first output current into a first programming current, and programming, by the programming circuit (314, 316), a first storage element of a second plurality of storage elements of a second area of ​​the non-volatile memory using said first programming current.

13. The method of claim 12, further comprising: - applying, by the control circuit (208) to a plurality of second read paths, one or more second input values ​​generated by reading the first of the second plurality of storage elements, each second read path comprising one of the storage elements of the first plurality of storage elements (400), - adding, by a second calculation circuit (212), currents provided by the second read paths to generate a second output current; - converting, by the programming circuit (314, 316), the second output current into a second programming current, and programming, by the programming circuit (314, 316), another storage element of the first area (202) of the memory using said second programming current.

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