Electronic circuit

Abstract

Electronic Circuit This description concerns an electronic circuit comprising a first chip, having a GaN transistor, and a second chip, stacked such that an element of the second chip electrically connects a first node and a second node of the first chip, which are respectively connected to a conduction node and a control node of the GaN transistor. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Electronic circuit Technical field

[0001] The present description relates generally to electronic circuits and associated methods. Prior art

[0002] When manufacturing an electronic circuit, it may be useful to test certain components of the circuit before the circuit is completely finalized or assembled with other circuits. Summary of the invention

[0003] There is a need to provide electronic circuits whose components can be tested during manufacturing while minimizing manufacturing and design costs.

[0004] One embodiment overcomes all or part of the drawbacks of known circuits.

[0005] One embodiment provides an electronic circuit comprising a first chip, having a GaN transistor, and a second chip, stacked such that an element of the second chip electrically connects a first node and a second node of the first chip connected respectively to a conduction node and a control node of the GaN transistor.

[0006] One embodiment provides a method of manufacturing an electronic circuit comprising: - stacking a first chip, having a GaN transistor and a second chip, such that an element of the second chip electrically connects a first node and a second node of the first chip connected respectively to a conduction node and a control node of the GaN transistor.

[0007] In one embodiment, said element of the second chip comprises a conductive track arranged on a first face of the second chip.

[0008] In one embodiment, the second chip is a silicon-based chip.

[0009] In one embodiment, the second chip comprises at least one transistor.

[0010] In one embodiment, the transistor of the second chip is of the MOS type and the GaN transistor of the first chip is HEMT type.

[0011] In one embodiment, said transistor of the second chip has: - a first conduction node connected to the first node of the first chip via said element, and - a second conduction node connected to the control node of the transistor of the first chip via another element.

[0012] In one embodiment, an electrical contact between said element of the second chip and the first and second nodes of the first chip is a solder or a brazing.

[0013] In one embodiment, the second node of the first chip is connected to the control node of the GaN transistor via an electronic component.

[0014] In one embodiment, said electronic component is active or passive.

[0015] In one embodiment, said electronic component is configured to allow the establishment of an automatic operating point of the GaN transistor.

[0016] In one embodiment, said electronic component is a resistor.

[0017] In one embodiment, before stacking the first and second chips, the first and second nodes of the first chip are disconnected from each other.

[0018] In one embodiment, before stacking the first and second chips, a test of the electronic component is carried out. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] schematically illustrates a part of an electronic circuit according to one embodiment;

[0021] [Fig.2] illustrates a top view of the electronic circuit portion of the embodiment of [Fig.l];

[0022] [Fig.3] schematically illustrates a top view of an embodiment of an electronic circuit;

[0023] [Fig.4] schematically illustrates a sectional view AA of a part of the electronic circuit of the embodiment of [Fig.3];

[0024] [Fig.5] schematically illustrates the electronic circuit of [Fig.3] according to one embodiment; and

[0025] [Fig.6] illustrates a method of manufacturing the electronic circuit of [Fig.3]. Description of the embodiments

[0026] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements useful for understanding the modes of the described embodiments have been represented and are detailed.

[0028] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0030] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0031] [Fig.l] schematically illustrates an electronic circuit 170 according to one embodiment.

[0032] More particularly, [Fig.l] represents a first circuit of the electronic circuit 170 formed in a first chip 100 which comprises a GaN transistor 102. A first node NI of the first chip 100 is connected to a conduction node 142, 144, for example the source, of the GaN transistor 102. A second node N2 of the first chip 100 is connected to a control node 130, 132, for example the gate, of the GaN transistor 102. The transistor 102 also comprises another conduction node 110 for example the drain.

[0033] In the example shown, the conduction node 142, 144 and the control node 130, 132 each comprise two tracks, it is however possible to envisage a single track for each of them.

[0034] In one example, the GaN transistor is of the high-electron-mobility type (HEMT).

[0035] By the term "GaN transistor" is meant that the substrate of the transistor is an alloy based on gallium nitride, with however the possibility that other elements can be incorporated into this base alloy. This includes in particular transistors comprising one or more heterojunctions formed by alloys such as AlGaN / InGaN, AlInAs / GalnAs, GalnAs / AlGaAs, AlGaAs / AlGa.

[0036] In the example shown, the second node N2 of the first chip 100 is connected to the control node 132 of the GaN transistor via an electronic component 120. In one example, the electronic component 120 is configured to allow the establishment of an automatic operating point of the GaN transistor. In another example, the electronic component 120 is an active or passive component. The electronic component 120 is for example a resistor.

[0037] In the example shown, the nodes N1 and N2 are disconnected, in other words are not directly connected. This makes it possible to carry out test measurements, for example to determine a physical parameter of the component 120, for example its resistance and / or a leakage current of the gate 132 of the transistor 102.

[0038] [Fig. 2] illustrates a top view of a portion of the electronic circuit 170 of the embodiment of [Fig. 1]. More particularly, [Fig. 2] represents the first chip 100. In the example shown, a connection pad of the conduction node 110 of the GaN transistor 102, for example the drain, is arranged on an upper portion of the chip 110 in the form, for example, of a rectangle arranged in and / or on a substrate 202, for example made of GaN. Connection pads connected to the tracks 130, 132 forming the control node are arranged in a corner opposite the conduction node 110 on the same surface of the substrate 202. Connection pads connected to the tracks 142, 144 forming the source of the transistor 102 are arranged for example in and / or on the same surface of the substrate 202 and this between the pads connected to the tracks 130 and 132.Between the connection pads connected to the tracks 142, 144 is the electronic component 120, which in this example is a resistor arranged on the same surface of the substrate 202. The electronic component 120 is electrically isolated, on the first chip 100, from the connection pads connected to the tracks 142, 144. In a manner not illustrated, the electronic component 120 is for example connected to the tracks 130 and 132 by vias and / or conductive tracks in the substrate 202.

[0039] The examples of figures 1 and 2 make it possible to measure, for example, one or more physical parameters of the electronic component 120. However, once the measurement or test has been carried out, to form a complete circuit, the nodes NI and N2 must, for example, be electrically connected. This is the case, for example, if one wishes to implement a cascode structure from the first chip 100.

[0040] It is possible to make this connection by performing a soldering with a wire (wire bonding in English) between the nodes NI and N2. However, this is expensive and can cause reliability problems as well as introduce interference into the signals.

[0041] The described embodiments provide, in addition to the first chip 100, a second chip, stacked with the first chip so that an element of the second chip electrically connects the first node N1 and the second node N2 of the first chip. This makes it possible to carry out measurements on the first chip, for example on the electronic component 120, and once the assembly is formed with the second chip, to obtain a complete circuit, for example a cascode type circuit. Another advantage is that, unlike the use of a soldered wire, the appearance of parasitic elements of the “RLC” type is limited. This also induces better stability during signal transitions and limits the costs related to soldering and additional material.

[0042] [Fig. 3] schematically illustrates a top view of an embodiment of an electronic circuit 370.

[0043] The circuit 370 includes the first chip 100, similar to that described in Figures 1 and 2, and a second chip 300. The first and second chips 100, 300 are stacked. In one example, the second chip 300 is a silicon-based or semiconductor-based chip. In another example, the second chip 300 includes at least one circuit with a transistor.

[0044] In the example shown, the second chip 300 is stacked above the first chip. The second chip 300 comprises an element 350 arranged on a face of the second chip 300 which faces the surface located in front of the first chip 100. The element 350 of the second chip comprises for example a conductive track, for example metallic or made of a heavily doped semiconductor. This conductive track is for example formed by or connected to a drain 340 or a source or a gate of a transistor of the second chip 300.

[0045] In the example of [Fig.3], it can be seen by transparency that the second chip covers the connection pads connected to the tracks 142, 144 as well as the electronic component 120.

[0046] In the example shown, the element 350 partially covers the connection pads connected to the tracks 142, 144. In another example, the element 350 completely covers these pads. As shown in [Fig. 1], the source of the transistor 102 can be divided into two parts 142, 144, both connected to the node N1. The element 350 electrically connects the first node N1 and the second node N2 of the first chip 100, in other words, the element 350 electrically connects the source of the transistor 102 to the second node N2, which is itself connected to the electronic component 120. In an example where the source of the transistor 102 is formed by a single conductive track, the element 350 electrically connects this track, and thus the source of the transistor 102, to the second node N2.

[0047] In one example, an electrical contact between the element of the second chip 300 and the first and second nodes NI, N2 of the first chip is made with a weld or a solder. In another example, this electrical contact is made by means of a conductive adhesive film (“die attach adhesive film” in English) containing for example silver and / or nickel, and / or copper and / or gold and / or palladium. A heat treatment accompanied or not by the application of pressure can also be used to form the contact.

[0048] The example of [Fig.3] makes it possible to increase the contact surface between the first and second chip to make contact between nodes N1 and N2 unlike a wire connection whose contact surfaces are reduced and fragile.

[0049] [Fig.4] schematically illustrates a sectional view AA of part of the circuit electronics of the embodiment of [Fig.3]. Section AA intersects the first and second chips 100, 300 at the source connection pads 142, 144 as well as the electronic component 120 and the element 350.

[0050] In the example shown, the pads of the source 142, 144 are arranged in the substrate 202 from the surface of the first chip 100 which is opposite the second chip 300. The element 350 is arranged in a substrate 402 of the second chip 300 from the surface of the second chip facing the first chip. The element 350 partially covers the source pads 142, 144 of the transistor 102 of the first chip 100 at the level of the node NI, which is distributed on the source pads 142, 144. The element 350 also covers the element 120 at the level of the node N2 which is distributed on the surface of the component 120. These coverings as well as any associated welds or solders form the electrical contact between the source 142, 144 of the transistor 102 and the second node N2 which is connected to the gate of the transistor 102.

[0051] In one example, the element 350 is a part of a conduction node, for example a drain 340, of a transistor of the second chip. This makes it possible to limit the connection lengths as much as possible.

[0052] [Fig.5] schematically illustrates the electronic circuit of [Fig.3] according to one embodiment.

[0053] In the example shown, the first chip 100 comprises a circuit similar to that of [Fig.l] and the element 350 of the second chip 300 is a part of the drain 340 of a transistor 502 of the second chip 300. In one example, the transistor 502 of the second chip 300 is of the MOS (Metal Oxide Semiconductor) type and the substrate 402 is silicon-based.

[0054] In the example shown, the source 542 of the transistor 502 is connected, preferably connected, to the control node 130, 132 of the GaN transistor 102 of the first chip 100. This connection is made for example in a similar manner to the connection between the first and second nodes NI, N2. In this example, the source 542 of the transistor 502 is connected to the substrate of the transistor 502. The drain 340 of the transistor 502 is connected to the element 350 and therefore also to the nodes NI and N2. The transistor 502 further has a control node 530.

[0055] The example of [Fig.5] thus forms a cascode type circuit with the source 142, 144 of the GaN transistor 102 in series with the drain 340 of the transistor 502, and the gate 130, 132 of the transistor 102 connected to the source 542 of the transistor 502.

[0056] [Fig.6] illustrates a method of manufacturing the electronic circuit of [Fig.3].

[0057] In a first step 600 (STACK GaN DIE AND MOS DIE), the first and the second chips 100, 300 are superimposed for example so as to place the element 350 opposite the source pads 142, 144 as well as with the surface of the electronic component 120. Nodes NI and N2 are at this stage disconnected.

[0058] In a second step 602 (CONNECT FIRST NODE AND SECOND NODE OF GaN DIE WITH AN ELEMENT OF SECOND DIE), the nodes NI and N2 of the first chip 100 are electrically connected by the element 350 of the second chip. The connection is either direct or by means of soldering or brazing and / or by means of alloys and / or by the application of a heat treatment and / or pressure.

[0059] Before step 600, the nodes NI and N2 being disconnected, it is possible to test for example the resistance of the component 120 and / or a leakage current of the gate of the GaN transistor 102.

[0060] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, element 350 may be formed by a plurality of conductive points or surfaces.

[0061] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the element 350, it may be a conductive track or also be materialized by a conduction or control node or even a control node of a back gate of the transistor 502 of the second chip 300. The element 350 may further be materialized by a part of an electronic component such as a node of a diode or an inductance or a capacitance for example.

[0062] In the examples described, the second chip 300 is stacked on the first chip 100, however it is conceivable for the person skilled in the art to provide the reverse.

[0063] The described embodiments can be applied for example for applications using power such as for example automotive applications.

Claims

Claims

1. An electronic circuit (370) comprising a first chip (100), having a GaN transistor (102), and a second chip (300), stacked such that an element (350) of the second chip (300) electrically connects a first node (NI) and a second node (N2) of the first chip (100) respectively connected to a conduction node (140,142) and a control node (130,132) of the GaN transistor (102).

2. The circuit of claim 1, wherein said element (350) of the second chip (300) comprises a conductive track arranged on a first face of the second chip (300).

3. The circuit of claim 1 or 2, wherein the second chip (300) is a silicon-based chip.

4. A circuit according to any one of claims 1 to 3, wherein the second chip (300) comprises at least one transistor (502).

5. The circuit of claim 4, wherein the transistor (502) of the second chip (300) is of the MOS type and the GaN transistor (102) of the first chip (100) is of the HEMT type.

6. Circuit according to claim 4 or 5, wherein said transistor (502) of the second chip (300) has: - a first conduction node (340) connected to the first node (NI) of the first chip (100) via said element (350), and - a second conduction node (542) connected to the control node (130,132) of the transistor (102) of the first chip (100) via another element.

7. A circuit according to any one of claims 1 to 6, wherein an electrical contact between said element (350) of the second chip and the first and second nodes (NI, N2) of the first chip (100) is a solder or a brazing.

8. Circuit according to any one of claims 1 to 7, in which the second node (N2) of the first chip is connected to the control node of the GaN transistor (102) via an electronic component (120).

9. The circuit or method of claim 8, wherein said electronic component (120) is active or passive.

10. A circuit or method according to claim 8 or 9, wherein said electronic component (120) is configured to allow the establishment of an automatic operating point of the transistor GaN (102).

11. A circuit or method according to any one of claims 8 to 10, wherein said electronic component (120) is a resistor.

12. A method of manufacturing an electronic circuit (370) according to any one of claims 1 to 11, the method comprising: - stacking a first chip (100), having a GaN transistor (102) and a second chip (300), such that an element (350) of the second chip (100) electrically connects a first node (NI) and a second node (N2) of the first chip connected respectively to a conduction node (142, 144) and to a control node (130, 132) of the GaN transistor (102).

13. The method of claim 12, wherein, before stacking the first and second chips (100,300), the first and second nodes (NI, N2) of the first chip (100) are disconnected from each other.

14. The method of claim 13, wherein before stacking the first and second chips (100,300), a test of the electronic component (350) is performed.

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