Processor identification

Abstract

Identification of processors The present description relates to a device (2) comprising: a bus (BUS); peripherals (Periph1, Periph5, CAR) coupled to the bus, the peripherals comprising a first circuit (CAR); processors (CPU1, CPU2) coupled to the bus and initiating accesses to the peripherals each comprising an address phase followed by a data phase; and for each processor, a second circuit (CID1, CID2) providing an identifier (CID) of the processor on the bus during the address phase of each access initiated by the processor. For each read access to the first circuit (CAR) initiated by one of the processors (CPU1, CPU2), the first circuit (CAR) stores the identifier (CID) present on the bus (BUS) during the address phase of the access, then provides the identifier stored on the bus during the data phase of the access. Figure for the abstract: Fig. 2

Description

Title of the invention: Identification of processors Technical field

[0001] The present description relates generally to electronic circuits, and more particularly to systems on chip (SOC) comprising several processors. Prior art

[0002] Devices, or systems on chip, comprising several processors configured to execute the same set of instructions are known. In such devices, the processors are coupled, for example connected, to a bus to be able to implement read and / or write accesses to peripherals coupled, for example connected, to the bus.

[0003] In some of these known devices, read and / or write access to each peripheral is conditioned by the identity of the processor that initiated this access. Each processor is then identified by a unique identifier that is different from the identifiers of the other processors. For this purpose, each processor is associated with an identification circuit which, each time the processor initiates access to a peripheral via the bus, conveys or provides the identifier of the processor on the bus. In this way, when a peripheral receives an access request, it checks whether the identifier of the processor that initiated this access corresponds to the identifier of a processor authorized to access this peripheral.

[0004] In this way, it is possible to define compartments in the device, each compartment comprising a processor and all the peripherals to which the processor has the right to access. The identifier of each processor, provided by the identification circuit associated with this processor, is, for example, called the compartment identifier.

[0005] These known compartmentalized devices have various drawbacks. Summary of the invention

[0006] There is a need to overcome all or part of the disadvantages of the known compartmentalized devices described above.

[0007] For example, it would be desirable to have a compartmentalized device of the type described above, in which each processor would be able to obtain its compartment identifier.

[0008] One embodiment overcomes all or part of the drawbacks of the known compartmentalized devices described above.

[0009] One embodiment provides a device comprising: a bus; peripherals coupled to the bus, the peripherals comprising a first circuit; processors coupled to the bus, and configured to execute a same set of instructions and initiate accesses to the peripherals via the bus, each access comprising an address phase followed by a data phase; and for each processor, a second circuit associated with the processor and configured to provide a processor identifier on the bus during the address phase of each access initiated by the processor, in which the first circuit is configured to, upon each read access to the first circuit initiated by one of the processors: - memorize the identifier present on the bus during the address phase of the access; and - provide the identifier memorized on the bus during the data phase of the access.

[0010] Another embodiment provides a method implemented in a device comprising a bus, peripherals connected to the bus and comprising a first circuit, processors coupled to the bus, executing the same instruction set, each being associated with a second circuit and initiating accesses to the peripherals via the bus, each access comprising an address phase followed by a data phase, the method comprising: - initiate, with one of the processors, a read access to the first circuit; - provide the bus, during the address phase of the access and with the second circuit associated with the processor initiating the access, with an identifier of the processor; - memorize with the first circuit the identifier present on the bus during the address phase of the access; - provide the bus, with the first circuit, and during the data phase of the access, with the stored identifier.

[0011] According to one embodiment: the peripherals comprise memory shared between at least two of said processors; and a program defined by a sequence of instructions of said instruction set is recorded in said memory and is accessible to said at least two processors.

[0012] According to one embodiment, the program comprises at least one portion having an execution conditioned by the identifier of the processor executing the program.

[0013] According to one embodiment, for each access by one of the processors to one of the peripherals other than the first circuit, the device is configured to condition access to the peripheral on the basis of the identifier of the processor having initiated the access.

[0014] According to one embodiment, the first circuit comprises a register configured to memorize, during the address phase of each read access to the first circuit, the identifier present on the bus and corresponding to the processor having initiated the read access; provide the bus, during the data phase of each read access to the first circuit, with the identifier stored during the address phase of this read access.

[0015] According to one embodiment, each identifier corresponds to a different processor.

[0016] According to one embodiment, read and write access to the second circuits is impossible.

[0017] According to one embodiment, the bus is of the AMBA type.

[0018] According to one embodiment, the identifier of each processor is hard-coded in the second circuit associated with this processor.

[0019] According to one embodiment, the first circuit is accessible in read-only mode. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] represents, in the form of blocks, an example of a device to which the described embodiments and variants apply;

[0022] [Fig.2] represents, in the form of blocks, an exemplary embodiment of a device;

[0023] [Fig. 3] represents, in the form of a flowchart, an exemplary embodiment of a method implemented in the device of [Fig. 2]; and

[0024] [Fig.4] represents, in the form of blocks, an example of a detailed embodiment of a circuit of the device of [Fig.2]. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0027] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when referring to position qualifiers absolute, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or orientation qualifiers, such as the terms "horizontal", "vertical", etc., are referred to unless otherwise specified to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] [Fig.l] represents, in block form, an example of a device or system on chip 1 to which the described embodiments and variants apply.

[0031] The device 1 comprises N processors CPUi, with N being an integer greater than or equal to 2, and i being an integer index ranging from 1 to N. In the example of [Fig.l], N is equal to 2 and the device therefore comprises two processors CPUI and CPU2. The processors CPUi are configured to execute the same set of instructions. Preferably, the processors CPUi are identical, although this is not essential as long as they can execute the same set of instructions.

[0032] The device 1 further comprises M peripherals Periphj, with M a strictly positive integer and j an integer index ranging from 1 to M. In the example of [Fig.l], M is equal to 5 and the device 1 comprises the peripherals Periphl, Periph2, Periph3, Periph4 and Periph5. As an example, one of the M peripherals, for example the peripheral Periph5 in the example of [Fig.l], is a memory shared between at least two of the N processors.

[0033] The device 1 further comprises a bus BUS to which the peripherals Periphj are coupled, for example connected, and to which the processors CPUi are coupled, for example connected.

[0034] The CPUi processors are the circuits of the device 1 which are configured to initiate read and / or write accesses to other circuits, for example the peripherals Periphj, coupled to the bus BUS. The CPUi processors then have the role of "master" circuits. Conversely, the peripherals Periphj cannot initiate read and / or write accesses to the other circuits coupled to the bus BUS. The peripherals Periphj then have the role of "slave" circuit.

[0035] In the device 1, the CPUi processors are configured so that each write or read access to a peripheral Periphj initiated by a CPUi processor, via the bus BUS, comprises two successive phases. More particularly, each read or write access to a peripheral Periphj comprises a first phase, called the address phase, followed by a second phase, called the data phase.

[0036] For example, during the address phase of an access, the CPUi processor having initiated this access provides on the bus BUS: - the address where the CPUi wants to write or read data, therefore the address of the Periphj device it wants to access; and - an indication that the requested access is read or write access.

[0037] By way of example, the bus BUS comprises several conductive wires on which the bits of the write or read address of the data are transmitted simultaneously, in parallel, each address bit being transmitted on a corresponding conductive wire.

[0038] For example, the bus BUS comprises a conductor on which the indication that the access is a read access or a write access is transmitted. For example, a bit in a first binary state is transmitted on this conductor to indicate a read access, and in a second binary state to indicate a write access.

[0039] By way of example, the bus BUS comprises a conductive wire on which a clock signal is available timing the first and second phases of each access.

[0040] By way of example, the bus comprises a conductor wire on which a bit is transmitted indicating, by a first binary state, that data bits available on the conductors of the bus BUS are valid and can be read, and, by a second binary state, that the data bits available on the conductors of the bus are not valid.

[0041] For example, each first phase has a duration of one cycle of the clock signal. For example, in this case, the address bits, the bit indicating the type (read or write) of access, and, for example, the bit indicating whether the bits on the bus BUS are valid or not are then transmitted simultaneously and in parallel.

[0042] For example, during the data phase of an access, the data that is read or written is transmitted on the bus. For example, the bus BUS comprises several conductive wires on which the data bits written or read are transmitted simultaneously, in parallel, each data bit being transmitted on a corresponding conductive wire.

[0043] For example, the BUS bus is of the AMBA type (from the English "Advanced Micro-controller Bus Architecture").

[0044] The device 1 further comprises, for each processor CPUi, a CIDi circuit associated with the processor CPUi. Thus, in the example of [Fig.l], a CIDI circuit is associated with the processor CPUI, and a CID2 circuit is associated with the processor CPU2.

[0045] Each CIDi circuit includes the compartment identifier of the processor with which it is associated.

[0046] For example, in certain phases of operation, for example when CPUi processors are turned off to implement a low-power mode, one or more compartment identifiers of one or more processors, for example one or more processors turned off, may be delegated to another processor, for example a processor that remains turned on. Thus, the CPUi processor to which one or more compartment identifiers of other CPUi processors have been delegated may implement functions normally assigned to these other processors. For example, a A CPUi processor that remains on can perform functions normally assigned to a processor that has been turned off, thereby leaving that other processor turned off. This temporary assignment to a processor of the compartment ID(s) of one or more other processors is, for example, called "compartment ID delegation".

[0047] For example, in each CIDi circuit, the compartment identifier of the CPUi processor with which the CIDi circuit is associated is hard-coded, i.e. in hardware.

[0048] For example, the compartment identifier of each CPUi processor is determined once and for all during the design of the device 1. In other words, this identifier cannot be modified.

[0049] Preferably, each CIDi circuit is neither a peripheral Periphj nor a CPUi processor. For example, the CIDi circuits cannot initiate read or write access to a peripheral Periphj. Furthermore, the CIDi circuits are, for example, neither read nor write accessible.

[0050] Each CIDi circuit is configured, at each access (read or write) to a peripheral Periphj via the bus BUS which is initiated by its associated processor CPUi, to provide on the bus the compartment identifier of this processor CPUi, during the data phase of this access. For example, the bus BUS comprises several conductor wires on which bits corresponding to (or encoding) the compartment identifier of the processor having initiated the access are transmitted. In this way, the bits of the compartment identifier are transmitted simultaneously, in parallel, each bit of the compartment identifier being transmitted on a conductor dedicated to this purpose.

[0051] As already indicated previously, the provision of a compartment identifier per processor CPUi makes it possible to compartmentalize the device 1. In other words, this makes it possible to define, or choose, for each processor CPUi, which peripheral(s) Periphj this processor can access.

[0052] For example, a peripheral can be accessible to several CPUi processors. For example, when the peripheral Periph5 is a memory, this memory can be accessible to several processors, for example to the two processors CPUI and CPU2 in the example of [Fig.l], the memory then being said to be "shared".

[0053] To implement these compartments in the device 1, each peripheral Periphj is configured, when it receives an access request initiated by a CPUi processor, during the data phase of this access, to condition this access, i.e. the implementation of the read or write access to data in the peripheral, to the compartment identifier of the CPUi processor having initiated the access.

[0054] For example, when a CPUi processor initiates an access to a peripheral Periphj, as the CIDi circuit associated with the CPUi processor provides to the bus BUS, during the phase address of this access, the compartment identifier of the processor CPUi, the peripheral Periphj determines which processor initiated the access thanks to the compartment identifier that it reads on the bus BUS during the data phase. Then, the peripheral Periphj compares this read identifier with the compartment identifier(s) of a list comprising the compartment identifier(s) of all the processors CPUi of device 1 which have the right to access this peripheral Periphj. If the compartment identifier read is found in this list, the processor CPUi having initiated the access has the right to access the peripheral Periphj and the access continues with the data phase during which the peripheral Periphj will provide data on the bus (for a read access) or receive data (for a write access).

[0055] For example, in [Fig.l], the peripherals Periphl and Periph2 are accessible only by the processor CPUI, the peripherals Periph3 and Periph4 are accessible only by the processor CPU2, and the peripheral Periph5 is accessible by both processors CPUI and CPU2. The device 1 then comprises two compartments.

[0056] A disadvantage of the device 1 is that each processor CPUi does not have access to its compartment identifier, or, in other words, does not have knowledge of its identifier.

[0057] To overcome this drawback, it is proposed to add a circuit to the peripherals. At each read access to this circuit, this circuit stores, during the address phase of the access, the compartment identifier of the processor having initiated the access, then this circuit provides to the bus, during the data phase of the access, the identifier stored during the address phase.

[0058] Preferably, the stored identifier provided on the bus during the data phase of the access corresponds to the data read during this read access. For example, when the bus comprises conductive wires configured to transmit in parallel, during the data phase of an access, the bits of the data read or written during this access, then the stored identifier is transmitted, during the data phase, on these conductive wires.

[0059] [Fig.2] represents, in the form of blocks, an exemplary embodiment of a device 2.

[0060] Device 2 is similar to device 1 of [Fig.l], and only the differences between these two devices are highlighted here. In other words, unless otherwise indicated, everything indicated for device 1 applies to device 2.

[0061] Compared to the device 1, the device 2 comprises, in addition to the M peripherals Periphj, an additional peripheral CAR. The circuit CAR is coupled, for example connected, to the bus BUS.

[0062] Preferably, the CAR circuit or peripheral is accessible in read-only mode.

[0063] For example, read access to the CAR peripheral is carried out in the same way way that read access to one of the Periphj devices.

[0064] For each read access to the CAR peripheral initiated by one of the CPUi processors, the CAR peripheral is configured to store the compartment identifier of the CPUi processor that initiated the access. This storage is performed during the data phase of the access, the compartment identifier of the CPUi processor that initiated the access then being available on the BUS bus. For example, the CAR circuit detects that a processor has initiated a read access to the CAR circuit by comparing its address with that available on the BUS bus during the address phase of the access, and by detecting on the BUS bus that the requested access is a read access.

[0065] Furthermore, the circuit CAR is configured, during the data phase of this access, to provide the stored identifier on the bus BUS. More particularly, the circuit CAR is configured, during this data phase, to provide the compartment identifier on the bus BUS so that the processor CPUi having initiated the read access obtains its compartment identifier, or, in other words, so that it can read this compartment identifier.

[0066] For example, the compartment identifier stored by the CAR circuit during the address phase of the access is restored on the bus BUS during the following data phase as being the data transmitted on the bus.

[0067] For example, each time a processor CPUi validly accesses a peripheral Periphj, during the data phase of the access, the data to be read or written corresponding to this access passes over the bus BUS and, in the case of a read access to the peripheral CAR, this data corresponds to the compartment identifier stored by the circuit CAR during the address phase of this read access.

[0068] In this way, when a CPUi processor wishes to know its compartment identifier, it is sufficient for this CPUi processor to initiate a read access to the CAR circuit, so that it receives, during the data phase of the access, its compartment identifier in the form of the data read in the CAR circuit.

[0069] The fact that each CPUi processor of the device 1 can obtain its compartment identifier has many advantages.

[0070] For example, according to one embodiment, one of the M peripherals Periphj, for example the peripheral Periph5, is a memory shared between at least two processors of the device 2, for example between the processors CPUI and CPU2 in the example of [Fig. 2]. It is then possible to store in the memory Periph5 a computer program code common to these two processors, this program comprising portions whose execution is conditioned by the identifier of the processor executing the program.

[0071] In other words, the code comprises one or more portions which can (or must) each only be executed by one of the processors CPUI and CPU2 allocated to this portion. Thus, when one of the processors CPU1 and CPU2 executes the code and arrives at such a portion of the code, it only executes this portion of code if its compartment identifier corresponds to the compartment identifier of the processor having the right to execute this portion of code. To do this, the processor executing the code implements a read access to the CAR circuit so as to obtain its compartment identifier, and compares its compartment identifier thus obtained with that which conditions the execution of the portion of code. If the two identifiers are identical, the processor executes the portion of code, and, conversely, if the two identifiers are different, the processor does not execute this portion of code. The program common to several processors which is stored in shared memory is, for example, defined by a sequence of instructions from the instruction set common to these processors.

[0072] As an example, we call "HSR->Attr" the compartment identifier of a processor CPUi that this processor CPUi obtains during a read access to the circuit CAR, CPU1_CID the compartment identifier of the processor CPUI, CPU2_CID the compartment identifier of the processor CPU2, P a code executable by either of the processors CPUI and CPU2, PI a first portion of the code C, and P2 a second portion of this code P. As an example, we consider that the code P has the following form: if (HSR->Attr == CPU1_CID) { PI} elsif (HSR->Attr == CPU2_CID) { P2}. When this P code example is executed by the CPUI processor, the latter makes a read access to the CAR circuit when it reaches the condition "if (HSR->Attr == CPU1_CID)" and then compares the identifier obtained with the identifier CPU1_CID. Since these are equal, the condition HSR->Attr == CPU1_CID is fulfilled and the CPUI processor executes the PL code portion. Then, when the CPUI processor reaches the condition "elsif (HSR->Attr == CPU2_CID)", it either makes a read access to the CAR circuit again if it had not memorized the identifier obtained during the previous read access to the CAR circuit, or it directly uses the identifier obtained during the previous read access to the CAR circuit if it had memorized it. The processor then compares the identifier obtained thanks to the read access to the CAR circuit with the identifier CPU2_CID.Since these are different, the condition HSR->Attr == CPU2_CID is not met and the CPUI processor then does not execute the P2 portion. Similarly, when the P code is executed by the CPU2 processor, it does not execute the PI portion but executes the P2 portion.

[0073] Conditioning the execution of one or more portions of a code on the compartment identifier of the CPUi processor executing the code allows this code to be common to multiple CPUi processors, while retaining portions of code that can only be executed by a given processor. The result is that instead of storing specific code in memory for each CPUi processor, what is stored in memory is code common to multiple processors with one or more specificities for at least one of these processors.

[0074] This allows to reduce the size of the Periph5 memory.

[0075] This also allows, when the code must be updated to modify or add a function or portion of code specific to one of the CPUi processors, that the verification of the obtained code and its deployment are simplified.

[0076] Although an example of a P code common to two processors CPUI and CPU2 has been described above, the person skilled in the art is able to predict a code common to more than two processors from the functional indications given above.

[0077] Furthermore, although an example of a code P common to several CPUi processors has been described above in which the code P comprises a specific portion for each CPUi processor, the person skilled in the art will be able to provide a code common to several processors comprising at least one portion specific to a given processor, and which may or may not comprise, for each other processor sharing this code, at least one portion specific to this processor.

[0078] Although an example of code P common to two processors CPUI and CPU2 has been described in which the portion PI can only be executed by the processor CPUI, and the portion P2 can only be executed by the processor CPU2, in other examples not illustrated where the device further comprises a processor CPU3, at least one of the portions PI and P2 can be executed by more than one processor. For example, in this case, the portion PI can be executed by either of the processors CPUI and CPU3 while the portion P2 can only be executed by the processor CPU2.

[0079] [Fig. 3] represents, in the form of a flowchart, an example of an embodiment of a method implemented in the device 2 of [Fig. 2].

[0080] More particularly, [Fig.3] illustrates an exemplary embodiment of read access to the CAR circuit, the step of read access to the CAR circuit being referenced 300 in [Fig.3].

[0081] This phase 300 of read access to the CAR circuit first comprises an address phase 302 (block "Address Phase of Read Access CAR"). During this address phase 302, the processor CPUi having initiated the read access provides the bus BUS with the address where a data item must be read. This address corresponds, for example, to the address of the peripheral CAR or of a register of the peripheral CAR. Furthermore, during this address phase 302, the circuit CIDi of the processor CPUi having initiated the access provides the bus BUS with the compartment identifier of this processor CPUi.

[0082] During phase 302, at a step 304 (block "Memorize CID"), the CAR circuit stores the compartment identifier present on the bus. For example, the CAR circuit detects that a processor CPUi has initiated a read access to the CAR circuit thanks to the address and the indication that the requested access is a read access, this information being present on the bus BUS during the address phase 302. For example, the compartment identifier present on the bus BUS during the address phase 302 of the read access 300 to the CAR circuit is stored in a register of the CAR circuit.

[0083] The address phase 302 of the read access 300 is followed by the data phase 306 (block "Data Phase of Read Access CAR") of this access 300.

[0084] During the data phase 306, at a step 308 (block "Provide CIDm"), the circuit CAR provides the bus BUS with the compartment identifier that the circuit CAR stored in step 304 of the previous address phase 302. The compartment identifier provided to the BUS then corresponds to the data of the read access 300, that is to say to the data that is read from the circuit CAR by the processor CPUi having initiated the access 300.

[0085] The end of the data phase 306 marks the end of the read access 300 to the CAR circuit.

[0086] [Fig.4] represents, in the form of blocks, an example of a detailed embodiment of the CAR circuit of the device 2 of [Fig.2].

[0087] The circuit CAR comprises a register REG. The register REG is configured to store, during the address phase of each read access to the circuit CAR, the identifier of the processor CPUi having initiated the access, this identifier being supplied to the bus BUS by the circuit CIDi associated with this processor CPUi. The register REG is further configured, during the data phase of each read access to the circuit CAR, to supply to the bus BUS the identifier stored during the previous address phase.

[0088] For example, the register REG comprises a plurality of D-type flip-flops 400 ("D flip-flip" in English). For example, each flip-flop 400 comprises a data input D configured to receive a bit, an output Q configured to provide a bit stored in the flip-flop 400, and a synchronization input clk configured to receive a timing signal, for example the clock signal of the bus BUS. Each flip-flop 400 is then configured, at each active edge of the clock signal received on its input clk, to store the bit present on its input D and update its output Q accordingly.

[0089] By way of example, the circuit CAR comprises a selection or routing circuit 402. The circuit 402 is configured to provide, at the data input of the register REG, the compartment identifier CID present on the bus BUS during the address phase of each read access to the circuit CAR, and the compartment identifier CIDm stored in the register REG otherwise.

[0090] For example, the circuit 402 comprises an input 10, an input II, an input of selection S and an output O coupled, preferably connected, to the input of the register REG, for example to the inputs D of the flip-flops 400. The input II of the circuit 402 is, for example, configured to receive the compartment identifier CID present on the bus BUS during the address phase of each read or write access initiated by a processor CPUi, the input 10 of the circuit 402 being for example configured to receive the output of the register REG, that is to say the identifier CIDm stored in the register REG. The input S of the circuit 402 is, for example, configured to receive a binary control signal Ctrl.When the Ctrl signal is in a first binary state, the circuit 402 couples its input II to its output O, or, in other words, provides on its output O the identifier CID present on its input II, and, when the Ctrl signal is in a second binary state, the circuit 402 couples its input 10 to its output O, or, in other words, provides on its output O the stored identifier CIDm present on its input 10. The Ctrl signal is configured to be in its first binary state during the address phase of each read access to the CAR circuit, and in its second binary state otherwise.

[0091] By way of example, the circuit CAR comprises a circuit 404 configured to provide the signal Ctrl from the signals available on the bus BUS. For example, the circuit 404 is configured to detect that an access to the circuit CAR has been initiated by a processor CPUi from the address present on the bus BUS and the indication present on the BUS that a read access is requested.

[0092] The person skilled in the art is able to provide other examples of implementation of the circuit CAR from the functional indications given above. For example, the circuit 402 can be omitted. In such an example, the data input of the register REG then directly receives the compartment identifier CID present on the bus BUS, and the register REG, for example each of the flip-flops 400, further comprises an activation input receiving the signal Ctrl and being configured to allow the updating of the register REG only during the active edges of the clock signal of the bus BUS while the signal Ctrl is in its first binary state, and not to modify, or update, the register REG if the signal Ctrl is in its second binary state.

[0093] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0094] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Device (2) comprising: a bus (BUS); peripherals (Periphl, Periph5, CAR) coupled to the bus, the peripherals comprising a first circuit (CAR); processors (CPU1, CPU2) coupled to the bus, and configured to execute the same set of instructions and initiate accesses to the peripherals via the bus, each access comprising an address phase followed by a data phase; and for each processor, a second circuit (CID1, CID2) associated with the processor and configured to provide an identifier (CID) of the processor on the bus during the address phase of each access initiated by the processor, in which the first circuit (CAR) is configured for, at each read access (300) to the first circuit (CAR) initiated by one of the processors (CPU1, CPU2): - memorize (304) the identifier (CID) present on the bus (BUS) during the address phase (302) of the access (300); and - provide (308) the stored identifier (CIDm) on the bus (BUS) during the data phase (306) of the access (300).

2. Method implemented in a device (2) comprising a bus (BUS), peripherals (Periphl, Periph5, CAR) connected to the bus and comprising a first circuit (CAR), processors (CPU1, CPU2) coupled to the bus, executing the same instruction set, each being associated with a second circuit (CID1, CID2) and initiating accesses to the peripherals via the bus, each access comprising an address phase followed by a data phase, the method comprising: - initiate, with one of the processors, a read access (300) to the first circuit (CAR); - providing the bus (BUS), during the address phase (302) of the access (300) and with the second circuit (CID1, CID2) associated with the processor (CPU1, CPU2) initiating the access, with an identifier (CID) of the processor; - memorize (304) with the first circuit (CAR) the identifier (CID) present on the bus (BUS) during the address phase (302) of the access (300); - supply (308) to the bus (BUS), with the first circuit (CAR), and during the data phase (306) of the access (300), the stored identifier (CIDm).

3. Device according to claim 1, wherein: the peripherals comprise a memory (Periph5) shared between at least two of said processors (CPU1, CPU2); and a program defined by a sequence of instructions of said set of instructions is recorded in said memory and is accessible to said at least two processors (CPU1, CPU2).

4. Device according to claim 3, in which the program comprises at least one portion having an execution conditioned by the identifier (CID) of the processor (CPU1, CPU2) executing the program.

5. Device according to any one of claims 1, 3 and 4, wherein, for each access by one of the processors (CPU1, CPU2) to one of the peripherals other than the first circuit (CAR), the device (2) is configured to condition access to the peripheral on the basis of the identifier (CID) of the processor (CPU1, CPU2) having initiated the access.

6. Device according to any one of claims 1 and 3 to 5, in which the first circuit (CAR) comprises a register (REG) configured to: store (304), during the address phase (302) of each read access (300) to the first circuit, the identifier (CID) present on the bus (BUS) and corresponding to the processor having initiated the read access; provide (308) to the bus (BUS), during the data phase (306) of each read access (300) to the first circuit (CAR), the stored identifier (CIDm) during the address phase (302) of this read access (300).

7. Device according to any one of claims 1 and 3 to 6, in which each identifier (CID) corresponds to a different processor (CPU1, CPU2).

8. Device according to any one of claims 1 and 3 to 7, in which read and write access to the second circuits (CID1, CID2) is impossible.

9. Device according to any one of claims 1 and 3 to 8, in which the bus (BUS) is of the AMBA type.

10. Device according to any one of claims 1 and 3 to 9, in which the identifier (CID) of each processor (CPU1, CPU2) is hard-coded in the second circuit (CID1, CID2) associated with this processor.

11. Device according to any one of claims 1 and 3 to 10, in which the first circuit (CAR) is accessible in read-only mode.

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