SPAD TYPE photodetector

Abstract

The invention relates to a photodetector comprising a SPAD-type photodiode including, within a semiconductor substrate, a first doped region of a first type of conductivity and a second doped region of a second type of conductivity opposite to the first type of conductivity so as to form a PN junction; an extinction transistor including, within the substrate, a channel of the second type of conductivity, a gate electrically isolated from the substrate by a dielectric layer, and a third doped region of the first type of conductivity flush with an upper face of the substrate. The dielectric layer is interposed between the gate and the first doped region, and the channel is delimited by the first doped region and the third doped region. Figure 1

Description

Title of the invention: SP AD TYPE photodetector Technical field

[0001] The field of the invention is that of photodetectors comprising at least one avalanche photodiode for the detection of single photons, also called SPAD photodiode (from the English "Single Photon Avalanche Diode"). The invention also relates to photodetectors comprising a matrix of SPAD photodiodes. STATE OF THE PRIOR ART

[0002] A SPAD photodiode is an extremely sensitive detector capable of detecting a single photon. It essentially consists of a PN junction in a semiconductor layer, reverse-biased at a voltage above its avalanche threshold, also called breakdown voltage. This creates an intense electric field inside the SPAD. A photogenerated carrier is then accelerated by the electric field to a speed sufficient to trigger an impact ionization phenomenon, or avalanche phenomenon. Thus, a single photon is capable of generating a measurable electrical signal in a very short response time.

[0003] Once a signal is detected, it is necessary to interrupt the avalanche and recharge the SPAD photodiode. For this, a quenching circuit is typically used to control the avalanche phenomenon. The quenching circuit can be passive or active. Active circuits allow better control of the avalanche but are however more bulky than passive circuits.

[0004] The simplest passive extinguishing circuit consists of a resistor connected in series with the SPAD photodiode. At the moment of the avalanche, the electric current flowing through the resistor increases rapidly, increasing a potential difference across the resistor by applying Ohm's law, mechanically decreasing the potential difference across the SPAD photodiode. If the resistor is sufficiently resistive, the electric field inside the SPAD photodiode decreases until the avalanche is extinguished. The SPAD photodiode then gradually returns to its initial polarization.

[0005] The resistor may for example be a lightly doped silicon bar 10 μm long, placed at the edge of the SPAD photodiode. The extinction circuit then occupies a large surface area compared to the size of the SPAD photodiode, this is all the more damaging in the case of photodetectors comprising a matrix of SPAD photodiodes. In addition, such a circuit does not allow precise control of the avalanche phenomenon.

[0006] To reduce the surface area of ​​the extinguishing circuit and improve avalanche control, It is possible to replace the resistor with a transistor. Patent application JP 2022-148028 proposes such a solution. Figure 8 of this document illustrates a pixel of a photodetector comprising a SPAD photodiode. The SPAD photodiode comprises, in a substrate, a PN junction defining an avalanche zone. The avalanche zone is at a non-zero distance from an upper face of the substrate. The pixel further comprises a PMOS transistor for quenching the avalanche and recharging the SPAD photodiode. Doped wells of different types isolate the PMOS transistor from the cathode of the photodiode. The drain of the PMOS transistor is connected to the cathode of the photodiode by metal interconnects (Figures 8 and 10). The channel of the PMOS transistor extends along a plane parallel to the upper face of the substrate.

[0007] In this embodiment of the prior art, the extinction circuit still occupies a significant surface area, in particular due to the presence of the doped wells and the arrangement of the channel of the PMOS transistor. There is therefore a need to further reduce the surface area of ​​the extinction circuit. Statement of the invention

[0008] The invention aims to remedy at least in part the drawbacks of the prior art, and more particularly to propose a photodetector comprising a SPAD type photodiode and an extinction circuit which is less bulky than in the prior art.

[0009] For this purpose, the subject of the invention is a photodetector, comprising a SPAD type photodiode and an extinction transistor. The SPAD type photodiode comprises, in a semiconductor substrate, a first doped region of a first conductivity type and a second doped region of a second conductivity type opposite to the first conductivity type so as to produce a PN junction. The extinction transistor comprises, in the substrate, a channel of the second conductivity type, a gate electrically insulated from the substrate by a dielectric layer, and a third doped region of the first conductivity type flush with an upper face of the substrate. The photodetector is such that the dielectric layer is interposed between the gate and the first doped region, and the channel is delimited by the first doped region and the third doped region.

[0010] Some preferred but non-limiting aspects of this photodetector are as follows.

[0011] The gate may extend into the substrate from the top face of the substrate, and the first doped region of the photodiode may be separated from the top face by a non-zero distance.

[0012] The photodiode may further comprise a fourth doped region of the second conductivity type flush with the upper face of the substrate.

[0013] The substrate may comprise a first doped layer and a second layer doped, both of the second conductivity type, such that the second doped layer has a dopant atom concentration different from a dopant atom concentration of the first doped layer, the second doped region may extend into the first doped layer and the channel may extend into the second doped layer.

[0014] The substrate may further comprise a doped upper layer of the second conductivity type, having a doping atom concentration strictly lower than the doping atom concentration of the second doped layer, arranged such that the second doped layer may be interposed between the first doped layer and the doped upper layer, and the fourth doped region may extend into the doped upper layer.

[0015] The third doped region may comprise a first doped zone and a second doped zone of the first conductivity type, the photodetector being able to be such that the first doped zone has a concentration of dopant atoms strictly greater than a concentration of dopant atoms of the second doped zone, and may be included in the second doped zone.

[0016] The dielectric layer can define with the first doped region 201 a plane substantially parallel to the upper face, the first doped region and the gate being able to extend on either side of this plane.

[0017] The PN junction may be ellipsoidal in shape.

[0018] The gate may fill a recess in the substrate and the first doped region may surround the recess.

[0019] The recess may comprise a shoulder and the first doped region may conform to the shoulder.

[0020] The channel may be opposite a portion of the dielectric layer with a thickness of between 7 nm and 20 nm.

[0021] The quenching transistor may belong to a quenching circuit configured to apply a fixed bias voltage VG to the gate.

[0022] The first conductivity type may be an N type, and the second conductivity type may be a P type.

[0023] The photodetector may further comprise a reading circuit electrically connected to the anode of the photodiode.

[0024] The photodetector may be a back-illuminated photodetector.

[0025] The invention also relates to a method of manufacturing this photodetector, optionally including one or more preferred characteristics.

[0026] The manufacturing method comprises the following steps: producing a recess in a substrate; covering the recess with a dielectric layer; filling the recess with a doped polycrystalline semiconductor material of the first conductivity type to obtain a gate electrically insulated from the substrate by the dielectric layer.

[0027] The production of the recess may comprise a first etching of a first cavity from an upper face of the substrate, the first cavity having a bottom and a side wall, a covering of the bottom and the side wall with a protective layer, a removal of the protective layer on a portion of the bottom of the first cavity, while retaining the protective layer on the side wall, a second selective etching with respect to the protective layer of a second cavity from the bottom of the first cavity.

[0028] The method may further comprise a step of doping by diffusion of dopant atoms in the vapor phase between the step of producing the recess and the step of covering the recess with the dielectric layer. Brief description of the drawings

[0029] Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the appended drawings in which:

[0030] [Fig.l] is a schematic sectional view of a photodetector according to a first embodiment comprising a planar type SPAD photodiode;

[0031] [Fig.2] is a top view of a photodetector according to the first or second embodiment;

[0032] [Fig.3] is a schematic sectional view of a photodetector according to a second embodiment comprising a needle-type SPAD photodiode;

[0033] [Fig.4] is an electrical diagram of an electronic circuit comprising a SPAD photodiode according to the first or second embodiment;

[0034] [Fig.5] is a dynamic simulation of the triggering and stopping of an avalanche phenomenon in a photodetector according to the second embodiment.

[0035] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0036] In the figures and in the remainder of the description, the same references represent identical or similar elements. Furthermore, the different elements are not shown to scale so as to enhance the clarity of the figures. Furthermore, the different embodiments and variants are not mutually exclusive and may be combined with each other. Unless otherwise indicated, the terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the limits are included, unless otherwise indicated.

[0037] By “based on”, we mean that the material is a compound formed of at least the same elements of the semiconductor compound of interest.

[0038] Throughout the description, when comparing dopant atom concentrations of two regions or two zones, the average concentrations within these regions are compared. Thus, when it is said that a zone A has a dopant atom concentration greater than a dopant atom concentration of a zone B, it is understood that the average dopant atom concentration within the volume of zone A is greater than the average dopant atom concentration within the volume of zone B.

[0039] The invention relates to a photodetector, as well as to a method for manufacturing such a photodetector. The photodetector comprises a SPAD type photodiode and an extinguishing transistor for extinguishing an avalanche phenomenon in the SPAD photodiode. The transistor is of the NMOS or PMOS type. A common doped region of a semiconductor substrate forms both a cathode (respectively an anode) of the SPAD photodiode and a source (respectively a drain) of the NMOS (respectively PMOS) transistor. Thus the surface area occupied by the SPAD photodiode and transistor assembly is reduced.

[0040] The common doped region of the substrate may be buried, that is to say it is located at a non-zero distance from an upper face of the substrate. In this case, a doped region flush with the upper face of the substrate defines with the common doped region, a channel of the transistor which extends along an axis substantially perpendicular to the upper face. Such a transistor is called a vertical channel transistor. This arrangement makes it possible to further reduce the surface area occupied by the assembly consisting of the SPAD photodiode and the transistor.

[0041] The invention is particularly advantageous for a photodetector comprising a matrix of pixels extending in a detection plane, since it makes it possible to reduce the size of the pixels.

[0042] Particular embodiments will be described relating to a photodetector comprising a SPAD type photodiode and a vertical channel transistor having in common a doped region of a substrate. However, these embodiments can be adapted to include any type of avalanche photodiodes, for example avalanche photodiodes having separate charging and / or acceleration and / or multiplication zones.

[0043] [Fig.l] schematically illustrates a photodetector 10 according to a first embodiment. The photodetector 10 comprises a matrix of pixels extending in a detection plane. For the sake of clarity and to avoid overloading the figure, half of a pixel has been shown in [Fig.l], seen along section AA of [Fig.2]. [Fig.2] schematically shows a top view of the same pixel, in its entirety.

[0044] The photodetector 10 comprises, in a substrate 300, a photodiode 200, an extinction transistor 100 and an isolation trench 305.

[0045] The substrate 300 comprises an upper face 300a and a lower face 300b, substantially planar and parallel to the detection plane. The substrate 300 is based on a semiconductor material, here doped P-type. The photodetector 10 comprises a stack of insulating and conductive layers (not shown), called an interconnection stack, in which metal lines and contacts electrically connected to the photodiode 200 and to the extinction transistor 100 can be formed. When the interconnection stack is arranged on the side of the illumination face of the substrate, the photodetector 10 is called a front side illumination photodetector or FSI photodetector (for Front Side Illumination in English). When the interconnect stack is arranged on the side opposite the illumination face of the substrate, the photodetector 10 is called a back-side illumination photodetector or B SI photodetector (for Back Side Illumination in English).The photodetector 10 of the first embodiment may be a BSI photodetector with an interconnect stack disposed on the side of the upper face 300a.

[0046] Here and for the remainder of the description, a direct three-dimensional orthogonal reference frame (X, Y, Z) is defined, where the X and Y axes form a plane parallel to the upper face 300a of the substrate 300, the X axis being oriented here parallel to an axis of the pixel matrix, and where the Z axis is oriented substantially orthogonal to the upper face 300a of the substrate 300, and is oriented from the lower face 300b towards the upper face 300a. In the remainder of the description, the terms “vertical” and “vertically” are understood as relating to an orientation substantially parallel to the Z axis, and the terms “horizontal” and “horizontally” as relating to an orientation substantially parallel to the (X, Y) plane. Furthermore, the terms “lower” and “upper” are understood as relating to an increasing positioning when moving away from the substrate 300 in the +Z direction.

[0047] The photodiode 200 comprises a first doped region 201 of a first conductivity type and a second doped region 202 of a second conductivity type opposite to the first conductivity type so as to produce a PN junction. The second doped region 202 surrounds the first doped region 201 in a half-space delimited by a plane substantially parallel to the upper face 300a. In this example, the first doped region 201 is of type N and thus forms a cathode of the photodiode 200. The second doped region 202 is therefore of type P.

[0048] Preferably, the first doped region 201 and the second doped region 202 are each ellipsoidal in shape, or hemispherical in the half-space, just like the PN junction. This makes it possible to maximize the volume of the region of the substrate 300 within which a photon is likely to trigger an avalanche, while miniaturizing the photodiode 200. This also helps limit untimely avalanches.

[0049] The photodiode 200 further comprises a fourth doped region 203 of the second conductivity type flush with the upper face 300a of the substrate 300. The fourth doped region 203 occupies a peripheral region of the pixel. Here it is P-doped and defines an anode of the photodiode 200.

[0050] The extinction transistor 100 comprises, in the substrate, a channel 102 interposed between the first doped region 201 and a third doped region 103 of the first conductivity type flush with the upper face 300a of the substrate 300. The channel 102 is of the same conductivity type as that of the substrate 300, therefore P-doped in this example. With the doping types chosen here, the third doped region 103 defines a drain of the transistor and the first doped region 201, a source of the transistor.

[0051] The third doped region 103 may have, as shown here, an annular shape. It advantageously comprises a first doped zone 103a which has a concentration of dopant atoms strictly greater than a concentration of dopant atoms of a second doped zone 103b. The first doped zone 103a is included in the second doped zone 103b, that is to say that the second doped zone 103b surrounds the first doped zone 103a in a plane parallel to the upper face 300a. The second doped zone 103b is interposed between the first doped zone 103a and the fourth doped region 203, thus the electric field is reduced in the vicinity of the upper face 300a and an untimely avalanche in this zone can be avoided.

[0052] The extinction transistor 100 further comprises a gate 105 electrically insulated from the substrate by a dielectric layer 104. The gate 105 is flush with the upper face 300a of the substrate 300 and has, in this example, a substantially cylindrical shape, with an axis parallel to the Z axis. The dielectric layer 104 defines with the first doped region 201 a separation plane substantially parallel to the upper face 300a of the substrate 300, that is to say that there is an interface between the dielectric layer 104 and the first substantially planar doped region 201 which is included in this plane. The first doped region 201 and the gate 105 extend mainly on either side of the separation plane. Furthermore, in a direction of the separation plane, the first doped region 201 has a dimension strictly greater than a dimension of the dielectric layer 104. The separation plane is for example identical to the plane delimiting the half-space.

[0053] The dielectric layer 104 has a portion 104a facing the channel 102, hereinafter called gate oxide 104a. The gate 105 may be metallic or based on a semiconductor material. In the latter case, it is doped with the first type of conductivity or the second type of conductivity, here the gate 105 is of the first type of conductivity. It may comprise a first doped zone 105a which is flush with the upper face 300a of the substrate 300. The part not included in the first doped zone 105a constitutes a second doped zone 105b of the gate 105. The first and second doped zones 105a, 105b are of the same conductivity type which can be the first or the second conductivity type, here of type N. The gate oxide 104a and of the channel 102 is opposite the second doped zone 105b. In addition, the concentration of doping atoms of the first doped zone 105a can be strictly greater than the concentration of doping atoms of the second doped zone 105b.

[0054] The third doped region 103, the gate 105, the first doped region 201 and the second doped region 202 occupy a central region of the pixel. Metal contacts are arranged in contact with the gate 105, the third doped region 103 and the fourth doped region 203, possibly through a passivation layer not shown. The dopant atom concentrations of the first doped area 103a of the drain 103, the first doped area 105a of the gate 105 and the anode 203 are chosen to reduce the contact resistance.

[0055] Advantageously, the substrate 300 comprises a first doped layer 301 in contact with a second doped layer 302, both of the second conductivity type. The second doped region 202 extends into the first doped layer 301 and the channel 102 extends into the second doped layer 302. A concentration of doping atoms in the second doped layer 302 may be different, for example strictly lower, than a concentration of doping atoms in the first doped layer 301. It is thus possible to optimize the resistivity of the channel 102 and the electric field in the photodiode 200 independently of each other. Even more advantageously, the concentration of doping atoms of the first doped layer 301 varies gradually along the Z axis so as to attract the photogenerated charges towards the second doped region 202.

[0056] Also advantageously, the substrate 300 comprises a doped upper layer 303 of the second conductivity type in which the third doped region 103, the first and second doped zones 103a, 103b when they are present, and the fourth doped region 203 extend. The upper layer 303 is lightly doped. For example, it has a concentration of doping atoms strictly lower than the concentration of doping atoms of the second doped layer 302. This makes it possible to reduce the electric field in the vicinity of the upper face 300a and thus to avoid any untimely avalanche that may occur in this zone.

[0057] In this example, the first and second doped layers 301, 302 are made of P-doped silicon. The concentration of doping atoms in the layer 301 is between 1015 and 1018 atoms / cm3, for example equal to 9.1016 atoms / cm3. That of the second doped layer 302 is between 1015 and 1018, for example equal to 4.1016 atoms / cm3. That of the upper doped layer 303 is between 1014 and 1017, for example equal to 4.1016 atoms / cm3. example equal to 1015 atoms / cm3.

[0058] The first doped layer 301 has for example a thickness between 1 pm and 15 pm. The second doped layer 302 has a thickness between 500 nm and 5 pm, preferably between 1 and 4 pm. The upper doped layer 303 has a thickness between 100 nm and 500 nm.

[0059] The fourth doped region 203 has a concentration of dopant atoms of between 1017 and 5.1020 atoms / cm3. That of the first doped region 201 is between 1017 and 5.1020 atoms / cm3. That of the second doped region 202 is between 1016 and 1020 atoms / cm3. That of the first doped zone 103a is between 1017 and 5.1020 atoms / cm3. That of 103b is between 1016 and 1019 atoms / cm3.

[0060] The first and second doped zones 105a, 105b are here made of polycrystalline silicon. The second doped zone 105b has a concentration of dopant atoms of between 1017 and 5.1020. That of the first doped zone 105a is between 1017 and 5.1020 atoms / cm3.

[0061] The gate 105 has a section perpendicular to the Z axis with a diameter of between 100 nm and 1 pm, for example equal to 600 nm. The gate oxide 104a has a thickness measured in a direction parallel to the upper face 300a of the substrate 300 of between 2 nm and 100 nm, preferably between 2 and 20 nm, for example equal to 7 nm. The length of the channel 102 measured in a direction parallel to the Z axis is between 500 nm and 5 pm, preferably between 1 pm and 4 pm, for example equal to 1 pm.

[0062] The first and second doped layers 301, 302 and the upper doped layer 303 are for example in-situ doped epitaxial layers.

[0063] The pixels are separated laterally from each other by isolation trenches or walls 305 extending vertically through the substrate 300, for example over the entire thickness of the first doped layer 301. The isolation trenches 305 are, for example, capacitive isolation trenches, for example of the CDTI (Capacitive Deep Trench Isolation) type, each comprising a core or central wall made of an electrically conductive material, for example doped polycrystalline silicon, and a lateral coating made of an electrically insulating material, for example silicon oxide. Alternatively, the isolation trenches 305 are insulating trenches entirely filled with a dielectric material, for example silicon oxide, for example trenches of the DTI (Deep Trench Isolation) type.The isolation trenches 305 are for example formed from the upper face 300a of the substrate 300.

[0064] [Fig. 3] schematically illustrates a photodetector 20 according to a second embodiment. For the same reasons explained in connection with [Fig. 1], we have shown half of a pixel in [Fig.3], seen along section AA of [Fig.2]. [Fig.2] is also a schematic top view of a pixel of the second embodiment, taken in its entirety. Only the differences from the first embodiment will be described here. The photodetector 20 of the second embodiment may be a BSI detector with an interconnect stack arranged on the upper face 300a of the substrate 300.

[0065] The substrate 300 accommodates a non-through recess. The first doped region 201 surrounds this recess on a lower part, that is to say that the recess has a bottom and a side wall, and the first doped region 201 covers the bottom and a lower part of the side wall. The recess extends deep into the substrate 300, typically to a depth of several micrometers, for example a depth of between 5 and 25 μm. It is coated with the dielectric layer 104 and filled by the gate 105. The gate 105 therefore extends from the upper face 300a of the substrate 300 to the bottom of the recess.

[0066] When the gate 105 is based on a semiconductor material, it may comprise a first doped zone 105a of the first conductivity type or of the second conductivity type, here of the first conductivity type, which is flush with the upper face 300a of the substrate 300. The part not included in the first doped zone 105a may comprise one or more different doped zones of the first conductivity type. For example, the gate oxide 104a may be opposite a second doped zone 105b. The first doped region 201 may be opposite the second doped zone 105b and / or a third doped zone 105c not shown. The concentrations of dopant atoms of doped zones 105a, 105b, 105c may be different, for example the concentration of dopant atoms of the first doped zone 105a may be strictly greater than the concentration of dopant atoms of the second doped zone 105b when it is present.The third 105c doped region can be a dielectric.

[0067] The recess may comprise a shoulder, that is to say that in the vicinity of a plane parallel to the upper face 300a, the area of ​​a section of the recess parallel to the upper face 300a increases rapidly in the +Z direction. In this case, the area of ​​a section of the first doped region 201 in this plane is strictly greater than the maximum area of ​​the section of the recess parallel to the upper face 300a in the vicinity of this plane. Preferably, the first doped region 201 matches the shoulder.

[0068] The first doped region 201 and the second doped region 202 may rest, as shown here, on a doped lower layer 304 of the first conductivity type or the second conductivity type. The doped lower layer 304 has a lower dopant atom concentration than the first doped region 201 and the second doped region 202. The second doped region 202 extends laterally from the first doped region 201 to the isolation trench 305.

[0069] [Fig.4] is an electrical diagram of an electronic circuit comprising a photodiode 200 according to the first or second embodiment, in the case where the first conductivity type is an N type, and the second conductivity type is a P type.

[0070] The electronic circuit further comprises a power supply circuit 401, a switching off circuit 402 and a reading circuit 403.

[0071] The extinguishing circuit 402 comprises an extinguishing transistor 100 according to the first or second embodiment. It is configured to apply a potential VG to the gate 105 of the extinguishing transistor 100. The potential VG is here a fixed potential. Alternatively, the potential VG may be variable, for example controlled by a drain current iD of the extinguishing transistor 100. In this case, the extinguishing circuit 402 is capable of applying a first potential VG for which the channel of the extinguishing transistor 100 is open during the avalanche and a second potential VG for which the channel of the extinguishing transistor 100 is closed as soon as the avalanche stops, for a duration of a few nanoseconds.

[0072] The power supply circuit 401 is configured to apply a fixed potential VD to the drain of the extinguishing transistor 100. The source of the extinguishing transistor 100 is, for its part, electrically connected to the cathode of the photodiode 200, which is consistent with the explanations given in connection with the first and second embodiments. The anode of the photodiode 200 is electrically connected to a source of potential V A-

[0073] The reading circuit 403 is electrically connected to the anode of the photodiode 200. It is intended to measure and / or detect a signal emitted by the photodiode 200 following the triggering of an avalanche phenomenon. It may comprise, for example, a capacitor connected in series with a resistor, or an inverter.

[0074] For example, the anode of the photodiode 200 is electrically connected to ground; the potential VA is then equal to 0 V. The potential VG is fixed and is between 18.0 and 18.2 V, for example equal to 18.2 V. The potential VD is greater than the breakdown voltage of the photodiode 200, for example greater than the breakdown voltage of 2 V, for example equal to 18.6 V.

[0075] Alternatively, the gate 105 of the extinguishing transistor 100 can be connected to ground, so that VG is equal to 0 V. The potential VD is equal to -0.4 V and the potential VA is equal to -18.6 V.

[0076] In the absence of photons, the extinction transistor 100 is blocked. The cathode of the photodiode 200 and the source of the extinction transistor 100, which correspond to the first doped region 201, are at a potential Vs close to VD. The gate 105 is at a potential VG close to Vs, for example VG differs from Vs by a voltage close to the threshold voltage of the extinction transistor 100, thus the electrical resistance of the channel 102 has a high value R;. A potential difference Vs - VA then creates an intense internal electric field inside the photodiode 200. When an incident photon generates an electron-hole pair in an absorption region of the photodiode 200, the electron is accelerated by the internal electric field until it reaches a speed sufficient to trigger an avalanche phenomenon. The electron thus generates many other electrons which are collected by the first doped region 201, generating a drain current iD. The resistance of the channel 102 R; being high, the potential Vs decreases rapidly. The potential difference Vs - VA then decreases; it passes below the breakdown voltage and the avalanche stops.The drop in Vs also causes a decrease in the electrical resistance of channel 102 until it reaches a low value Ra allowing the photodiode 200 to be recharged, so that the potential Vs and the electrical resistance of channel 102 gradually increase until they return to their initial values, before the avalanche is triggered.

[0077] Using simulation tools known to those skilled in the art, such as for example the TCAD Sentaurus® simulator from Synopsys, it is possible to adjust the parameters of the extinction transistor 100 to adjust the high and low values ​​R;, Ra of the electrical resistance of the channel 102, and thus control the avalanche in the photodiode 200. For example, it is possible to adjust: the thickness of the gate oxide 104a, the length of the channel 102, the dopant atom concentrations of the channel 102 and the gate 105.

[0078] [Fig. 5] is a dynamic simulation of the triggering and stopping of an avalanche phenomenon in a photodetector according to the second embodiment. Here, the parameters of the NMOS type extinguishing transistor 100 are chosen so as to extinguish an avalanche in the photodiode 200. In particular, the thickness of the gate oxide 104a is equal to 7nm, the length of the channel 102 is equal to 1 pm, the concentration of dopant atoms of the channel 102 is equal to 4.1016 atoms / cm3 and the concentration of dopant atoms of the gate 105 is equal to 2.1020 atoms / cm3.

[0079] Here, the variation of the drain current iD in amperes as a function of time in ns (nanoseconds) is represented. The scale used is semi-logarithmic on the ordinate. Curve A is obtained for a gate potential VG equal to 18.0 V, curve B for a potential VG equal to 18.1 V, curve C for a potential VG equal to 18.2 V and curve D for a potential VG equal to 18.3 V. Curves A, B and C show an extinction of the avalanche and a recharging of the photodiode 200. On curve D, the drain current iD has a series of peaks before settling at a high threshold for which the avalanche is maintained, including in the channel 102 of the extinction transistor 100.

[0080] A manufacturing method that may be suitable for producing a photodetector according to the first embodiment is now described.

[0081] In a first step, a planar photodiode 200 is produced in a first epitaxially grown doped layer 301, using conventional process steps of the semiconductor industry, such that a first doped region 201 is flush with an upper face of the first doped layer 301. An example of such a sequence of process steps is taught in patent application FR3121282 A1, in connection with figures 3 to 9. The first doped layer 301 is based on P-doped silicon during epitaxial growth.

[0082] During a second step, a second doped layer 302 is grown by epitaxy on the upper face of the first doped layer 301. The second doped layer 302 is based on P-doped silicon during epitaxial growth.

[0083] During a third step, a doped upper layer 303 is grown by epitaxy on a face opposite the first doped layer 301 of the second doped layer 302, to produce a stack of a substrate 300. The stack comprises the first and second doped layers 301, 302 and the doped upper layer 303. The substrate 300 has an upper face 300a belonging to the doped upper layer 303. The doped upper layer 303 is based on P-doped silicon during epitaxial growth.

[0084] During a fourth step, a recess, for example cylindrical, is etched from the upper face 300a of the substrate 300, so as to pass through the doped upper layer 303 and the second doped layer 302. The recess has a bottom substantially parallel to the upper face 300a, and a side wall substantially perpendicular to the bottom. The bottom is in contact with the first doped region 201 and entirely included therein.

[0085] In a fifth step, a dielectric layer 104 is deposited conformally in the recess to cover the bottom and the side wall of the recess, for example by CVD or LPCVD. Alternatively, thermal oxidation may be used. On the side wall of the recess, the dielectric layer 104 has a thickness of between 2 nm and 100 nm, preferably between 2 and 20 nm, for example equal to 7 nm.

[0086] During a sixth step, the recess is filled with N-type doped polycrystalline silicon to produce a gate 105 of an extinction transistor 100 whose source comprises the first doped region 201.

[0087] During a seventh step, insulation trenches 305 are made passing through the doped upper layer 303, the second doped layer 302 and the first doped layer 301.

[0088] A seventh step comprises implantations of doping atoms to produce a first doped zone 105a of the gate 105, a first doped zone 103a and a second doped zone 103b to produce a drain of the extinction transistor 100, a fourth doped region 203 to produce an anode of the photodiode 200, all flush with the upper face 300a.

[0089] A manufacturing method suitable for producing a photodetector according to the second embodiment is now described.

[0090] In a first step, a stack of three silicon layers is grown by epitaxy. The stack comprises, in order, a first doped layer 301 P, a second doped layer 302 P having a doping atom concentration strictly lower than a doping atom concentration of the first doped layer 301 and an upper doped layer 303 having a doping atom concentration strictly lower than a doping atom concentration of the second doped layer 302. The three layers are based on silicon.

[0091] During a second step, a first cavity, for example cylindrical, is etched from an upper face 300a of the stack, so as to pass through the doped upper layer 303 and at least part of the second doped layer 302. The first cavity has a bottom substantially parallel to the upper face 300a, and a side wall substantially perpendicular to the bottom.

[0092] In a third step, a protective layer is conformally deposited in the first cavity to cover the bottom and sidewall of the first cavity, for example by CVD or LPCVD. Alternatively, thermal oxidation may be used. The protective layer has a thickness of between 5 nm and 50 nm.

[0093] In a fourth step, a through opening is etched in the protective layer until it reaches the bottom of the first cavity, while preserving a non-zero thickness of the protective layer on the side wall of the first cavity.

[0094] A fifth step comprises a directional etching of the first doped layer 301 selectively with respect to the protective layer, in order to obtain a second cavity in the first doped layer 301. The second cavity extends in depth into a portion of the first doped layer 301, typically to a depth of several micrometers, for example a depth of between 5 and 25 μm. It has a bottom substantially parallel to the upper face 300a, and a side wall substantially perpendicular to the bottom. The first and second cavities form a recess of a substrate 300 which comprises the stack.

[0095] A sixth step comprises doping by vapor diffusion of dopant atoms, for example phosphorus or arsenic, to obtain a first doped region 201 of type N surrounding the second cavity, and preferably a lower part of the first cavity. The first doped region 201 is intended to be a cathode of a photodiode 200.

[0096] In a seventh step, a dielectric coating is conformally deposited in the first cavity and the second cavity to cover the bottoms and walls of the first and second cavities, for example by CVD or LPCVD. Alternatively, thermal oxidation may be used to obtain the dielectric coating. This step may be preceded by removal of the protective layer. At the end of this step, the recess is coated with a dielectric layer 104 which comprises the protective layer and the dielectric coating if the protective layer is dielectric and has not been removed. Otherwise, the dielectric layer 104 is the dielectric coating. At the end of this step, the dielectric layer 104 has a portion 104a facing the second doped layer 302 which has a thickness of between 2 nm and 100 nm, preferably between 2 and 20 nm, for example equal to 7 nm.

[0097] During an eighth step, the recess is filled with N-type doped polycrystalline silicon to produce a gate 105 of an extinction transistor 100 whose source comprises the first doped region 201.

[0098] During a ninth step, insulation trenches 305 are made passing through the upper doped layer 303, the first doped layer 301 and the second doped layer 302.

[0099] A tenth step comprises implantations of doping atoms to produce a first doped zone 105a of the gate 105, a first doped zone 103a and a second doped zone 103b to produce a drain of the extinction transistor 100, a fourth doped region 203 to produce an anode of the photodiode 200, all flush with the upper face 300a.

[0100] Particular embodiments have just been described. Different variants and modifications will be apparent to those skilled in the art. It is notably possible to reverse all types of doping. For N-type doping in silicon, it is for example possible to use phosphorus, arsenic, antimony, or bismuth. For P-type doping in silicon, it is for example possible to use boron, aluminum, gallium or indium.

Claims

Claims

1. Photodetector (10, 20), comprising: • a SPAD type photodiode (200) comprising, in a semiconductor substrate (300), a first doped region (201) of a first conductivity type and a second doped region (202) of a second conductivity type opposite to the first conductivity type so as to produce a PN junction; • an extinction transistor (100) comprising, in the substrate (300), • a channel (102) of the second conductivity type, • a gate (105) electrically insulated from the substrate (300) by a dielectric layer (104), • a third doped region (103) of the first conductivity type flush with an upper face (300a) of the substrate (300); characterized in that • the dielectric layer (104) is interposed between the gate (105) and the first doped region (201), • the channel (102) is delimited by the first doped region (201) and the third doped region (103).

2. The photodetector (10, 20) of claim 1, wherein the gate (105) extends into the substrate (300) from the top face (300a) of the substrate (300), and the first doped region (201) of the photodiode (200) is separated from the top face (300a) by a non-zero distance.

3. Photodetector (10, 20) according to claim 2, wherein the photodiode (200) further comprises a fourth doped region (203) of the second conductivity type flush with the upper face (300a) of the substrate (300).

4. A photodetector (10, 20) according to claim 2 or 3, wherein the substrate (300) comprises a first doped layer (301) and a second doped layer (302), both of the second conductivity type, such that the second doped layer (302) has a dopant atom concentration different from a dopant atom concentration dopant atonicities of the first doped layer (301), the second doped region (202) extends into the first doped layer (301) and the channel (102) extends into the second doped layer (302).

5. Photodetector (10, 20) according to claims 3 and 4, wherein the substrate (300) further comprises a doped upper layer (303) of the second conductivity type, having a doping atom concentration strictly lower than the doping atom concentration of the second doped layer (302), arranged such that the second doped layer (302) is interposed between the first doped layer (301) and the doped upper layer (303), and the fourth doped region (203) extends into the doped upper layer (303).

6. A photodetector (10, 20) according to claim 5, wherein the third doped region (103) comprises a first doped area (103a) and a second doped area (103b) of the first conductivity type, the photodetector being such that the first doped area (103a) has a dopant atom concentration strictly greater than a dopant atom concentration of the second doped area (103b), and is included in the second doped area (103b).

7. Photodetector (10) according to any one of claims 2 to 6, in which the dielectric layer (104) defines with the first doped region 201 a plane substantially parallel to the upper face (300a), the first doped region (201) and the gate (105) extending on either side of this plane.

8. The photodetector (10) of claim 7, wherein the PN junction is ellipsoidal in shape.

9. The photodetector (20) of any one of claims 2 to 6, wherein the gate (105) fills a recess in the substrate (300) and the first doped region (201) surrounds the recess.

10. The photodetector (20) of claim 9, wherein the recess comprises a shoulder and the first doped region (201) conforms to the shoulder.

11. Photodetector (10, 20) according to any one of the preceding claims, in which the channel (102) is opposite a portion (104a) of the dielectric layer (104) with a thickness of between 7 nm and 20

12. llili. Photodetector (10, 20) according to any one of the preceding claims in which the extinction transistor (100) belongs to an extinction circuit (402) configured to apply a polarization voltage- fixed VG grid (105).

13. A photodetector (10, 20) according to any preceding claim wherein the first conductivity type is an N type, and the second conductivity type is a P type.

14. Photodetector (10, 20) according to the preceding claim further comprising a reading circuit (403) electrically connected to the anode of the photodiode (200)

15. A photodetector (10, 20) according to any preceding claim wherein the photodetector (10, 20) is a backside illumination photodetector.

16. Method of manufacturing a photodetector according to any one of claims 1 to 15, comprising the following steps: • producing a recess in a substrate (300), • covering the recess with a dielectric layer (104) • filling the recess with a doped polycrystalline semiconductor material of the first conductivity type to obtain a gate (105) electrically insulated from the substrate (300) by the dielectric layer (104).

17. Manufacturing method according to the preceding claim in which the production of the recess comprises • a first etching of a first cavity from an upper face (300a) of the substrate (300), the first cavity having a bottom and a side wall, • a covering of the bottom and the side wall with a protective layer, • a removal of the protective layer on a part of the bottom of the first cavity, while retaining the protective layer on the side wall, • a second selective etching with respect to the protective layer of a second cavity from the bottom of the first cavity, the method further comprising: • a doping step by diffusion of dopant atoms in phase vapor between the step of making the recess and the step of covering the recess with the dielectric layer (104).

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