Electronic device

Abstract

Electronic Device This description relates to a method for manufacturing a memory comprising at least one first phase-change memory cell (12a), each first cell (12a) comprising a resistive element (24), a first metallic layer (25), and a second layer (26) of a phase-change material, the first layer (25) being located between the resistive element (24) and the second layer (26), the method comprising: a. the formation of a layer (20) comprising the resistive element (24); b. the formation of a third metallic layer on the layer (20); c. the etching of the third layer; and d. the formation of the second layer (26). Figure for the abstract: Fig. 1

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more specifically to electronic devices comprising phase change memories and their manufacturing methods. Prior art

[0002] A phase change material is a material having the ability to change its crystalline state under the effect of heat and more particularly to switch between a crystalline state and an amorphous state, more highly resistive than the crystalline state. This phenomenon is used to define two memory states, for example 0 and 1, differentiated by the resistance measured across the phase change material.

[0003] There is a need to improve electronic chips comprising a memory circuit comprising memory cells based on a phase change material, and their manufacturing methods. Summary of the invention

[0004] One embodiment provides a method of manufacturing a memory comprising at least one first phase change memory cell, each first cell comprising a resistive element, a first metal layer and a second layer of a phase change material, the first layer being located between the resistive element and the second layer, the method comprising: a. forming a level comprising the resistive element; b. forming a third metal layer on the level; c. etching the third layer; and then d. forming the second layer.

[0005] According to one embodiment, the first metal layer is made of TiSiN, TiN, or TaN, the third metal layer being made of the same material as the first layer.

[0006] According to one embodiment, the device comprises at least two first cells, the first metal layers of different first cells being separated from each other.

[0007] According to one embodiment, the first metal layer is in contact with the resistive element and with the second layer made of a phase change material.

[0008] According to one embodiment, the device comprises at least one second phase change memory cell comprising a resistive element and a second layer of a phase change material, the second layer is in contact with the resistive element, the method comprising etching the first layer at the em- placements of the second cells.

[0009] According to one embodiment, the device comprises rows of memory cells, the cells of the same row comprise a second layer made of a common phase change material.

[0010] According to one embodiment, the memory cells each comprise a portion of the second layer made of a phase change material, the portions of the second layer made of a phase change material of the different cells being separated from each other.

[0011] According to one embodiment, the method comprises a step e., subsequent to step d. in which the portions of the first level and of the second layer in a phase change material located around the memory cells are etched.

[0012] According to one embodiment, the device comprises at least two lines of memory cells, the method comprising a step e., subsequent to step d., in which the portions of the first level and of the second layer of a phase change material located between the two lines of memory cells are etched.

[0013] According to one embodiment, the device comprises at least two columns of memory cells, the method comprising a step f. subsequent to step e., in which the portions of the first level and of the second layer of a phase change material located between the two columns of memory cells are etched.

[0014] According to one embodiment, step c. comprises etching the third metal layer so as to form the first metal layer.

[0015] According to one embodiment, step c. comprises etching the third metal layer so as to form strips each comprising the first layers of first cells of the same column of memory cells.

[0016] According to one embodiment, step e. comprises etching the strips so as to form the first metal layers. Brief description of the drawings

[0017] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0018] [Fig.l] represents an embodiment of an electronic device;

[0019] [Fig.2] illustrates the operation of the device of [Fig.l];

[0020] [Fig.3] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0021] [Fig.4] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0022] [Fig.5] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0023] [Fig.6] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0024] [Fig.7] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0025] [Fig.8] illustrates several possible cases of alignment;

[0026] [Fig.9] represents a device resulting from a step of a manufacturing process of the device of [Fig.l];

[0027] [Fig. 10] represents a device resulting from a step of another method of manufacturing another device of [Fig.l];

[0028] [Fig.l 1] represents a device resulting from a step of another method of manufacturing the device of [Fig.l]; and

[0029] [Fig. 12] shows another embodiment of an electronic device. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] [Fig. 1] represents an embodiment of an electronic device 10. More specifically, [Fig. 1] represents two sectional views 1A and 1B. View 1A corresponds to a sectional view along plane AA of view 1B and view 1B corresponds to a sectional view along plane BB of view 1A. Planes AA and BB are preferably substantially perpendicular.

[0036] The device 10 comprises a memory region. Said memory region comprises at least one memory cell 12a, 12b, preferably several memory cells 12a, 12b. The memory cells 12a, 12b are phase change memory cells. The device 10 comprises a first type of memory cells 12a. The device 10 comprises at least one cell 12a. [Fig. 1] represents three cells 12a in view 1A and three cells 12a in view 1B. The device 10 comprises for example a second type of memory cells 12b. [Fig. 1] comprises a cell 12b, in view 1A.

[0037] The memory cells 12a, 12b are arranged in a memory matrix. View 1A represents memory cells of the same row of the memory matrix. Similarly, view 1B represents memory cells of the same column of the memory matrix. The row of cells 12a, 12b of view 1A thus extends in a first direction X. The column of cells 12a, 12b of view 1B thus extends in a second direction Y, for example substantially orthogonal to the direction X. The memory matrix is ​​a "wall" type structure, that is to say that the cells of the same rows are located in the same wall.

[0038] The device 10 comprises a level 14. The level 14 comprises an insulating layer 16. The insulating layer 16 is for example made of silicon oxide or silicon nitride. The level 14 further comprises conductive contacts 18, for example made of metal, for example tungsten. The conductive contacts extend for example over the entire height of the layer 16. One end of each conductive contact 18 is flush with an upper face of the layer 16. The device 10 comprises at least as many contacts 18 as there are memory cells 12. Each memory cell 12a, 12b is located on a contact 18.

[0039] Each row of memory cells comprises a level 20. The levels 20 of the different rows are separated from each other. The levels 20 of the different rows are thus not in contact.

[0040] Each level 20 comprises an insulating layer 22, for example made of silicon oxide. Each insulating layer 22 extends over the upper face of the layer 16 and over the upper ends of contacts 18, in particular of the contacts 18 corresponding to the memory cells of the row.

[0041] Each level 20 further comprises conductive elements 24. Each level 20 preferably comprises as many elements 24 as cells 12. Each cell 12a, 12b comprises an element 24. The elements 24 correspond to resistive elements. The elements 24 correspond to heating elements. The elements 24 have for example an L shape in the plane of view 1A. The elements 24 comprise a vertical part extending from the end of the contact 18 corresponding to the memory cell of the element 24 to the upper face of the layer 22. Thus, the end upper end of the vertical part is flush with the upper face of the layer 22 and the lower end of the vertical part is in contact with the contact 18. The element 24 comprises for example a horizontal part in contact with the lower end of the horizontal part and extending at least partially, preferably entirely, over the upper end of the contact 18.

[0042] Each cell 12a comprises a layer 25. Each layer 25 is located on the upper face of the level 20. More precisely, the layer 25 of each cell 12a is located so as to be in contact with the upper end of the element 24 of the corresponding memory cell and with the layer 22. Each layer 25 is in contact with only one element 24, that is to say the element 24 of the memory cell comprising the layer 25. The layers 25 are separated from each other.

[0043] The layer 25 preferably has a dimension in the Y direction substantially equal to the dimension of the upper face of the layer 22. The layer 25 is made of a conductive material, preferably a highly resistive metal, for example TiSiN, TiN, or TaN.

[0044] Each row of memory cells further comprises a layer 26 made of a phase change material. The layer 26 is for example made of an alloy of germanium, antimony and tellurium. The layer 26 is for example made of an alloy of germanium, antimony, tellurium and selenium. The layer 26 may for example comprise dopants, for example arsenic, indium, carbon or nitrogen. Each layer 26 extends in the direction of the rows of the corresponding memory matrix. Each layer 26 extends over the layers 25 and the level 20 of the corresponding row. Thus, each layer 26 covers, and preferably is in contact with, the layers 25 and the level 20. More precisely, each layer 26 covers, for example entirely, and preferably is in contact with, the layers 25 of the memory cells 12a of the corresponding row and the ends of the elements 24 of the memory cells 12b of the corresponding row.Each layer 26 preferably completely covers the upper face of the layer 22.

[0045] The layers 25 of the same row of cells are separated from each other by portions of the layer 26.

[0046] Each row of memory cells further comprises a conductive layer 28. Layer 28 is preferably made of a metal. Layer 28 corresponds to an electrode of the memory cell. Layer 28 extends over the upper face of layer 26. Layer 28 preferably completely covers the upper face of layer 26. Layer 28 is preferably in contact with layer 26, preferably at all points.

[0047] Each row of memory cells further comprises an insulating layer 30. Layer 30 corresponds to a passivation layer. Layer 30 extends over the upper face of layer 28. Layer 30 preferably completely covers the upper face upper layer 28. Layer 30 is preferably in contact with layer 28, preferably at all points.

[0048] The device 10 further comprises a layer 32. The layer 30 is made of an insulating material, for example silicon nitride. The layer 32 conformally covers the structure described above. In other words, the layer 32 covers the stacks of layers of the rows of the matrix. In other words, each stack, comprising a level 20, layers 25, and layers 26, 28, 30, is conformally covered by the layer 32. The layer 32 thus covers the upper face of the layer 30 and the lateral faces of the layers 22, 26, 28, 30 and the elements 24. The layer 32 may also cover the lateral faces of at least some layers 25. The layer 32 further covers the portions of the upper face of the level 14 located between the stacks.

[0049] [Fig. 2] illustrates the operation of the device of [Fig. 1]. More specifically, [Fig. 2] is a sectional view in the plane of view 1A, illustrating four memory cells, one cell 12b and three cells 12a, in different programming states.

[0050] The cells 12b are binary memory cells. In other words, the cells 12b can be programmed to contain one of the first and second values. In other words, the portion of the layer 26 corresponding to each cell 12b can be in a highly resistive state, the amorphous state, and in a more weakly resistive state, the crystalline state, illustrated in [Fig.2] by the formation of a crystalline zone 34 delimited by dotted lines. The programming of each cell 12b therefore corresponds to the transition from one of the two states to the other or vice versa. It is not possible to program a third value, different from the first and second values.

[0051] The cells 12a are cells that can be programmed to contain one of at least three values. Thus, depending on the current flowing through each cell, i.e. depending on the temperature applied to the layer 26, the crystalline region obtained can have different sizes, corresponding to different resistivities. Thus, in the example of [Fig.2], the cells 12a can correspond to four different values, including three values ​​corresponding to the formation of a crystalline region, the three crystalline regions being delimited by dotted lines.

[0052] Figures 3 to 7 and 9 illustrate preferably successive steps of a method of manufacturing the device of [Fig.l].

[0053] [Fig. 3] represents a device resulting from a step of a method of manufacturing the device of [Fig. 1]. More precisely, [Fig. 3] represents two sectional views 3A and 3B. View 3A corresponds to a sectional view along plane AA of view 3B and view 3B corresponds to a sectional view along a plane BB of view 3A. Planes AA and BB are preferably substantially perpendicular.

[0054] During this step, level 14 is formed. In other words, layer 16 is formed, for example on an upper face of a substrate not shown. The contacts 18 are then formed in the layer 16. For example, the contacts 18 pass through the layer 16 so as to be flush with the upper face of the layer 16 and to reach the substrate not shown.

[0055] The step of [Fig. 3] further comprises the formation of the level 20. The formation of the level 20 comprises, for example, the formation of an insulating layer of thickness substantially equal to the thickness of the layer 22 and, for example, made of the material of the layer 22, the formation of a cavity, one side wall of which extends over the contacts 18 of one column of the memory matrix and an opposite side wall of which extends over the contacts 18 of another column of the memory matrix. A conductive layer made of the material of the elements 24 is formed conformally on the structure. Spacers made of an insulating material, for example the material of the layer 22, are formed on the walls of the layer so as to cover the locations of the elements 24. The portions of the conductive layer not protected by the spacers are then removed, forming the elements 24. The cavity is then filled, for example with the material of the layer 22, so as to form the layer 22.

[0056] [Fig. 4] represents a device resulting from a step of a method of manufacturing the device of [Fig. 1]. More precisely, [Fig. 4] represents two sectional views 4A and 4B. View 4A corresponds to a sectional view along plane AA of view 4B and view 4B corresponds to a sectional view along a plane BB of view 4A. Planes AA and BB are preferably substantially perpendicular.

[0057] During this step, a layer 42 is formed on the structure. More precisely, the layer 42 is formed on the level 20. Thus, the layer 42 covers, preferably entirely, the upper face of the layer 22 and the upper ends of the elements 24. The layer 42 covers at least the upper ends of the elements 24 corresponding to the cells 12a.

[0058] The layer 42 is made of the material of the layers 25. The thickness of the layer 42 is substantially equal to the thickness of the layers 25.

[0059] [Fig. 5] represents a device resulting from a step of a manufacturing method of the device of [Fig. 1]. More specifically, [Fig. 5] represents two sectional views 5A and 5B. View 5A corresponds to a sectional view along plane AA of view 5B and view 5B corresponds to a sectional view along a plane BB of view 5A. Planes AA and BB are preferably substantially perpendicular.

[0060] The step of [Fig.5] comprises the etching of layer 42 so as to form layers 25. The formation of layers 25 preferably comprises the etching of only layer 42. The etching of layer 42 is carried out before the formation of layer 26 of phase change material.

[0061] The etching of layer 42 comprises, for example, the formation of masks of etching not shown at the locations of layers 25, so as to protect the portions of layer 42 constituting layers 25, and the etching of layer 42 around the etching masks.

[0062] Alternatively, the etching of the layer 42 may comprise the formation of first etching masks extending in the direction of the rows of the memory matrix and each covering the portions of the layer 42 corresponding to the layers 25 of the row. The etching step then comprises the etching of the layer 42 around the first masks. The step further comprises the formation of second etching masks extending in the direction of the columns of the memory matrix and each covering the portions of the layer 42 corresponding to the layers 25 of the column. The etching step then comprises the etching of the layer 42 around the second masks.

[0063] [Fig. 6] represents a device resulting from a step of a manufacturing method of the device of [Fig. 1]. More specifically, [Fig. 6] represents two sectional views 6A and 6B. View 6A corresponds to a sectional view along plane AA of view 6B and view 6B corresponds to a sectional view along a plane BB of view 6A. Planes AA and BB are preferably substantially perpendicular.

[0064] During this step, layers 44, 46, 48 are formed on the structure.

[0065] Layer 44 is made of the material of layers 26. The thickness of layer 44 is preferably substantially equal to the thickness of the layers 26. The layer 44 preferably covers the entire structure. More precisely, the layer 44 preferably covers the entire level 20 and the layers 25. Thus, all the layers 25 and the upper ends of the elements 24 of the cells 12b are covered, and preferably in contact with the layer 44. The layer 44 is common to all the lines.

[0066] The layer 46 is made of the material of the layers 28. The thickness of the layer 46 is preferably substantially equal to the thickness of the layers 28. The layer 46 covers, preferably entirely, the layer 44. The layer 46 is preferably in contact with the layer 44.

[0067] The layer 48 is made of the material of the layers 30. The thickness of the layer 48 is preferably substantially equal to the thickness of the layers 30. The layer 48 covers, preferably entirely, the layer 46. The layer 48 is preferably in contact with the layer 46.

[0068] [Fig. 7] represents a device resulting from a step of a method of manufacturing the device of [Fig. 1]. More precisely, [Fig. 7] represents two sectional views 7A and 7B. View 7A corresponds to a sectional view along plane AA of view 7B and view 7B corresponds to a sectional view along a plane BB of view 7A. Planes AA and BB are preferably substantially perpendicular.

[0069] The step of [Fig.7] includes the formation of the memory cell lines. More precisely Specifically, [Fig.7] comprises etching level 20, and layers 44, 46, 48 between the memory cell rows so as to form levels 20 and layers 26, 28, 30 of the memory cell rows.

[0070] The formation of the lines comprises for example the formation of etching masks, each etching mask being located opposite the portions of the level 20 and the layers 44, 46, 48 corresponding to a line of the memory matrix. An etching step, or several successive etching steps, is then carried out so as to form the lines. The etching is preferably configured to reach the upper face of the level 14. The etching step of [Fig.7] preferably does not include the etching, even partial, of the layers 25.

[0071] One could have chosen not to etch layer 42 of [Fig. 4] before the formation of layer 26. Layer 42 would then be etched during the step of [Fig. 7]. However, the etching process of the layer material also allows the etching of the material of layer 26, the etching rate of layer 26 being much higher than the etching rate of layer 42. Before level 20 can be etched, the etching of layer 42 would have to be carried out. However, during the etching of layer 42, the etching process would cause the lateral etching of layer 26, which would decrease the efficiency of the memory cells and increase the variability between cells.

[0072] [Fig. 8] illustrates several possible alignment cases. [Fig. 8] comprises four views each representing a row of a memory matrix in the BB plane of FIGS. 3 to 7 at the manufacturing stage of [Fig. 7]. The different views represent more precisely different possible arrangements of the layers 25 in the memory cell row.

[0073] View 8A corresponds to a case in which the etching mask of the step of [Fig.7] is located opposite layer 25. The mask is aligned with layer 25. Thus, during the etching of the line of the memory matrix, layer 26 is etched so as to uncover the side walls of layer 25. The dimension of the line in the Y direction is then substantially equal, for example equal, to the dimension of layer 25.

[0074] View 8B corresponds to a case in which the dimension of the etching mask in the Y direction is greater than the dimension of the layer 25 in the Y direction and in which the mask is located opposite the entire layer 25 and the portions of the layer 22 and the element 24 surrounding the layer 25. Thus, the side walls and the upper face of the layer 25 are covered by the layer 26.

[0075] In the case of views 8A and 8B, the etching of the lines does not reach layer 25. Thus, although the etching process of layers 26 and 22 etches the material of layer 25 more slowly, the presence of layers 25 has no impact on the etching of the lines.

[0076] View 8C corresponds to a case in which the etching mask is offset by relative to layer 25. Thus, the mask is not located opposite a portion of layer 25.

[0077] View 8D corresponds to a case in which the dimension of the etching mask in the Y direction is smaller than the dimension of the layer 25 in the Y direction and in which the mask is located opposite a central portion of the layer 25.

[0078] In the case of views 8C and 8D, the etching of the line, and more precisely of layer 26, leads to the uncovering of layer 25. However, the etching of level 20 can be carried out around layer 25. Thus, the etching step is not maintained to etch layer 25, which avoids the involuntary etching of layer 26 and the formation of lateral cavities in layer 26.

[0079] Thus, although there is no self-alignment between the etching of the line and the etching of the layer 25, this does not impact the advantages of the described embodiment.

[0080] [Fig. 9] represents a device resulting from a step of a method of manufacturing the device of [Fig. 1]. More specifically, [Fig. 9] represents two sectional views 9A and 9B. View 9A corresponds to a sectional view along plane AA of view 9B and view 9B corresponds to a sectional view along a plane BB of view 9A. Planes AA and BB are preferably substantially perpendicular.

[0081] During this step, the passivation layer 32 is formed. In other words, the layer 32 is formed conformally on the structure resulting from the step of [Fig.7]. The layer 32 thus preferably covers the upper faces of the layers 30, the portions of the upper faces of the level 14 and the side walls of the lines, that is to say the side walls of the layers 22, 25, 26, 28, 30 and of the elements 24.

[0082] The method may for example comprise additional steps, subsequent to the step of [Fig.9]. During these steps, the spaces separating the lines may be filled with one or more insulating layers not shown.

[0083] Figures 10 and 11 illustrate another method of manufacturing the device of [Fig.l].

[0084] [Fig. 10] represents a device resulting from a step of another method of manufacturing another device of [Fig.l]. More precisely, [Fig.10] represents two sectional views 10A and 10B. View 10A corresponds to a sectional view along plane AA of view 10B and view 10B corresponds to a sectional view along a plane BB of view 10A. Planes AA and BB are preferably substantially perpendicular.

[0085] The step of [Fig. 10] is configured to replace the step of [Fig. 5]. In other words, the method of Figures 10 and 11 comprises, before the step of [Fig. 10], the steps of Figures 3 and 4, as previously described.

[0086] The step of [Fig. 10] differs from that of [Fig. 5] in that the layer 42 is etched so as to form stripes 50. The stripes extend in the Y direction, that is to say the direction in which the columns of memory cells extend. Each strip 50 comprises the portions of the layer 42 corresponding to the layers 25 of the same column of memory cells. Each strip 50 further comprises the portions of the layer 42 located between the layers 25 of the column. The dimension of each strip 50 in the X direction is preferably substantially equal to the dimension of the layers 25 in the X direction.

[0087] In the embodiment of Figures 10 and 11, the memory preferably comprises columns of cells 12a, i.e., columns of the memory array comprising only cells 12a, and columns of cells 12b, i.e., columns of the memory array comprising only cells 12b. Thus, strips 50 are formed in the locations of the cells 12a and are not formed on the locations of the cells 12b.

[0088] [Fig. 11] represents a device resulting from a step of another method of manufacturing the device of [Fig.l]. More precisely, [Fig.11] represents two sectional views 11A and 11B. View 11A corresponds to a sectional view along plane AA of view 11B and view 11B corresponds to a sectional view along plane BB of view 11A. Planes AA and BB are preferably substantially perpendicular.

[0089] The step of [Fig. 11] includes the step of [Fig.6] as described in connection with [Fig.6].

[0090] The step of [Fig. 11] further comprises a step replacing the step of [Fig.7]. More specifically, the step of [Fig.11] comprises the steps of [Fig.7] and further comprises, during the etching of the memory cell lines, the etching of the strips 50.

[0091] The method of Figures 10 and 11 further comprises steps not shown. In particular, the method of Figures 10 and 11 comprises the step of [Fig.9].

[0092] Although the method of Figures 10 and 11 does not prevent the inadvertent etching of the layer 26 during the etching of the strips 50, the method of Figures 10 and 11 makes it possible to form cells 12a in a "wall" type memory matrix.

[0093] [Fig. 12] shows another embodiment of an electronic device 52. More specifically, [Fig. 12] shows two sectional views 12A and 12B. View 12A corresponds to a sectional view along plane AA of view 12B and view 12B corresponds to a sectional view along plane BB of view 12A. Planes AA and BB are preferably substantially perpendicular.

[0094] The device 52 comprises the elements of the device 10, arranged in an identical manner. These elements will not be detailed again. Thus, the device 52 comprises: - level 14, comprising layer 16 and contacts 18; - level 20, comprising layers 22 and elements 24; - layers 25 of conductive material; - layers 26 of phase change material; - layers 28 of conductive material; - layers 30 of insulating material; and - the passivation layer 32 made of insulating material.

[0095] The device 52 comprises cells 120a, similar to the cells 12a described in relation to [Fig.l], i.e. cells configured to contain one value from at least three values. The device 52 comprises, for example, cells 120b similar to the cells 12b described in relation to [Fig.l], i.e. cells configured to contain one value from at least two values.

[0096] The device 52 differs from the device 10 of [Fig. 1] in that the memory cells are individualized. In other words, the rows of memory cells are separated into portions corresponding to each memory cell. More specifically, each memory cell 120a comprises a portion of layer 22, an element 24, a layer 25, a portion of layer 26, a portion of layer 28, and a portion of layer 30. Each memory cell 12b comprises a portion of layer 22, an element 24, a portion of layer 26, a portion of layer 28, and a portion of layer 30.

[0097] The memory cells, and more precisely the stacks of each memory cell comprising level 20, layers 26, 28, 30 and possibly layer 25, are separated from each other. Thus, the different levels and the different layers of said stacks are not in contact with the stacks of the other cells.

[0098] Layer 32 of [Fig. 12] differs from layer 32 of [Fig.l] in that layer 32 covers, in [Fig. 12], all the side walls of each cell. Thus, layer 32 separates the cells from each other. In other words, the side walls, for example the four side walls, of layers 22, 26, 28, 30, the upper face of layer 30 and possibly the side walls of layer 25 and element 24, are covered by layer 32.

[0099] A method of manufacturing the device 52 comprises the method steps of Figures 3 to 9 or the method steps of Figures 10 and 11. The method of manufacturing the device 52 comprises, for example after the step of [Fig.9] or after the step of [Fig.11], a step of forming an insulating layer (not shown) covering the structure resulting from [Fig.9] so as to fill the spaces between the lines and so as to obtain a flat upper face. The method then comprises forming an etching mask comprising strips (not shown) extending in the Y direction so as to cover the locations of the memory cells. More specifically, each strip (not shown) covers the locations of the memory cells of a column. Each strip further covers the regions separating the cells of said column. The method then comprises etching the stack, the layer 32 and the insulating layer not shown. The method then comprises, for example, forming a layer not shown in a conformal manner on the structure, the layer not shown being, for example, made of the material of the layer 32.

[0100] Another manufacturing method comprises the steps of the method of Figures 3 to 9 or the steps of the method of Figures 10 and 11. The method of manufacturing the device 52 differs from the method of Figures 3 to 9 or the method of Figures 10 and 11 in that, in step 7, or in step 11, the etching masks, formed before the etching of the stack of level 20 and layers 25, 26, 28, 30, do not have a strip shape but a shape such that each mask substantially covers, preferably only, the location of a memory cell. Thus, the etching makes it possible to obtain individualized cells.

[0101] An advantage of the embodiments is that they make it possible to obtain layers 26 of phase change material having straight and flat profiles. In particular, the side walls of the layers 26 are not etched during the etching of the layer 25.

[0102] Another advantage of the embodiments is that they allow for improved alignment of layer 26 and layers 25.

[0103] Another advantage of the embodiments is that they allow wall-type or point-type memory cells to be formed.

[0104] Another advantage of the embodiments is that they allow the dimensions of the memory cells to be reduced, which allows the current required for programming to be reduced.

[0105] Another advantage of the embodiments is that they make it possible to form, on the same circuit, and possibly in the same memory, cells comprising a layer 25 and cells not comprising a layer 25.

[0106] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0107] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing a memory comprising at least one first phase-change memory cell (12a, 120a), each first cell (12a, 120a) comprising a resistive element (24), a first metal layer (25) and a second layer (26) of a phase-change material, the first layer (25) being located between the resistive element (24) and the second layer (26), the method comprising: a. forming a level (20) comprising the resistive element (24); b. forming a third metal layer (42) on the level (20); c. etching the third layer (42); then d. forming the second layer (26).

2. The method of claim 1, wherein the first metal layer (25) is TiSiN, TiN, or TaN, the third metal layer (42) being the same material as the first layer (25).

3. A method according to claim 1 or 2, wherein the device comprises at least two first cells (12a, 120a), the first metal layers (25) of different first cells being separated from each other.

4. A method according to any one of claims 1 to 3, wherein the first metal layer (25) is in contact with the resistive element (24) and with the second layer (26) of a phase change material.

5. A method according to any one of claims 1 to 4, wherein the device comprises at least one second phase change memory cell (12b, 120b) comprising a resistive element (24) and a second layer (26) of a phase change material, the second layer (26) is in contact with the resistive element (24), the method comprising etching the first layer at the locations of the second cells (12b, 120b).

6. Method according to any one of claims 1 to 5, in which the device comprises rows of memory cells (12a, 12b, 120a, 120b), the cells of the same row comprise a second layer (26) of a common phase change material.

7. A method according to any one of claims 1 to 5, wherein the memory cells (12a, 12b, 120a, 120b) each comprise a portion of the second layer (26) made of a phase change material, the portions of the second layer (26) made of a phase change material of the different cells being separated from each other.

8. Method according to any one of claims 1 to 7, in which the method comprises a step e., subsequent to step d. in which the portions of the first level (20) and of the second layer (26) of a phase change material located around the memory cells are etched.

9. Method according to any one of claims 1 to 7, in which the device comprises at least two rows of memory cells (12a, 12b, 120a, 120b), the method comprising a step e., subsequent to step d., in which the portions of the first level (20) and of the second layer (26) of a phase change material located between the two rows of memory cells are etched.

10. Method according to claims 7 and 9, in which the device comprises at least two columns of memory cells, the method comprising a step f. subsequent to step e., in which the portions of the first level (20) and of the second layer (26) of a phase change material located between the two columns of memory cells are etched.

11. A method according to any one of claims 1 to 10, wherein step c. comprises etching the third metal layer (42) so as to form the first metal layer (25).

12. Method according to any one of claims 1 to 10, in which step c. comprises etching the third metal layer (42) so as to form strips (50) each comprising the first layers (25) of first cells (12a) of the same column of memory cells.

13. A method according to claims 8 and 12, wherein step e. comprises etching the strips (50) so as to form the first metal layers (25).

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