Method of configuring a non-volatile phase change memory

Abstract

Method for configuring a non-volatile phase-change memory The present description relates to a method for configuring a non-volatile phase-change memory, comprising partitioning said memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being linked to different physical write parameters. Figure for abstract: Fig. 3

Description

Title of the invention: Method for configuring a non-volatile phase-change memory Technical field

[0001] The present description generally relates to methods for configuring non-volatile phase-change memories as well as to microcontrollers implementing these methods. Prior art

[0002] Non-volatile phase-change memories incorporated in microcontrollers are potentially sensitive to high temperatures such as those used during soldering steps. This can cause the data written to the memory to be corrupted prior to the soldering step. It is also difficult to predict at what point in the life of the microcontroller the soldering step will take place. Summary of the invention

[0003] There is a need to provide a method for configuring the non-volatile phase change memory of a microcontroller so as to address cases where the microcontroller is soldered before or after writing data to the memory while maintaining a satisfactory maximum number of write cycles.

[0004] One embodiment overcomes all or part of the drawbacks of the known methods.

[0005] One embodiment provides a method of configuring a non-volatile memory. volatile phase change memory, comprising partitioning said memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being linked to different physical write parameters.

[0006] One embodiment provides a microcontroller having a non-volatile phase change memory, configured to implement a partition of said memory into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being linked to different physical write parameters.

[0007] According to one embodiment, the first maximum number of write cycles corresponds to the use of a first write mode and the second maximum number of write cycles corresponds to the use of a second write mode.

[0008] According to one embodiment, the partition and the use of the first and second writing modes are implemented by a memory interface.

[0009] According to one embodiment, when the first writing mode is used, data written before a soldering step of the microcontroller is kept stable during said soldering step.

[0010] According to one embodiment, when the second writing mode is used, a value written before a soldering step of the microcontroller is not kept stable during said soldering step.

[0011] According to one embodiment, the second maximum number of write cycles is at least five times greater than the first maximum number of write cycles.

[0012] According to one embodiment, the crystallinity of memory sectors of regions of the first and second sets is different, after writing, depending on the use of the first or second writing mode.

[0013] According to one embodiment, the use of the first or second writing mode is defined for each region of each set by one or more configuration bytes.

[0014] According to one embodiment, the definition of the use of the first or second writing mode is implemented with a byte association register linked with the configuration byte(s).

[0015] According to one embodiment, when the use of the first writing mode has been defined for one or more regions of one of the sets and this or these regions correspond to an application requiring a number Nappli of writing cycles greater than the first maximum number of writing cycles, then said region or regions are divided into N memory sectors in which data of the application are written successively; N being greater than or equal to the ratio between Nappli and the first maximum number of write cycles.

[0016] According to one embodiment, the N memory sectors have their respective address indexed and when one of the data of the application is written in the memory sector of index N, then the following data is written in the sector of the lowest index.

[0017] According to one embodiment, after writing a region using the second writing mode, said region can be rewritten using the first writing mode.

[0018] According to one embodiment, after writing a region using the first writing mode, said region cannot be rewritten using the second writing mode.

[0019] According to one embodiment, the first writing mode comprises applying a first level of voltage, current or power; and the second writing mode comprises applying a second voltage, current or power level different from the first voltage, current or power level.

[0020] According to one embodiment, the first voltage, current or power level is greater than the second voltage, current or power level. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of specific embodiments provided by way of non-limiting example in connection with the accompanying figures, among which:

[0022] [Fig. 1] schematically represents, in block form, an example of a microcontroller of the type to which the described embodiments apply;

[0023] [Fig. 2] represents, in block form, a method of configuring a block of [Fig. 1] according to one embodiment;

[0024] [Fig. 3] represents, in block form, a method of configuring a block of [Fig. 1] according to another embodiment;

[0025] [Fig. 4] schematically represents, an example of a block of the microcontroller according to one embodiment;

[0026] [Fig. 5] represents, in block form, a method of configuring a block of [Fig. 4];

[0027] [Fig.6] represents very schematically an example of a block of [Fig.4];

[0028] [Fig.7] represents in block form a method of configuring and writing the block of [Fig.6]; and

[0029] [Fig.8] represents in block form another method of configuring and writing the block of [Fig.6]. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] [Fig. 1] represents, very schematically and in the form of blocks, an example of a microcontroller 100 of the type to which the described embodiments apply. The microcontroller 100 is for example a microcontroller.

[0036] The microcontroller 100 comprises a non-volatile memory 104 (NVM), for example of the phase change type, capable of communicating, via a communication bus 114, with a non-volatile memory interface 106 (NVM INTERFACE) configured to write or read data in and from the non-volatile memory 104.

[0037] The microcontroller 100 further comprises, for example, a processing unit 110 (CPU) comprising one or more processors under control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, a volatile memory of the random access type (Random Access Memory, RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140 (data, address and command). The memory 104 is connected to the system bus 140 via the non-volatile memory interface 106 and via the bus 114. The device 100 further comprises an input / output interface 108 (FO interface) connected to the system bus 140 to communicate with the outside.

[0038] The microcontroller 100 may integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, or other processing units), symbolized by a block 116 (FCT) in [Fig.l]. Among these other circuits, the microcontroller 100 comprises for example a read-only or static memory 118 (ROM).

[0039] The memory 104 is for example partitioned into different regions comprising one or more memory sectors. In a phase change memory 104, these sectors can be rewritten directly without requiring a prior erasure operation. Writing to these sectors is carried out by changing their resistance, for example by applying physical writing parameters such as a voltage or a current at the time of writing.

[0040] Several write modes have recently been developed for writing data to the memory sectors of phase change memories. Some modes write modes allow a high maximum number of write cycles, for example of the order of 10,000 cycles, while other write cycles allow a lower maximum number of write cycles, for example of the order of 1,000 cycles but with higher temperature resistance. The cycling performances of the different write modes are linked, for example, to a change in crystallinity of the memory sectors depending on the chosen write mode. The term crystallinity is similarly understood to mean an atomic arrangement, for example an orientation of atomic planes, lattice parameters, or even an amorphous, multicrystalline or monocrystalline character. The sectors written with the write modes allowing a high maximum number of write cycles (eg 10,000 cycles) are however more sensitive to high temperatures such as those reached in the microcontroller 100 when it is soldered.Thus, data written in high-cycle write modes may be corrupted or erased, i.e. not robust, when the microcontroller is soldered.

[0041] The different regions of the memory 104 are for example used by different applications implemented by the microcontroller 100. Each type of application may require a different maximum number of cycles. Some applications may also be implemented in the factory by the manufacturer of the microcontroller and others loaded by external service providers who will solder the microcontroller into a product before or after writing the data. It is therefore difficult to predict when the microcontroller will be soldered.

[0042] On the other hand, conventional non-volatile memories, i.e. those which are not phase-change memories, allow high write cycling without, however, being excessively sensitive to temperature. It is therefore appropriate to allow customers or service providers to use phase-change memories in a way that is similar to the use of conventional non-volatile memories.

[0043] The described embodiments propose partitioning the memory 104 into a first set of one or more regions having a first maximum number of write cycles and a second set of one or more other regions having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being linked to different physical write parameters.

[0044] This makes it possible to take advantage of the advantages of phase change memories such as the absence of the need for erasure before rewriting while offering flexibility in the choice of writing mode to the different customers or service providers using the microcontroller 100. It is thus, for example, possible to choose, for a given region of the memory, a writing mode resistant to soldering, and for another region, another writing mode which is certainly not robust with respect to the welding step, but which is still implemented after welding.

[0045] An embodiment further allows for a maximum number of write cycles similar to a conventional non-volatile memory while ensuring that the data written before soldering will be kept robust.

[0046] [Fig.2] represents in block form a method of configuring a block of [Fig.l] according to one embodiment. More particularly, [Fig.2] illustrates a method of configuring the memory 104.

[0047] In a first step 202 (START), the method of configuring the memory 104 begins and is implemented, for example using the memory interface 106.

[0048] In a second step 204 (PARTITIONING OF NVM PCM MEMORY IN DIFFERENT AREAS, EACH AREA HAVING AT LEAST TWO POSSIBLE WRITING MODES WITH DIFFERENT MAXIMUM NUMBER OF WRITING CYCLES), the memory 104 is divided, for example using the memory interface 106, into one or more regions each having several possible writing modes. The region or regions are each composed of one or more memory sectors. In other words, the memory 104 is partitioned into several regions each having several possible writing modes, each writing mode allowing a maximum number of writing cycles of the memory sectors as well as a temperature resistance of the data specific to it.

[0049] In one example, a first write mode (power mode) allows data written before a soldering step of the microcontroller 100 in a memory sector of one of the regions of the memory 104 to be kept stable during the soldering step of the microcontroller 100. The first write mode is for example obtained by applying a first voltage level, a first current level or a first electrical power level. These first voltage, current or power levels may also include variations in voltage, current or power.

[0050] In an example of a second writing mode (user mode), data written in a memory sector, before a soldering step of the microcontroller, is not kept stable during the soldering step. This difference in temperature resistance between the first mode and the second mode is for example due to the fact that the first mode (power mode) implements one or more voltages, currents or powers higher than those implemented for the second mode (user mode). The second writing mode is for example obtained by applying a second voltage level, a second current level or a second electrical power level that are different, for example lower, than the first voltage, current or power level. These second voltage, current or power levels may also include variations in voltage, current, or power. In one example, the resistivity of memory sectors in a region obtained with the second write mode is different from the resistivity obtained with the first write mode.

[0051] In one example, the second write mode (user mode) allows a higher maximum number of write cycles than the first mode (power mode), for example greater than five times. The second write mode (user mode) allows a maximum number of write cycles, for example of the order of 10,000 cycles, while the first write cycle (power mode) allows a maximum number of write cycles, for example of the order of 1,000 cycles, but with greater temperature resistance of the written data.

[0052] The difference between the maximum number of write cycles achievable by the first write mode and the second write mode is for example due to the differences between the first and second voltage or current modes.

[0053] [Fig. 3] represents in block form a method of configuring a block of [Fig. 1] according to another embodiment. The method of [Fig. 3] is similar to the method of [Fig. 2] but with an additional step 306 (DEFINE FOR THE DIFFERENT AREAS, ONE WRITING MODE AMONG THE POSSIBLE WRITING MODES) implemented after step 204.

[0054] In step 306, a write mode, among the possible write modes, for example either the first or the second mode, is defined, in other words selected, for each region of the memory 104. This definition is for example implemented by the memory interface 106.

[0055] By the term designation, we mean that each region is assigned a writing mode selected from the first or second writing mode for example. The selection of the writing mode is done for example by changing a configuration byte (option byte in English).

[0056] In the case where the first writing mode permanently modifies the crystallinity of the memory sectors, after writing memory sectors of a region defined with the first writing mode (power mode), these sectors cannot be rewritten when said region is then defined with the second writing mode (user mode).

[0057] Conversely, in the case where the second writing mode (user mode) does not definitively modify the crystallinity of the memory sectors, after writing memory sectors of a region defined with the second writing mode (user mode), these sectors can be rewritten if said region is then defined with the first writing mode (power mode).

[0058] The method of [Fig.3] provides the possibility of designating or assigning, for each region, the first or second writing mode for example while allowing the use of the microcontroller by several successive service providers or customers.

[0059] [Fig.4] represents, very schematically, an example of a block of the microcontroller 100 according to one embodiment.

[0060] More particularly, [Fig.4] represents an example of partitioning the memory 104 into regions 402 (User memory), 404 (System memory), 406 (HCD), 408 (OBK1 / 2 / 3), 410 (OBK0), 412 (OTP), 414 (RO), 416 (USER OBs) and 418 (Engi Obs). The writing mode defined for each of the regions of the example of [Fig.4] depends on the use of the regions for example by different applications.

[0061] The region 402 comprises for example several sub-parts, each sub-part being defined with one of the writing modes. In one example, each sub-part corresponds to a group of several sectors, for example four. For the definition of the writing mode of each sub-part, a byte association register (bitmap in English) is for example used in association with the configuration byte(s). In one example, setting a configuration bit or byte of the byte association register to 0 or 1 corresponds to the definition of the writing mode chosen for the sub-part corresponding to said bit or byte. In one example, the byte association register is called NVM_WRMyR. In this example, a first sub-part is denoted NVM_WRMyR [0], a second is denoted NVM_WRMyR [1] and a third is denoted NVM_WRMyR [2], etc.The byte association register associates a bit or byte representing the first or second write mode (e.g. 0 for the first mode and 1 for the second) with each of the sub-parts of region 402.

[0062] Region 404 is for example used by an application whose data is written by the manufacturer of the microcontroller 100. In addition, since region 404 is not intended to be rewritten, it only requires a low write cycling capacity. A soldering step will undoubtedly be implemented later in the life of the microcontroller. Region 404 is therefore for example defined with the first write mode so that the data can be retained during the soldering step.

[0063] Region 406 is used for example by an application that requires a large number of write cycles. Region 406 is therefore defined with the second write mode. In one example, this definition of the write mode is hard-coded upon manufacture of the microcontroller so that it cannot be modified by a program.

[0064] Region 412 corresponds, for example, to data written only once (One Time Programmable data in English). The low level of cycling required therefore makes it possible to use the first writing mode (power mode) for this region.

[0065] Region 414 corresponds, for example, to data that can only be read (Read Only Data in English). The low level of write cycling required therefore makes it possible to use the first write mode (power mode) for this region 414.

[0066] The region 416 corresponds for example to data which is written by the manufacturer of the microcontroller but which can be updated by an external service provider during the life of the microcontroller for example. In other words, the microcontroller is likely to be soldered after the data has been written by the manufacturer. The write mode defined for this region must therefore be the first write mode (power mode). Nevertheless, it may be necessary for the updates of the data in this region to remain possible throughout the life of the microcontroller 100. For example, certain applications require that a greater number Nappli, for example 10000, of write cycles be achievable.

[0067] The embodiments described in [Fig.6] and 7 make it possible to address this problem.

[0068] The region 418 is for example programmed by the manufacturer with data which correspond for example to manufacturing or debugging data issued by the manufacturer. The number of write cycles in the life of the microcontroller is reduced and the region 418 is therefore defined with the first write mode (power mode) to support the soldering step.

[0069] The region 420 comprises, for example, five sub-parts OBK0, OBK1, OBK2, OBK3NS and OBK3S which comprise configuration byte keys which correspond to security keys for different service providers, for example. These configuration byte keys are programmable, for example, by different service providers external to the manufacturer. It is, for example, possible to allow the four sub-parts OBK1, OBK2, OBK3NS and OBK3S to be defined with a programmable writing mode after manufacturing, which allows for increased flexibility of use.

[0070] The OBK0 sub-part is for example programmed by the manufacturer with data that must remain robust throughout the life of the microcontroller 100. The OBK0 sub-part is therefore defined with the first write mode (power mode). In one example, this definition of the write mode is hard-coded from the manufacture of the microcontroller so that it cannot be modified by a program.

[0071] In an example not shown, all the sub-parts OBK1, OBK2, OBK3NS and OBK3S, thanks to two sectors, a current sector which contains the valid values ​​of all the security keys of the sub-parts OBK1, OBK2, OBK3NS and OBK3S and a substitution sector used to update these keys. To update a key in one of the sub-parts, the substitution sector is selected, for example with the implementation of a dedicated register, then the new key is written, by way software for example, in the substitution sector and the valid keys of the other sub-parts are copied into the substitution sector for example by a state machine associated with a command called for example OBKSWAP. The OBKSWAP command is implemented, for example by the memory interface 106, to exchange the role of the two sectors. The substitution sector thus becomes the current sector where the data of the new key is valid. Since the sub-parts OBK1, OBK2, OBK3NS and OBK3S, can be defined with different writing modes and used with a different number of write cycles, it is not recommended to update all the sub-parts each time a key of only one of the sub-parts must be updated.For example, if the OBK0 and OBK1 subparts are programmed with the first writing mode (power mode) and the other subparts are programmed with the second mode (user mode), then if the user updates the key in OBK2 a thousand times then the OBK0 and OBK1 subparts also cycle a thousand times which becomes harmful with the first writing mode.

[0072] It is therefore necessary to provide a different method for writing the sub-parts of the region 420 which is compatible with the fact that several writing modes are possibly defined for the different sub-parts OBK0, OBK1, OBK2, OBK3NS and OBK3S,

[0073] [Fig.5] represents in block form a method of configuring a block of [Fig.4] according to one embodiment. More particularly, [Fig.5] illustrates a method of writing in the sub-parts OBK1, OBK2, OBK3NS and OBK3S of the region 420.

[0074] The method of [Fig.5] consists of each sub-part OBK0, OBK1, OBK2, OBK3NS and OBK3S being managed independently for updating the data with two sectors specific to each of the sub-parts.

[0075] Since the sub-parts OBK1, OBK2, OBK3NS and OBK3S are processed, in the example of [Fig.5], independently, [Fig.5] represents the process of writing a new key in only one of the sub-parts, i.e. the sub-part which is concerned by the updating of one of the keys, the other sub-parts remaining with unchanged sectors.

[0076] In a step 502 (OBKSWAP Request), the current sector is called SI and the substitution sector is called S2. In this step, the command called OBKSWAP is implemented, for example with a state machine.

[0077] In a step 504 (Addr index=0), subsequent to step 502, an index of the address read from the current sector starts at zero.

[0078] In a step 506 (data in S2 is virgin?), subsequent to step 504, it is checked whether the address corresponding to the current index is virgin. If yes (branch Y) then a step 508 (Copy data from SI to S2) is implemented. If not, a step 510 (end of sector?) is implemented.

[0079] In step 508, the data of the current sector SI are copied with the updated key into the substitution sector S2 and then step 510 is implemented.

[0080] In step 510, if the address index corresponds to an end-of-sector address (Y branch) then a step 512 (Erase current sector: SI) is implemented. If the index does not correspond to an end-of-sector address (N branch) then the index is incremented and the method starts again at step 506.

[0081] In step 512, the current sector SI is erased.

[0082] Step 512 is followed by a step 514 (Swap current / alternate sector) in which the current sector S1 becomes the substitution sector and the substitution sector S2 becomes the current sector.

[0083] [Fig.6] represents very schematically an example of a block of [Fig.4]. [Fig.6] represents more particularly an example of implementation of the region 416 which is, in this embodiment, subdivided into ten sectors or groups of sectors 602 (USER OBI), 604 (USER OB2), 606 (USER OB3), 608 (USER OB4), 610 (USER OB5), 612 (USER OB6), 614 (USER OB7), 616 (USER OB8), 618 (USER OB9) and 620 (USER OB10). Each sector of the region 416 is defined with the first writing mode.

[0084] This implementation example, associated with the writing method described in the following figure, allows an application using the region 416 to benefit from the robustness of the data written with the first writing mode (power mode) while benefiting from a maximum number of writing cycles greater than that available for the first writing mode (power mode).

[0085] [Fig.7] represents in block form a method of configuring and writing the block of [Fig.6]. More particularly, [Fig.7] represents a method of configuring and writing the region 416 of [Fig.6].

[0086] The method of [Fig.7] comprises steps 202, 204 and 306 similar to the example of [Fig.3].

[0087] In an additional step 708 (DIVIDE THE AREA IN N GROUPS OF SECTORS, N BEING SUPERIOR OR EQUAL TO THE RATIO OF THE MAXIMUM NUMBER OF WRITING CYCLES NEEDED AND THE MAXIMUM NUMBER OF WRITING CYCLES OF THE FIRST MODE), performed after step 306, if the maximum number Nappli of write cycles necessary for an application using the region 416 is greater than the maximum number of write cycles of the first write mode (power mode), then this region is divided into N memory sectors in which data of the application are written. N is for example greater than or equal to the ratio between Nappli and the maximum number of write cycles of the first write mode (power mode).

[0088] In a step 710 (WRITE DATA IN ONE OF THE GROUP OF SECTORS THEN CHANGE SECTOR WHEN REACHING A THRESHOLD), after step 708, a counter counts the number of write cycles having taken place in each of the N memory sectors.

[0089] In one example, when the counter reaches a certain threshold for a sector, then data is written to another sector. In one example, the sector with the least data written becomes the sector where new application data is written when the counter reaches that threshold.

[0090] Steps 708 and 710 are for example implemented using the memory interface 106.

[0091] Each sector of the region 416 having for example a capacity of 1000 write cycles due to the use of the first write mode (power mode), by passing from one sector to another, it is possible to reach, for the region 416 as a whole, a maximum number of write cycles of 10000 (10*1000) cycles which is much higher than the maximum number of write cycles of the first write mode (power mode) while maintaining robustness of the written data with respect to a welding step.

[0092] [Fig. 8] represents in block form another method of configuring and writing the block of [Fig. 6]. More particularly, [Fig. 8] represents a method of configuring and writing the region 416 of [Fig. 6].

[0093] The method of [Fig.8] comprises steps 202, 204 and 306 similar to the example of [Fig.3].

[0094] In an additional step 808 (WRITE A FIRST VALID DATA IN A FIRST SECTOR WITH A FIRST INDEX), performed after step 306, a valid data item is written, with the first write mode, in a first sector or group of sectors of the region 416 whose address has a first index. This data item corresponds for example to a security key such as a configuration byte key.

[0095] In a step 809 (ALL SECTORS HAVE REACHED A MAXIMUM NUMBER OF DATA WRITING CYCLE?) subsequent to step 808, if the N sectors or groups of sectors of the region 416 have been written a number of times equal to the maximum number of write cycles possible of the first write mode (branch Y) then the method stops with a step 811 (STOP). Otherwise (branch N), a step 810 (UPDATE SECTOR INDEX AND WRITE DATA IN SECTOR CORRESPONDING TO UPDATED INDEX) is implemented.

[0096] In step 810, the data previously written in the first sector is no longer valid. In this step, the index of the address relating to the sector or group of sector of region 416 is incremented unless the index is equal to the number N defined in [Fig.7]. If the index is equal to N then the index is reset to 0, for example in a circular permutation manner. The new valid data is then written, with the first write mode (power mode), in the sector or group of sectors of region 416 whose address corresponds to the updated index. The N sectors are thus filled in turn until the maximum number of write cycles linked to the use of the first write mode is reached for each of the sectors.

[0097] Step 809 is then implemented again.

[0098] Steps 808, 809 and 810 are for example implemented using the memory interface 106.

[0099] In the example where the maximum number of write cycles of the first mode is 1000 cycles, it is thus possible to achieve, for the region 416 as a whole, a maximum number of write cycles of 10000 (10*1000) cycles which is much greater than the maximum number of write cycles of the first write mode (power mode) while maintaining robustness of the written data with respect to a welding step.

[0100] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the use of bit association registers may be generalized to all regions of memory 104.

[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, even if the method has been described in the case of a microcontroller, the person skilled in the art will be able to use his knowledge to apply this method to other types of electronic circuits such as systems on chip (SOC).

Claims

Claims

1. A method of configuring a non-volatile phase change memory (104), comprising partitioning said memory (104) into a first set of one or more regions (402, 404, 406, 408, 410, 412, 414, 416, 418) having a first maximum number of write cycles and a second set of one or more other regions (402, 404, 406, 408, 410, 412, 414, 416, 418) having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being related to different physical write parameters.

2. The method of claim 1, wherein the first maximum number of write cycles corresponds to the use of a first write mode (power mode) and the second maximum number of write cycles corresponds to the use of a second write mode (user mode).

3. The method of claim 2, wherein the partitioning and use of the first and second write modes are implemented by a memory interface (106).

4. The method of claim 3, wherein when the first write mode (power mode) is used, data written before a soldering step of the microcontroller (100) is kept stable during said soldering step.

5. Method according to any one of claims 2 to 4, wherein, when the second writing mode (user mode) is used, a value written before a soldering step of the microcontroller (100), is not kept stable during said soldering step.

6. The method of any one of claims 1 to 5, wherein the second maximum number of write cycles is at least five times greater than the first maximum number of write cycles.

7. A method according to any one of claims 2 or 3 to 6 as dependent on claim 2, wherein a crystallinity of memory sectors of regions of the first and second sets is different, after writing, depending on whether the first or second writing mode is used.

8. A method according to any one of claims 2 or 3 to 7 as dependent on claim 3, wherein the use of the first or second write mode is defined for each region of each set by one or more configuration bytes.

9. The method of claim 8, wherein a definition of the use of the first or second write mode is implemented with a byte association register linked with the configuration byte(s).

10. Method according to any one of claims 2, or 3 to 9 in their dependence on claim 2, in which when the use of the first writing mode (power mode) has been defined for one or more regions of one of the sets and this or these regions correspond to an application requiring a number Nappli of writing cycles greater than the first maximum number of writing cycles, then said region or regions are divided into N memory sectors (502, 504, 506, 508, 510, 512, 514, 516, 518, 520) in which data of the application are written successively; N being greater than or equal to the ratio between Nappli and the first maximum number of writing cycles.

11. Method or microcontroller according to claim 10, in which the N memory sectors have their respective addresses indexed and when one of the data of the application is written in a memory sector of index N, the next data is then written in the sector of lowest index.

12. A method according to any one of claims 2 to 11 wherein, after writing a region using the second writing mode (user mode), said region can be rewritten using the first writing mode (power mode).

13. A method according to any one of claims 2 to 12 wherein, after writing a region using the first writing mode (power mode), said region cannot be rewritten using the second writing mode (user mode).

14. A method according to any one of claims 3 or 4 to 13 in their dependence on claim 2, wherein the first write mode (power mode) comprises the application of a first level of voltage, current or power; and the second write mode (user mode) comprises the application of a second level of voltage, current or power different from the first level of voltage, current or power.

15. The method of claim 14, wherein the first voltage, current or power level is greater than the second voltage, current or power level.

16. A microcontroller (100) having a non-volatile phase-change memory (104), configured to implement a partition of said memory (104) into a first set of one or more regions (402, 404, 406, 408, 410, 412, 414, 416, 418) having a first maximum number of write cycles and a second set of one or more other regions (402, 404, 406, 408, 410, 412, 414, 416, 418) having a second maximum number of write cycles greater than the first maximum number of write cycles, the first and second maximum numbers of write cycles being linked to different physical write parameters, the microcontroller being configured to implement the method according to any one of the preceding claims.

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