SYSTEM-ON-CHIP AND METHOD FOR POWER MANAGEMENT OF SUCH A SYSTEM-ON-CHIP

Abstract

According to one aspect, there is provided a system-on-chip comprising a central processing unit (CPU) configured to:- execute a first sequence of micro-instructions before being placed in a conservation power mode, said first sequence of micro-instructions being adapted to copy, into at least one data memory (TCDM) directly coupled to the central processing unit (CPU), an execution context of a computer program whose execution by the central processing unit (CPU) is interrupted to enter a conservation power mode, - execute a second sequence of micro-instructions upon exiting the conservation power mode to recover the execution context stored in said memories in order to resume the execution of the interrupted computer program. Figure for abstract: Figure 1

Description

Title of the invention: SYSTEM ON CHIP AND METHOD FOR POWER MANAGEMENT OF SUCH A SYSTEM ON CHIP

[0001] Embodiments and implementations relate to systems-on-chip, and more particularly to optimizing the power consumption of such systems-on-chip.

[0002] Systems on chips are commonly used in a wide variety of electronic devices, such as smartphones, tablet computers, laptops, embedded systems, connected objects (IoT), and many others.

[0003] A system on a chip (also referred to by the acronym "SoC" from the English expression "System on a Chip") is an electronic component that integrates several essential elements of a computer or electronic system on a single silicon chip. A system on a chip includes for example a central processing unit, a memory and communication interfaces on a single chip.

[0004] Optimizing the energy consumption of a system-on-chip is of great importance in order to avoid unnecessary energy consumption. In particular, the system-on-chip may be powered by a battery having a limited capacity. It is therefore appropriate to limit as much as possible the consumption of energy stored in this battery to increase the duration of use of the system-on-chip between two recharges of the battery.

[0005] In order to optimize the power consumption of a system-on-chip, the system-on-chip may comprise several power domains. The power domains correspond to areas of the system-on-chip which are distinct and electrically isolated. These power domains make it possible to independently power different functional blocks or subsystems of the system-on-chip. The use of power domains thus makes it possible to more efficiently manage the power consumption and to control the power supply of the elements of the system-on-chip according to their use or their operating state.

[0006] In particular, the power supply domains make it possible to control and manage the power supply of the elements of the system on chip selectively, by adapting the power supply of these elements according to their needs. It is thus possible to reduce the energy consumption when certain elements of the system on chip are not used.

[0007] The power management of the various elements of the system on chip can be ensured by an energy management system.

[0008] A system-on-chip may notably comprise a power domain associated with its central processing unit and a power domain associated with its energy management system.

[0009] It is important to optimize the power consumption of the system-on-chip when the central processing unit is inactive. In particular, the central processing unit may be made inactive during the execution of a computer program. It is then important to be able to stop the power supply to the central processing unit while retaining the execution context of the interrupted computer program in order to be able to recover it to resume the execution of the computer program once the power supply to the central processing unit is restored.

[0010] In this respect, software solutions are known that make it possible to stop the power supply to a central processing unit while maintaining the execution context of the interrupted computer program. However, these software solutions are generally complex and require the execution of a large number of instructions. Thus, the storage and recovery of the execution context can be relatively slow.

[0011] It is also possible to use dual-powered flip-flops to maintain the execution context when the power supply to the central processing unit is interrupted during the execution of a computer program. However, such flip-flops have the disadvantage of occupying a large space in the system-on-chip.

[0012] There is therefore a need to propose a solution making it possible to interrupt the power supply to the central processing unit of a system on chip during the execution of a computer program and then to restart this central processing unit relatively quickly once its power supply has been resumed.

[0013] There is also a need to provide such a solution having a limited impact on the footprint of the system on chip.

[0014] According to one aspect, there is provided a system on chip comprising: - a central processing unit, - memories directly coupled to the central processing unit, - a power supply controller configured to place the central processing unit and said memories: O in a normal operating power supply mode in which the central processing unit and said memories are supplied with a normal operating supply voltage, or O in a conservation power supply mode in which the central processing unit is no longer powered and said memories are powered by a conservation supply voltage lower than said operating supply voltage normal operation and sufficient to retain data stored in said memories, and in which the central processing unit is configured to: - execute a first sequence of micro-instructions - in particular injected, by the execution of a "goto_retention" instruction, into a processing chain of the central processing unit - before being placed in a conservation power supply mode, said first sequence of micro-instructions being adapted to copy, into at least one data memory directly coupled to the central processing unit, an execution context of a computer program whose execution by the central processing unit is interrupted to switch to a conservation power supply mode, - execute a second sequence of micro-instructions - in particular injected, by the execution of a “release_retention” instruction, into the processing chain of the central processing unit - at the output of the conservation power supply mode to recover the execution context stored in said memories in order to resume the execution of the interrupted computer program.

[0015] Such a system on chip therefore uses memories directly coupled to the central processing unit to store the execution context of a computer program executed by this central processing unit before switching to conservation power mode.

[0016] Thus, when the central processing unit is inactive, it is possible to stop the power supply to the central processing unit while maintaining sufficient power supply for said memories directly coupled to the central processing unit in order to maintain the execution context until the power supply to the central processing unit is resumed. This makes it possible to drastically reduce the energy consumption of the system on chip.

[0017] Furthermore, the preservation of the execution context in the memories directly coupled to the central processing unit allows a simple and rapid restoration of the execution context of the interrupted computer program once the power supply to the central processing unit has been restored. The execution of the computer program can therefore be resumed quickly after restoring the power supply to the central processing unit.

[0018] Such a system-on-chip also has the advantage that the storage and retrieval of the execution context in the memories directly coupled to the central processing unit for switching to and from the conservation power mode are performed by a state machine of the central processing unit and not by software. This makes it possible to perform the switching to and from the conservation power mode more simply and more quickly. This also makes it possible to ensure that the entire execution context is properly stored and retrieved in said at least one data memory directly coupled to the central processing unit. In particular, such a system-on-chip is configured to restore context information in read-only registers that can only be modified by hardware and not by software.

[0019] Such a system-on-chip also has the advantage of not using additional, bulky low-power components such as dual-power flip-flops to maintain the execution context of the interrupted computer program.

[0020] In an advantageous embodiment, the central processing unit comprises a power mode controller configured to communicate with the power controller in order to negotiate with the power controller a transition to a conservation power mode.

[0021] Advantageously, the central processing unit comprises a control unit configured to execute a state machine making it possible to execute microinstructions for: - storing the execution context in said at least one data memory directly coupled with the central processing unit before switching to the conservation power mode, - recovering the execution context in said at least one data memory directly coupled with the central processing unit at the output of the conservation power supply mode.

[0022] Preferably, the central processing unit is configured to execute instructions for entering and exiting the conservation power mode - in particular the instruction "goto_retention" for entering the conservation power mode and the instructions "luiX2 / addX2", "release_retention" and "mret" for exiting the conservation power mode -, these instructions being stored in at least one program memory directly coupled with the central processing unit.

[0023] Advantageously, the central processing unit further comprises a register configured to store an auxiliary stack pointer configured to store the value of a main stack pointer before entering a conservation power mode, said first sequence of micro-instructions being configured to store said auxiliary stack pointer in said at least one data memory directly coupled to the central processing unit before entering the conservation power mode, said second sequence of micro-instructions being configured to retrieve the value of the auxiliary stack pointer for use as the main stack pointer.

[0024] In an advantageous embodiment, the power supply controller is configured to, upon exiting the conservation power supply mode, transmit a signal making it possible to indicate to the central processing unit that the latter is returning from a conservation power supply mode, so that the central processing unit executes said second sequence of micro-instructions.

[0025] According to another aspect, there is provided a method of managing the power supply of a system on chip as described above, the method comprising: - an execution by the central processing unit of a first sequence of microinstructions - in particular injected, by the execution of an instruction "goto_retention", in a processing chain of the central processing unit - before being placed in a conservation power mode, said first sequence of micro-instructions being adapted to copy, into at least one data memory directly coupled to the central processing unit, an execution context of a computer program whose execution by the central processing unit is interrupted to enter a conservation power mode, - an execution by the central processing unit of a second sequence of microinstructions - in particular injected, by the execution of an instruction “release_retention”, in the processing chain of the central processing unit - upon exiting the retention power mode to recover the execution context stored in said memories in order to resume the execution of the interrupted computer program.

[0026] In an advantageous embodiment, the method comprises communication between a power mode controller of the central processing unit and the power controller in order to negotiate a transition to a conservation power mode.

[0027] Advantageously, the method comprises an execution by the central processing unit of micro-instructions provided by a state machine of a control unit of the central processing unit for: - storing the execution context in said at least one data memory directly coupled with the central processing unit before switching to the conservation power mode, - recovering the execution context in said at least one data memory directly coupled with the central processing unit at the output of the conservation power supply mode.

[0028] Preferably, the method comprises an execution, by the central processing unit, of instructions - in particular the instructions "goto_retention", "luiX2 / addX2", "release_retention" and "mret" - to enter and exit the conservation power mode, these instructions being stored in at least one memory of program coupled directly with the central processing unit.

[0029] Advantageously, the method further comprises storing an auxiliary stack pointer in a register of the central processing unit, the auxiliary stack pointer making it possible to store the value of a main stack pointer executed before entering a conservation power mode, the execution of said first sequence of micro-instructions making it possible to store said auxiliary stack pointer in said at least one data memory directly coupled to the central processing unit before entering the conservation power mode, the execution of said second sequence of micro-instructions making it possible to retrieve the value of the auxiliary stack pointer for use as the main stack pointer.

[0030] In an advantageous embodiment, the method further comprises, upon exiting the conservation power supply mode, a transmission by the power supply controller of a signal making it possible to indicate to the central processing unit that the latter is returning from a conservation power supply mode, so that the central processing unit executes said second sequence of micro-instructions.

[0031] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, which are in no way limiting, and the appended drawings in which:

[0032] [Fig.l]

[0033] [Fig.2]

[0034] [Fig.3]

[0035] [Fig.4]

[0036] [Fig.5] illustrate embodiments and implementations of the invention.

[0037] [Fig.l] illustrates a system on chip SOC. The system on chip SOC comprises a central processing unit CPU, a PCTRL power controller, TCM memories directly coupled to the central processing unit CPU (these memories may also be referred to as “tightly coupled memories”).

[0038] The central processing unit CPU is configured to execute instructions of a computer program, in particular of the “firmware” type.

[0039] In particular, the central processing unit CPU comprises elements well known to those skilled in the art, such as an arithmetic and logic unit ALU, an address generation unit AGU, a multiplication / division unit MUL, etc.

[0040] The SOC system on chip uses several power supply modes allowing its power consumption to be adapted according to the use of the different elements of this SOC system on chip. The SOC system on chip is divided into several power supply domains allowing the power supply to be adapted independently between the different power supply domains.

[0041] In particular, the system on chip comprises a first power domain PD_SOC containing the power controller PCTRL.

[0042] The system on chip SOC comprises a second power domain PD_CPU containing the central processing unit CPU.

[0043] The system on chip SOC comprises a third power domain PD_TCM containing the TCM memories.

[0044] The central processing unit CPU can be placed under different power supply modes.

[0045] In particular, the central processing unit CPU may be placed in a normal operating power supply mode. In this mode, the central processing unit CPU is powered by a voltage Vcore.

[0046] The central processing unit CPU may also be placed in an idle power mode. In this mode, the central processing unit CPU is no longer powered.

[0047] The CPU central processing unit may also be placed in a conservation power mode. In this mode, the CPU central processing unit is no longer powered but is configured to save the program execution context before its power is turned off.

[0048] The transition from the normal operating power mode to the conservation power mode is achieved by executing a "goto_retention" instruction capable of injecting micro-instructions into a processing chain ("pipeline") of the central processing unit (CPU).

[0049] The central processing unit CPU comprises a register bank REGF (or "register file"). The register bank REGF is used to temporarily store data during the processing of instructions by the central processing unit CPU during execution of a computer program.

[0050] The central processing unit CPU comprises a memory controller coupled with the TCM memories. The TCM memories are memories directly coupled and juxtaposed to the central processing unit CPU. The TCM memories are configured to provide fast access for the central processing unit, in particular faster compared to an external RAM memory or other types of memory further away from the central processing unit. These TCM memories thus make it possible to improve the performance of a computer program executed by the central processing unit CPU by reducing the memory access times. The TCM memories also have low latency, i.e. the time elapsed between a request for access to the memory and the data being made available by the memory. The latency of the TCM memories is in particular of the order of one cycle of the central processing unit. Each TCM memory has a peripheral circuit and an array. The array is used to store data or instructions. The peripheral circuit is used for the operation of the TCM memory. The peripheral circuit and the array can receive two different voltages for the same power supply mode.

[0051] The TCM memories can be placed in a normal operating power supply mode or in a conservation power supply mode. In the normal operating power supply mode, the peripheral circuit and the table of each TCM memory are powered by a voltage Vcore. In the conservation power supply mode, the periphery of each TCM memory is not powered but the table of each TCM memory is powered by a voltage Vret to keep the information it contains. The voltage Vret is a voltage lower than the voltage Vcore. The voltage Vret is adapted to be lower than the voltage Vcore but sufficient to allow conservation of the data in the TCM memories, and more particularly to maintain an execution context, as described below. The voltage Vret is for example of the order of 0.6 Volts.

[0052] The TCM memories comprise a TCPM program memory and a TCDM data memory. The TCPM program memory is configured to store instructions of a computer program executed by the central processing unit. The central processing unit uses an instruction pointer pointing to the instructions to be executed stored in the TCPM program memory during execution of a computer program.

[0053] The TCDM data memory comprises a main stack (zone DZ of the TCDM data memory) configured to store data generated during the execution of a computer program, in particular temporary data from the register bank REGF. The central processing unit also uses a main stack pointer SP pointing to addresses of the main stack of the TCDM data memory.

[0054] This main stack allows the contents of the register bank REGF to be saved during a change of execution context. This content is restored in the register bank REGF during the restoration of the execution context. The main stack pointer SP then points to the address of the last data saved in the zone DZ of the data memory TCDM.

[0055] Furthermore, the TCDM data memory is also configured to have a RETZ retention area. This RETZ retention area is used to store an execution context of the program before the central processing unit CPU enters retention mode. The RETZ retention area starts at a "retention_context_address" address known by the CTRLU control unit of the central processing unit CPU.

[0056] The central processing unit CPU further comprises control and status registers CSR. The CSR registers are configured to store operating parameters of the central processing unit CPU as well as information on the state of the central processing unit CPU.

[0057] The central processing unit CPU also includes a P_PETR interface for private peripherals. This P_PETR interface includes PPR registers for the private peripherals. The PPR registers for the private peripherals are used to configure and control the operation of peripherals of the system on chip, such as an interrupt controller, a memory protection unit, etc.

[0058] The central processing unit CPU further comprises a control unit CTRLU. The control unit CTRLU is configured to implement a state machine FSM, making it possible to inject micro-instructions into the processing chain of the central processing unit, before the central processing unit CPU enters the conservation power mode and upon exiting the latter. In particular, the instruction "goto_retention" is executed before entering the conservation power mode. The instruction "goto_retention" makes it possible to implement the state machine FSM to inject a sequence of micro-instructions into the processing chain of the central processing unit CPU. This sequence of micro-instructions makes it possible to save the execution context of the computer program in a TCM memory before entering the conservation power mode.

[0059] Upon exiting the conservation power mode, the central processing unit CPU executes a series of micro-instructions injected by a state machine FSM into the processing chain of the central processing unit. This series of micro-instructions makes it possible to recover the execution context of the interrupted computer program in order to resume the execution of this computer program.

[0060] The execution context corresponds to the set of data used by the computer program which needs to be saved to allow an interruption of the computer program and then a resumption of its execution at the point where the computer program was interrupted. The execution context includes the data stored in the register bank REGF, those stored in the control and status registers CSR and those stored in the registers PPR for private peripherals.

[0061] The central processing unit CPU also comprises an SSP register configured to store an auxiliary stack pointer (in English "Shadow stack pointer"). The auxiliary stack pointer takes the value of the main stack pointer to the area of ​​the TCDM data memory in which the execution context of the interrupted computer program, before entering conservation power mode. The SSP register thus makes it possible to store an auxiliary stack pointer SP2 pointing to the address of the main stack pointer before saving the execution context in the TCDM data memory. The sequence of microinstructions injected by the state machine is configured to store this auxiliary stack pointer SP2 in the conservation area RETZ of the TCDM data memory before entering conservation power mode. The storage of this auxiliary stack pointer SP2 makes it possible to recover, upon exiting conservation power mode, the address of the main stack pointer corresponding to the address of the top of the DZ area of ​​the TCDM data memory storing the temporary data generated during the execution of the computer program before entering conservation power mode.

[0062] The TCPM program memory also includes a WRZ zone in which instructions are stored for exiting the conservation power mode by recovering the execution context of the interrupted program and then branching to the instruction that follows the last instruction of the computer program executed before switching to conservation power mode. This WRZ zone begins at an address "warm_restart_addr[31:0]". In particular, the CTRLU control unit knows a start address "boot_address_i[31:0]" as well as an offset value for obtaining the address "warm_restart_addr[31:0]" by adding it to the start address.

[0063] In particular, this WRZ zone of the TCPM program memory includes “luiX2 / addX2” instructions making it possible to load the value of the end of the conservation zone into a register X2 of the register bank.

[0064] This WRZ area of ​​the TCPM program memory also includes a “release_retention” instruction. This instruction makes it possible to recover the execution context of the interrupted program stored in the TCDM data memory. In particular, this “release_retention” instruction makes it possible to recover the data stored in the retention area of ​​the TCPM program memory which are associated with the REGF register bank, the CSR control and status registers and the PPR registers for the peripherals in order to restore this data in the corresponding registers. The “release retention” instruction is also configured to decrement the stack pointer loaded by the “luiX2 / addX2” instruction in the X2 register of the register bank.

[0065] This WRZ area of ​​the TCPM program memory also includes an “mret” instruction. This instruction makes it possible to retrieve the value of the instruction pointer (in English “program counter”) stored in the TCDM data memory to use it for the instruction pointer in order to perform the branch. to the instruction following the last computer program instruction executed before entering conservation power mode.

[0066] The central processing unit CPU also includes an interrupt controller INT_CTRL. The interrupt controller is configured to receive interrupt signals. The interrupt signals may be used to stop the execution of a computer program.

[0067] The central processing unit CPU comprises a power mode controller RET_CTRL. The power mode controller RET_CTRL is configured to communicate with the power controller PCTRL.

[0068] The PCTRL power supply controller is contained in the first power supply domain. All of the elements of the first power supply domain are constantly supplied by a VSOC voltage.

[0069] The PCTRL power controller is configured to control the power supply of the different power domains of the system-on-chip.

[0070] In particular, the system on chip SOC is configured to generate the VSOC voltage, the conservation voltage Vret and the supply voltage Vcore. These voltages are generated from a power source, in particular a power generator of the system on chip SOC.

[0071] The system on chip SOC comprises a first power switch PWRS1 and a second power switch PWRS2 included in the power domain PD_SOC.

[0072] The first switch PWRS1 is controlled by the power supply controller PCTRL. The first switch PWRS1 is configured to receive the voltage Vret and to deliver or not deliver this voltage Vret to the power supply domain PD_TCM according to a command from the power supply controller PCTRL. In particular, the first switch delivers the voltage Vret only when the system on chip SOC is in a conservation mode.

[0073] The second switch PWRS2 is controlled by the power supply controller PCTRL. The second switch PWRS2 is configured to receive the Vcore voltage and to deliver or not deliver this Vcore voltage to the power supply domains PD_TCM and PD_CPU according to a command from the power supply controller PCTRL. In particular, the second switch PWRS2 delivers the Vcore voltage only when the system on chip SOC is in a normal operating power supply mode.

[0074] The PCTRL power controller is configured to receive a RET_REQ signal issued by the RET_CTRL power mode controller of the central processing unit CPU when the central processing unit CPU requests the PCTRL power controller to enter a conservation mode.

[0075] The PCTRL power controller is configured to transmit a RET_ACK signal to the RET_CTRL power mode controller of the central processing unit CPU when the PCTRL power controller agrees to put the central processing unit CPU into a conservation mode after receiving the RET_REQ signal.

[0076] The PCTRL power controller is configured to receive a RET_O signal from the RET_CTRL power mode controller of the central processing unit CPU when the central processing unit CPU receives the RET_ACK signal. The PCTRL power controller is configured to put the central processing unit CPU into conservation mode after receiving the RET_O signal.

[0077] The PCTRL power controller is also configured to transmit a RST_CSE signal to the central processing unit CPU when the PCTRL power controller puts the central processing unit CPU into a normal operating mode after being in a conservation mode. The RST_CSE signal is used to indicate to the CTRLU control unit of the central processing unit CPU to perform a conservation mode exit procedure to recover the execution context of the interrupted program.

[0078] The SOC system on chip also comprises ISOC isolation cells. These ISOC isolation cells are included in the PD_SOC power supply domain. The isolation cells make it possible to isolate the PD_CPU domain from the rest of the SOC system on chip when its power supply is interrupted. In particular, the isolation cells make it possible to prevent propagation of floating signals coming from the central processing unit when the latter is no longer electrically powered to other elements of the SOC system on chip.

[0079] [Fig.2] illustrates a method for managing the power supply of a system on SOC chip such as that described above. In particular, the power management method makes it possible to switch to a conservation power mode and then return to a normal operating power mode.

[0080] Before switching to a conservation power supply mode, in step 20, the central processing unit CPU operates normally and executes a computer program, in particular of the “firmware” type. The central processing unit CPU and the TCM memories are therefore placed in a normal operating power supply mode N0RM_M. Thus, the power supply controller PCTRL controls the second switch PWRS2 so that the central processing unit CPU is powered by the voltage Vcore.

[0081] [Fig.3] illustrates the state of the REGF, CSR, PPR registers of the central processing unit CPU as well as the state of the TCM memories before entering the conservation power mode.

[0082] Next, in step 21, the computer program receives an interrupt causing the execution of the computer program to stop and the execution of the "goto_retention" instruction. The interrupt may originate from a peripheral of the system-on-chip SOC. Alternatively, the "goto_retention" instruction may be present in the executable code of the computer program and be executed during the execution of the computer program.

[0083] The “goto_retention” instruction allows a sequence of micro-instructions to be injected into the processing chain of the central processing unit CPU.

[0084] In particular, this sequence of instructions is executed once all current memory accesses are completed.

[0085] The sequence of micro-instructions injected by the "goto_retention" instruction by implementing the FSM state machine makes it possible to disable the handling of interrupts by the INT_CTRL interrupt controller of the central processing unit CPU, in order to avoid any interrupt when switching to conservation power mode.

[0086] The execution of said sequence of micro-instructions causes storage of the execution context of the interrupted program in the RETZ retention zone of the TCDM data memory. In particular, the execution of the micro-instruction sequence causes storage of the REGF_V values ​​of the REGF register bank, the CSR_V values ​​of the CSR control and status registers and the PPR_V values ​​of the PPR registers for the peripherals.

[0087] This sequence of micro-instructions then makes it possible to generate the RET_REQ signal by the RET_CTRL power mode controller and to transmit it to the PCTRL power controller.

[0088] Then, the PCTRL power controller waits until the system on chip SOC is ready to enter a conservation power mode and then generates the RET_ACK signal and transmits it to the PCTRL power mode controller of the central processing unit CPU.

[0089] Once the RET_ACK signal is received, the execution of the microinstruction sequence then allows the RET_O signal to be generated by the RET_CTRL power mode controller and transmitted to the PCTRL power controller. This RET_O signal indicates that the central processing unit is ready to switch to conservation power mode.

[0090] In step 22, once the RET_O signal is received, the power supply controller PCTRL puts the central processing unit CPU and the TCM memories into a retention power supply mode. To do this, the power supply controller PCTRL controls the first power supply switch PWRS1 so as to deliver the voltage Vret to the TCM memories. The power supply controller PCTRL controls also the second power switch PWRS2 so as to stop the power supply to the central processing unit CPU.

[0091] The PCTRL power controller also stops the clock signal and forces a reset of the central processing unit (CPU) with the reset signal.

[0092] The power supply controller also controls the ISOC isolation cells to isolate the central processing unit CPU.

[0093] The central processing unit CPU and the TCM memories are thus placed in a conservation power supply mode RET_M. In particular, the central processing unit CPU is not powered and the TCM memories are powered by the voltage Vret. Thus, the data of the register bank REGF, the data of the control and status registers CSR and the data of the registers PPR for the peripherals are erased but kept in the conservation area RETZ of the data memory TCDM. [Fig.4] illustrates the conservation of the execution context in the conservation power supply mode.

[0094] Then, in step 23, the power supply controller PCTRL can take the central processing unit CPU and the TCM memories out of the conservation power mode according to the needs of the system on chip SOC. The exit from the conservation power mode is carried out in particular when a new data sequence of a peripheral of the system on chip SOC must be processed by the central processing unit.

[0095] In order to exit the conservation power mode, the power controller PCTRL controls the first switch PWRS1 and the second switch PWRS2 to deliver the Vcore voltage to the central processing unit CPU and the TCM memories. The central processing unit CPU and the TCM memories then enter a normal operating power mode N0RM_M.

[0096] The PCTRL power supply controller also restores the clock signal and the reset signal.

[0097] The PCTRL power supply controller also controls the ISOC isolation cells to stop the isolation of the central processing unit CPU.

[0098] The power supply controller PCTRL also transmits a RST_CSE signal to the central processing unit. This RST_CSE signal is used to indicate to the central processing unit CPU that it is exiting a conservation power mode. The central processing unit CPU can then implement a conservation power mode exit procedure. This procedure is implemented by executing power mode return functions. In particular, a state machine FSM of the control unit CTRLU is configured to inject into the processing chain (“pipeline”) of the central processing unit CPU a sequence of micro-instructions of the instruction “release_retention”. This sequence of micro- instructions are then executed by the central processing unit (CPU).

[0099] In particular, the instruction "release_retention" is executed to recover the data stored in the retention area RETZ of the TCDM data memory, i.e. the execution context of the interrupted computer program. As indicated previously, some REGF_V data is associated with the REGF register bank, other CSR_V data is associated with the CSR control and status registers, and still other PPR_V data is associated with the PPR registers for the peripherals. This data is recovered and then copied respectively into the REGF register bank, into the CSR control and status registers and into the PPR registers for the peripherals. In addition, the value of the main stack pointer is modified by taking the value of the auxiliary stack pointer stored in the RETZ retention area so that the main stack pointer points to the address at the top of the DZ area of ​​the TCDM data memory.The instruction pointer value is also retrieved and stored in the control and status registers CSR. [Fig.5] illustrates the recovery of the execution context upon exiting conservation power mode.

[0100] Then the "mret" instruction is executed to retrieve the instruction pointer from the control and status registers CSR in order to restore execution of the computer program from the address of the N_INST instruction which followed the last L_INST instruction of the computer program executed before putting the central processing unit into the conservation power mode.

[0101] Interrupt support by the INT_CTRL interrupt controller is then restored.

[0102] Execution of the computer program can then resume at step 24.

[0103] The system-on-chip and method described above use memories directly coupled to the central processing unit to store the execution context of a computer program executed by that central processing unit before entering a conservation power mode.

[0104] Thus, when the central processing unit is inactive, it is possible to stop the power supply to the central processing unit while maintaining sufficient power supply for said memories directly coupled to the central processing unit in order to maintain the execution context until the power supply to the central processing unit is resumed. This makes it possible to drastically reduce the energy consumption of the system on chip.

[0105] Furthermore, the preservation of the execution context in the memories directly coupled to the central processing unit allows a simple, rapid, complete and exact restoration of the execution context of the interrupted computer program once the power supply to the central processing unit is restored. The execution of the computer program can therefore be resumed quickly after restoring power to the central processing unit.

[0106] The system-on-chip and the method described above also have the advantage that the storage and retrieval of the execution context in the memories directly coupled to the central processing unit for entering and exiting the conservation power mode are performed by a state machine of the central processing unit and not by software. This makes it possible to perform the transition to and exit from the conservation power mode more simply, more quickly and accurately. This makes it possible in particular to ensure that the entire execution context is indeed stored and retrieved in said at least one data memory directly coupled to the central processing unit. In particular, such a system-on-chip is configured to restore context information in read-only registers that can only be modified by hardware and not by software.

[0107] The system-on-chip also has the advantage of not using additional, bulky low-power components such as dual-power flip-flops to maintain the execution context of the interrupted computer program.

Claims

Claims

1. System on chip comprising: - a central processing unit (CPU), - memories (TCPM, TCDM) directly coupled to the central processing unit (CPU), - a power controller (PCTRL) configured to place the central processing unit (CPU) and said memories (TCPM, TCDM): O in a normal operating power mode in which the central processing unit (CPU) and said memories (TCPM, TCDM) are powered by a normal operating supply voltage (Vcore), or O in a conservation power mode in which the central processing unit (CPU) is no longer powered and said memories (TCPM, TCDM) are powered by a conservation supply voltage (Vret) lower than said normal operating supply voltage (Vcore) and sufficient to preserve data stored in said memories (TCPM, TCDM),and wherein the central processing unit (CPU) is configured to: - execute a first sequence of micro-instructions before being placed in a conservation power mode, said first sequence of micro-instructions being adapted to copy, into at least one data memory (TCDM) directly coupled to the central processing unit (CPU), an execution context of a computer program whose execution by the central processing unit (CPU) is interrupted to enter a conservation power mode, - execute a second sequence of micro-instructions upon exiting the conservation power mode to recover the execution context stored in said memories in order to resume the execution of the interrupted computer program.,

2. The system-on-chip of claim 1, wherein the central processing unit comprises a power mode controller (RET_CTRL) configured to communicate with the power controller (PCTRL) to negotiate with the power controller (PCTRL) a transition to a conservation power mode.

3. A system-on-chip according to any one of claims 1 or 2, wherein the central processing unit comprises a control unit (CTRLU) configured to execute a state machine for executing micro-instructions to: - store the execution context in said at least one data memory (TCDM) directly coupled with the central processing unit (CPU) before entering the conservation power mode, - retrieve the execution context in said at least one data memory (TCDM) directly coupled with the central processing unit (CPU) upon exiting the conservation power mode.

4. A system-on-chip according to one of claims 1 to 3, wherein the central processing unit (CPU) is configured to execute instructions for entering and exiting the conservation power mode, these instructions being stored in at least one program memory (TCPM) coupled directly with the central processing unit (CPU).

5. System on chip according to one of claims 1 to 4, wherein the central processing unit (CPU) further comprises a register (SSP) configured to store an auxiliary stack pointer (SP2) configured to store the value of a main stack pointer before entering a conservation power mode, said first sequence of micro-instructions being configured to store said auxiliary stack pointer (SP2) in said at least one data memory (TCDM) directly coupled to the central processing unit (CPU) before entering the conservation power mode, said second sequence of micro-instructions being configured to retrieve the value of the auxiliary stack pointer for use as the main stack pointer.

6. System on chip according to one of claims 1 to 5, in which the power controller (PCTRL) is configured to, upon exiting the conservation power mode, transmit a signal (RET_CSE) making it possible to indicate to the central processing unit that the latter is returning from a conservation power mode, so that the central processing unit executes said second sequence of microinstructions.

7. Method for managing the power supply of a system on chip according to one of claims 1 to 6, the method comprising: - an execution by the central processing unit (CPU) of a first sequence of micro-instructions before being placed in a conservation power mode, said first sequence of micro-instructions being adapted to copy, into at least one data memory (TCDM) directly coupled to the central processing unit (CPU), an execution context of a computer program whose execution by the central processing unit (CPU) is interrupted to switch to a conservation power mode, - an execution by the central processing unit (CPU) of a second sequence of micro-instructions on exiting the conservation power mode to recover the execution context stored in said memories in order to resume the execution of the interrupted computer program.

8. The method of claim 7, comprising communicating between a power mode controller (RET_CTRL) of the central processing unit and the power controller (PCTRL) to negotiate a transition to a conservation power mode.

9. Method according to any one of claims 7 or 8, comprising an execution by the central processing unit of micro-instructions supplied by a state machine (FSM) of a control unit (CTRLU) of the central processing unit (CPU) to: - store the execution context in said at least one data memory (TCDM) directly coupled with the central processing unit (CPU) before switching to the conservation power mode, - retrieve the execution context in said at least one data memory (TCDM) directly coupled with the central processing unit (CPU) on exiting the conservation power mode.

10. Method according to one of claims 7 to 9, comprising an execution, by the central processing unit (CPU), of instructions for entering and exiting the conservation power mode, these instructions being stored in at least one program memory (TCPM) coupled directly with the central processing unit (CPU).

11. Method according to one of claims 7 to 10, further comprising storing an auxiliary stack pointer in a register (SSP) of the central processing unit (CPU), the auxiliary stack pointer making it possible to store the value of a main stack pointer before entering a conservation power mode, the execution of said first sequence of micro-instructions making it possible to store said auxiliary stack pointer (SP2) in said at least one data memory directly coupled to the central processing unit (CPU) before entering the conservation power mode, the execution of said second sequence of micro-instructions making it possible to retrieve the value of the auxiliary stack pointer for use as the main stack pointer.

12. Method according to one of claims 7 to 11, further comprising, at the output of the conservation power supply mode, a transmission by the power supply controller (PCTRL) of a signal (RET_CSE) making it possible to indicate to the central processing unit that the latter is returning from a conservation power supply mode, so that the central processing unit executes said second sequence of micro-instructions.

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