Manufacturing process of an SSOI structure

Abstract

Method for manufacturing an SSOI structure The present description relates to a method for manufacturing an SSOI structure comprising the following steps: - Providing a receiver substrate (10) comprising a first support substrate (11), - Providing a donor substrate (20) comprising a second support substrate (21) successively covered by a buffer layer, preferably made of SiGe (22), a strained silicon layer (23), an oxide layer (24) and an amorphous silicon layer (25), - Bringing the receiver substrate (10) and the donor substrate (20) into contact to form a bonding interface, - Carrying out a heat treatment at a temperature between 500 and 800°C to consolidate the bonding interface, - Removing the second support substrate (21) and the buffer layer (22), whereby an SSOI structure is obtained. Figure for abstract: Fig. 1A

Description

Title of the invention: Method for manufacturing an SSOI structure Technical field

[0001] The present description relates generally to the manufacture of microelectronic structures, and in particular to the manufacture of SSOI (“Strained Silicon On Insulator” type structures. Prior art

[0002] SSOI substrates comprise a substrate made of semiconductor material successively covered by an oxide layer (called buried oxide) then by a strained silicon layer.

[0003] Such stress can provide a semiconductor material with interesting electrical properties. For example, layers of strained silicon exhibit greater mobility of charge carriers (such as holes and electrons) than that usually found in relaxed silicon layers.

[0004] These substrates are of great interest for many applications in microelectronics or optics. In particular, these stacks are particularly promising for FD-SOI (“Fully Depleted SOI”) devices.

[0005] Until now, these substrates have been conventionally obtained by growing a thin silicon film on a so-called virtual SiGe substrate, then bonding the resulting assembly to a so-called receiver substrate, in particular made of silicon. The thin silicon film and the silicon wafer can be independently covered by an oxide layer. Thus, it is possible to have one of the following three bonding interfaces: an interface between two oxide layers, an interface between a strained silicon layer and an oxide layer, or an interface between an oxide covering the strained silicon and silicon.

[0006] Whatever the interface, a consolidation annealing of the bond is necessary. The annealings, for the various cases mentioned above, are of the order of 1000°C or even more (for example 1110°C), which causes several problems.

[0007] First of all, with such temperatures, the buried oxide tends to grow undesirably. However, a thin buried oxide (of the order of 10 nm) is desired. It is not possible to compensate for this growth by initially forming as thin an oxide as possible, without creating bonding difficulties.

[0008] Then, when such annealing is applied to a film of imperfect crystalline quality, the growth and multiplication of defects is favored.

[0009] In addition, the temperature increase must be slow so as not to deform the substrates, which lengthens the duration of the process and requires complex equipment. Summary of the invention

[0010] There is a need to manufacture an SSOI structure with a process implementing a low thermal budget, while having a good bonding interface.

[0011] This aim is achieved by a method of manufacturing an SSOI structure comprising the following steps: - Provide a receiving substrate comprising a first support substrate, - Providing a donor substrate comprising a second support substrate successively covered by a buffer layer, preferably SiGe, a strained silicon layer, an oxide layer and an amorphous silicon layer, - Bring the recipient substrate and the donor substrate into contact to form a bonding interface, - Carry out a heat treatment at a temperature between 500 and 800°C to consolidate the bonding interface, - Remove the second support substrate and the buffer layer, thereby obtaining an SSOI structure.

[0012] The invention is fundamentally distinguished from the prior art by the presence of an amorphous silicon layer, positioned under the buried oxide layer, at the bonding interface. Another amorphous silicon layer can be positioned on the receiving substrate. The bonding interface is therefore an interface between a silicon substrate and an amorphous silicon layer or an interface between two amorphous silicon layers.

[0013] Such interfaces allow the implementation of a consolidation annealing of the bonding at moderate temperatures (less than or equal to 800°C). The implementation of such temperatures limits the undesirable growth of the oxide layer and avoids the formation of defects and / or dislocations in the final SSOI substrate. Even if the annealing temperatures are lower than the temperatures conventionally implemented (typically 1000°C), they allow the bonding interface to be well closed.

[0014] Advantageously, the amorphous silicon layer has a thickness of between 5 nm and 10 nm.

[0015] Advantageously, the receiving substrate comprises the first support substrate and an additional layer of amorphous silicon.

[0016] Advantageously, the additional layer of amorphous silicon has a thickness of between 5 nm and 10 nm.

[0017] According to a first advantageous embodiment variant, the bonding is a hydrophilic bonding.

[0018] According to another advantageous embodiment variant, the bonding is a hydrophobic bonding.

[0019] Advantageously, the first support substrate is a substrate made of a semiconductor material, preferably silicon.

[0020] Advantageously, the second support substrate is a substrate made of a semiconductor material, preferably silicon.

[0021] The invention also relates to an SSOI structure obtained by such a method. The SSOI structure successively comprises a first support substrate, an amorphous silicon layer, an oxide layer, a strained silicon layer.

[0022] The oxide layer has a small thickness, typically less than 15 nm, preferably about 10 nm. This thin buried oxide layer has few or no defects.

[0023] Advantageously, the amorphous silicon layer has a thickness of between 5 and 10 nm.

[0024] Advantageously, an additional layer of amorphous silicon is arranged between the first support substrate and the layer of amorphous silicon.

[0025] Such a structure does not have any defects at the bonding interface (in particular there is no detachment). The interface is homogeneous. The structure can thus be used for the subsequent manufacture of microelectronic components.

[0026] Such a structure is particularly interesting for applications in microelectronics, optoelectronics or optics. Brief description of the drawings

[0027] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0028] [Fig.lA], [Fig.lB] and [Fig.lC] schematically represent different steps of a method of manufacturing an SSOI substrate according to a particular embodiment of the invention;

[0029] [Fig.2A], [Fig.2B] and [Fig.2C] schematically represent different steps of a method of manufacturing an SSOI substrate according to another particular embodiment of the invention.

[0030] For reasons of clarity of the figures, the different elements are not represented on a homogeneous scale. Description of the embodiments

[0031] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the modes of the described embodiments have been represented and are detailed.

[0033] In the following description, when referring to relative position qualifiers, such as the terms "on", "under", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] We will now describe in more detail the method of manufacturing an SSOI structure with reference to Figures 1A to 1C and to Figures 2A to 2C.

[0036] The method of manufacturing an SSOI substrate comprises the following steps: a) Providing, on the one hand, a receiving substrate 10 comprising a first support substrate 11, and on the other hand, a donor substrate 20 comprising a second support substrate 21 successively covered by a buffer layer 22, preferably made of SiGe, a strained silicon layer 23, an oxide layer 24 and an amorphous silicon layer 25 (figures 1A and 2A), b) Bringing the receiving substrate 10 and the donor substrate 20 into contact to form a bonding interface (figures 1B and 2B), c) Carry out a heat treatment to consolidate the bonding interface, the heat treatment being carried out at a temperature between 500 and 800°C, d) Removing the second support substrate 21 and the buffer layer 22, whereby an SSOI structure is obtained (figures IC and 2C).

[0037] According to a particular embodiment, the receiving substrate 10 is made up of the first support substrate 11.

[0038] According to another particular embodiment, the receiving substrate 10 comprises the first support substrate 11 and an additional amorphous silicon layer 12.

[0039] An oxide layer, for example, a native oxide layer, may be arranged between the first support substrate 11 and the additional amorphous silicon layer 12. The native oxide layer is, for example, a silicon oxide layer in the case of a silicon substrate.

[0040] The first support substrate 11 is preferably a substrate made of semiconductor material, preferably silicon.

[0041] The donor substrate 20 provided in step a) comprises the second support substrate 21 successively covered by the buffer layer 22, preferably made of SiGe, the strained silicon layer 23, the oxide layer 24 and the amorphous silicon layer 25.

[0042] The second support substrate 21 is preferably a substrate made of semiconductor material, preferably silicon.

[0043] The second support substrate 21 may be a bulk substrate, preferably made of silicon.

[0044] According to another variant embodiment, the second support substrate 21 can comprise a layer of semiconductor material, preferably silicon, and one or more other layers, for example it may comprise a layer of electrically insulating material, such as SiO2.

[0045] The buffer layer 22 (also noted TGB for “Thick Graded Buffer”) is, preferably, a SiGe layer. It contains for example 20 at% of Ge. The buffer layer can be a bilayer formed of a first part in SiGe having an increasing gradient of Ge from the support substrate 21 and a second part having a constant atomic percentage of Ge (20 at% for example). The first part of the buffer layer is in contact with the second support substrate 21. The second part of the buffer layer is in contact with the strained layer 23.

[0046] The buffer layer 22 can be formed by epitaxy. For example, to form such a layer by epitaxy, it is possible to carry out, in a first step, a so-called gradual epitaxy of SiGe having a gradient in atomic percentage of Ge ranging, for example, from 0% to 20% at from the second support substrate 21, then to carry out an epitaxy of SiGe with a constant percentage of Ge, for example 20% at.

[0047] The strained silicon layer 23 has a thickness of, for example, between 2 nm and 200 nm, advantageously between 10 and 25 nm on SiGe, preferably on SiGe at 20% at.

[0048] The strained silicon layer 23 is a layer whose crystallographic structure is strained in tension or compression depending on the use of the final structure. The crystallographic structure can be strained in tension or compression during crystal growth, preferably by epitaxy, which makes it possible to modify the crystal lattice in the growth direction.

[0049] The oxide layer 24 is a layer known as a buried oxide layer (BOX for “Buried OXide”). It is preferably a silicon oxide layer. This layer 24 may be a thermal oxide layer or a deposited oxide layer. Preferably, it is a thermal oxide. Such oxides are of better quality. This oxide will, advantageously, be obtained with a minimal thermal budget.

[0050] The amorphous silicon layer 25 preferably has a thickness of more than 5 nm. This layer can be formed, for example, by a chemical vapor deposition technique, in particular by low pressure chemical vapor deposition (LPCVD) or by reduced pressure chemical vapor deposition (RPCVD).

[0051] Before implementing step b), a suitable surface treatment is advantageously carried out on the receiving substrate 10 and / or on the donor substrate 20.

[0052] For example, the surface treatment may consist of carrying out one or more of the following treatments: mechanical and / or chemical polishing, chemical treatment, UV / Ozone treatment, RIE (“Reactive Ion Etching”) treatment, plasma treatment, hydrogen annealing, etc.

[0053] During step b), the donor substrate 20 and the receiving substrate 10 are brought into contact to form a bonding interface. More particularly, either the amorphous silicon layer 25 and the first support substrate 11 are brought into contact or the amorphous silicon layer 25 and the additional amorphous silicon layer 12 are brought into contact. The bonding between the donor substrate 20 and the receiving substrate 10 is a silicon-silicon type bonding.

[0054] The bonding interface may be the interface between the first support substrate 11 and the amorphous silicon layer 25 or the interface between the additional amorphous silicon layer 12 and the amorphous silicon layer 25.

[0055] This may be a so-called hydrophilic bond, i.e. the adhesion occurs between two hydrophilic surfaces, i.e. between two surfaces having the capacity to bond via water molecules present at the bonding interface. Hydrophilic surfaces are typically terminated by hydroxyl groups.

[0056] To implement hydrophilic bonding, a hydrophilic treatment of the surfaces to be bonded will be implemented, before step b). For example, this may involve SCI-type cleaning followed by rinsing with water. At the end of this step, the surfaces are covered with a thin film of water (of the order of 2 or 3 monolayers) bonded to the main face by hydrogen bonds.

[0057] According to another embodiment variant, the bonding is a so-called hydrophobic bonding, that is to say that the surfaces do not have the capacity to adsorb water molecules. The surfaces are for example saturated with hydrogen and / or fluorine atoms.

[0058] In order to achieve hydrophobic bonding, the surfaces to be bonded may be treated, prior to bonding, with hydrofluoric acid. Such a treatment is, for example, described in the article by Fournel et al. (ECS Trans. 2006, 3 (6), 139-146).

[0059] The bonding can be carried out at ambient pressure or under vacuum (for example with a vacuum greater than 1.103 mbar). This embodiment is particularly advantageous in the case of hydrophilic bonding. Such bonding of hydrophilic surfaces is for example described in document US 2022 / 0319910 AL

[0060] Alternatively, the bonding can be carried out under ultra-high vacuum (or UHV for “Ultra High Vacuum” in English terms).

[0061] Preferably, the bonding is a SAB (“Surface Activated Bonding”) bonding. For this, the surfaces of the amorphous silicon layers 12, 25 are ion-bombarded under ultra-high vacuum before being brought into contact. The contacting can be carried out at room temperature (typically between 20 and 25°C).

[0062] Alternatively, the collage may be an ADB (“Atomic Diffusion Bonding”). The bonding of the two amorphous silicon layers 12, 25 is carried out under UHV.

[0063] Such collages are, for example, described in the articles of Suga et al. (7th Electronic System-Integration Technology Conference (ESTC), 2018, 1-4) and Amino et al. (Japanese J. Appl. Phys., 2022, 61, SF1002).

[0064] Hydrophilic and hydrophobic bonds are preferred over ADB and SAB bonds for their ease of implementation and cost.

[0065] Even more preferably, the bonding is a hydrophilic bonding.

[0066] During step c), a heat treatment to consolidate the bonding is carried out. This heat treatment is, for example, carried out at a temperature between 500°C and 800°C, and preferably between 500°C and 700°C.

[0067] This consolidation annealing of the bond is carried out at a moderate temperature, compatible with Si-Si bonding.

[0068] In step d), the second support substrate 21 and the buffer layer 22 are removed, whereby an SSCI structure is obtained.

[0069] This separation step can be carried out by a Smart Cut™ type process. For a Smart Cut™ type process, hydrophilic bonding will be preferred.

[0070] In order to implement the Smart Cut™ type method, between step a) and step b), a step of implanting ionic species, such as hydrogen and / or helium, in the donor substrate 20 through the amorphous silicon layer 25 and the oxide layer 24 is carried out so as to form a weakening zone delimiting the part of the silicon layer 23 to be transferred. The fracture of the donor substrate 20 takes place along the weakening zone, which makes it possible to detach the remainder of the donor substrate 20 and transfer the thin silicon layer 23 onto the receiving substrate 10.

[0071] Advantageously, the consolidation annealing of the bond implemented during step c) makes it possible to produce the fracture along the weakening line. In other words, with a Smart Cut™ type process, steps c) and d) are carried out simultaneously.

[0072] Alternatively, the separation step can be carried out by physical removal carried out by grinding from the face of the donor substrate 20 opposite the bonding interface, followed by chemical attack for example.

[0073] The structure thus obtained is an SSOI structure successively comprising a support substrate 11, an amorphous silicon layer 25, a buried oxide layer 24 and a strained silicon layer 23. The silicon layer 23 can be strained in tension or in compression.

[0074] According to an alternative embodiment, the structure further comprises, between the support substrate 11 and the amorphous silicon layer 25, an additional layer of amorphous silicon 12.

[0075] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0076] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

[0077] Illustrative and non-limiting example of a particular embodiment

[0078] In this example, the donor substrate 20 is manufactured according to the following steps: - on a support substrate 21 (also called a virtual substrate), for example a solid silicon substrate, form a SiGe buffer layer 22 by carrying out a gradual epitaxy of SiGe from 0 to 20% over a thickness of 2 pm then an epitaxy of SiGe at 20% over a thickness of 0.5 pm to 2 pm, - polish the buffer layer 22 of SiGe at 20%at by chemical-mechanical polishing, - deposit a layer of strained silicon 23 by epitaxy, then clean the resulting layer, - carry out thermal oxidation of the silicon layer 23, at low temperature (typically 700°C) so as to obtain an oxide layer 24 of 25 nm, - form a layer of amorphous silicon 25 by LPCVD or RPCVD on the oxide layer, - carry out an implantation in order to be able to subsequently implement the fracture.

[0079] The receiving substrate 10 is manufactured according to the following steps: - provide a support substrate 11 in silicon covered by a layer of native oxide, - clean the substrate by a chemical treatment of the SCI or ozone type, - deposit a layer of amorphous silicon 12, by LPCVD or RPCVD.

[0080] The donor substrate 20 and the recipient substrate 10 are then assembled by gluing.

[0081] A low-temperature consolidation annealing is then carried out at low temperature (for example at 500°C). The consolidation annealing simultaneously allows the fracture to be produced and an SSOI structure to be obtained.

Claims

Claims

1. A method of manufacturing an SSOI structure comprising the following steps: - Providing a receiver substrate (10) comprising a first support substrate (11), - Providing a donor substrate (20) comprising a second support substrate (21) successively covered by a buffer layer, preferably made of SiGe (22), a strained silicon layer (23), an oxide layer (24) and an amorphous silicon layer (25), - Bringing the receiver substrate (10) and the donor substrate (20) into contact to form a bonding interface, - Carrying out a heat treatment at a temperature between 500 and 800°C to consolidate the bonding interface, - Removing the second support substrate (21) and the buffer layer (22), whereby an SSOI structure is obtained.

2. Method according to claim 1, characterized in that the amorphous silicon layer (25) has a thickness of between 5 nm and 10 nm.

3. Method according to one of the preceding claims, characterized in that the receiving substrate (10) comprises the first support substrate (11) and an additional layer of amorphous silicon (12).

4. Method according to the preceding claim, characterized in that the additional layer (12) of amorphous silicon has a thickness of between 5 nm and 10 nm.

5. Method according to any one of claims 1 to 4, characterized in that the bonding is a hydrophilic bonding.

6. Method according to any one of claims 1 to 4, characterized in that the bonding is a hydrophobic bonding.

7. Method according to any one of the preceding claims, characterized in that the first support substrate (11) is made of a semiconductor material, preferably silicon.

8. Method according to any one of the preceding claims, characterized in that the second support substrate (21) is made of a semiconductor material, preferably silicon.

9. SSOI structure successively comprising a first support substrate (11), an amorphous silicon layer (25), an oxide layer (24) and a strained silicon layer (23).

10. SSOI structure according to claim 9, characterized in that the layer of amorphous silicon (25) has a thickness between 5 and 10 nm.

11. Structure according to one of claims 9 and 10, characterized in that an additional layer (12) of amorphous silicon is arranged between the first support substrate (11) and the layer of amorphous silicon (25).

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