Electronic device

Abstract

Electronic Device The present description relates to an optoelectronic device comprising at least one pixel comprising: - a first semiconductor region (14); - a second semiconductor region (16) of a conductivity type different from the first conductivity type, resting on the first region (14); - a photodiode (22) resting on the second region (16), the photodiode (22) comprising a third semiconductor region (24), the third region (24) being in contact with the second region (16) and being separated from the first region (14) by the second region (16); and - a first conductive and insulated element (20), extending in the second region (16), being configured to be biased by a first voltage, during a first operating step, so as to allow the passage of charges from the third region (24) to the first region (14). Figure for abstract: Fig. 1A

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more particularly to optoelectronic devices comprising photodiodes. Prior art

[0002] A photodiode is a semiconductor component having the capacity to capture radiation from the optical domain and to transform it into an electrical signal. Summary of the invention

[0003] One embodiment provides an optoelectronic device comprising at least one pixel, the pixel comprising: - a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, different from the first conductivity type, lying on the first region; - a photodiode lying on the second region, the photodiode comprising a third semiconductor region of the first conductivity type, the third region being in contact with the second region and being separated from the first region by the second region; and - a first conductive and insulated element, extending in the second region, the first element being configured to be biased by a first voltage, during a first operating step, so as to allow the passage of charges from the third region to the first region.

[0004] Another embodiment provides a method for controlling an optoelectronic device comprising at least one pixel, the pixel comprising: - a first semiconductor region of a first conductivity type; - a second semiconductor region of a second conductivity type, different from the first conductivity type, resting on the first region; - a photodiode resting on the second region, the photodiode comprising a third semiconductor region of the first conductivity type, the third region being in contact with the second region and being separated from the first region by the second region; and - a first conductive and insulated element, extending in the second region, the method comprising a first operating step during which the conductive core of the first element is biased by a first voltage so as to allow the passage of charges from the third region to the first region.

[0005] According to one embodiment, the first element is a via comprising a conductive core and an insulating sheath extending through the first and second regions.

[0006] According to one embodiment, the conductive core of the first element comprises a first portion surrounded by the first region and a second portion surrounded by the second region, the second portion having horizontal dimensions greater than the horizontal dimensions of the first portion.

[0007] According to one embodiment, the photodiode comprises the third doped region of the first conductivity type and a fourth doped region of the second conductivity type, the third region comprising first and second layers forming a heterojunction, the first layer being made of a semiconductor material and the second layer comprising quantum dots, the fourth region being in contact with the second layer, the concentration of dopants of the first layer being greater than that of the second layer.

[0008] According to one embodiment, the pixel comprises a first insulated conductive wall surrounding the first region, the first wall being configured to be biased so as to deplete the first region.

[0009] According to one embodiment, the pixel comprises a second insulating wall surrounding the first region, and a second insulated conductive element extending into the first region.

[0010] According to one embodiment, the first region is divided into first and second parts, the first element being located in the second region, facing the first part of the first region, the first and second parts of the first region being separated by a third insulating wall, the pixel comprising a third element, the third element being conductive and insulated, the third element extending in the second region facing the second part of the first region, the third element being configured to be biased by a second voltage, during a second operating step, so as to allow the passage of charges from the third region to the second part of the first region.

[0011] According to one embodiment, the pixel is configured so that, during the first operating step, the third element is biased by a third voltage so as to block the passage of charges from the third region to the second part of the first region and in which the pixel is configured so that, during the second operating step, the first element is biased by a fourth voltage so as to block the passage of charges from the third region to the first part of the first region.

[0012] According to one embodiment, the first region is divided into at least two first parts and a second part, the pixel comprising as many first elements as first parts, each first element being located in the second region opposite one of the first parts of the first region, the first and second parts of the first region being separated from each other by a third insulating wall, the pixel comprising a third element, the third element being conductive and insulated, the third element extending into the second region opposite the second part of the first region, the third element being configured to be biased by a second voltage, during a second operating step, so as to allow the passage of charges from the third region to the second part of the first region.

[0013] According to one embodiment, the pixel comprises as many second insulated conductive elements as there are first parts of the first region, each second element extending into one of the first parts of the first region.

[0014] According to one embodiment, during the first operating step, the third element is biased by a third voltage so as to block the passage of charges from the third region to the second part of the first region and in which the pixel is configured so that, during the second operating step, the first elements are biased by a fourth voltage so as to block the passage of charges from the third region to the first parts of the first region.

[0015] According to one embodiment, the first region is divided into at least two first parts, the pixel comprising as many first elements as first parts, each first element being located in the second region opposite one of the first parts of the first region.

[0016] According to one embodiment, the pixel is configured to comprise a succession of steps, each step comprising the application of a voltage to the first element of one of the first parts so as to allow the passage of charges towards said first part and the application of a voltage to the other first elements so as to block the passage of charges towards the other first parts.

[0017] According to one embodiment, each first portion is surrounded by a first insulated conductive wall, the first wall being configured to be polarized so as to deplete said first region. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.1A] represents a sectional view of an embodiment of an electronic device;

[0020] [Fig.lB] represents a top view of the embodiment of [Fig.lA];

[0021] [Fig.2A] represents a sectional view of another embodiment of a device electronics;

[0022] [Fig.2B] represents a top view of the embodiment of [Fig.2A];

[0023] [Fig.3] represents a sectional view of another embodiment of an electronic device;

[0024] [Fig.4A] and [Fig.4B] illustrate the operation of the embodiment of the [Fig.3] ;

[0025] [Fig.5A] represents a sectional view of another embodiment of an electronic device;

[0026] [Fig.5B] represents another sectional view of the embodiment of [Fig.5A];

[0027] [Fig.5C] represents a top view of the embodiment of [Fig.5A];

[0028] [Fig.5D] represents another sectional view of the embodiment of [Fig.5A];

[0029] [Fig.6A] represents a sectional view of another embodiment of a device electronics; and

[0030] [Fig.6B] represents a top view of the embodiment of [Fig.6A]. Description of the embodiments

[0031] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0032] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been represented and are detailed.

[0033] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0034] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0035] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0036] [Fig.lA] represents a sectional view of an embodiment of an electronic device. [Fig.lB] represents a top view of the embodiment of [Fig.lA]. More specifically, [Fig.lA] is a sectional view along plane AA of [Fig.lB] and [Fig.lB] is a top view along plane BB of [Fig.lA].

[0037] The device is for example an optoelectronic device. The device comprises at least one pixel 10, preferably a plurality of pixels, for example at least one hundred pixels, for example at least a thousand pixels. For example, the pixels are arranged in a matrix. The device is, for example, configured to generate one or more electrical signals upon receiving light signals. For example, the device is a camera or a light sensor, for example a time-of-flight sensor.

[0038] The pixel 10 is located in and on a substrate 12. The substrate 12 is made of a semiconductor material, for example silicon. The substrate 12 comprises a first face 12a, or lower face, and a second face 12b, or upper face, opposite the first face 12a. Electronic components, not shown, are located in and on the substrate 12 on the side of the first face 12a. Thus, transistors can be formed in and on the substrate 12, more precisely on the side of the face 12a. The transistors comprise, for example, a source region and a drain region flush with the face 12a and a gate located on the face 12a. An interconnection network, not shown, i.e. a stack of insulating layers comprising conductive tracks and conductive vias so as to allow electrical connections, is for example located on the face 12a of the substrate.

[0039] The pixel 10 comprises a storage region 14. The region 14 corresponds to a doped well of the substrate 12. The well 14 is located on the side of the face 12b. Preferably, the well 14 is separated from the face 12a of the substrate 12 by the portions of the substrate in which the electronic components, for example the transistors, are located. The well 14 is made of a semiconductor material, for example the same material as the substrate 12, for example silicon. The well 16 is for example N-type doped. The well 14 is for example made of a single material, for example homogeneous. The concentration of dopants in the well 14 is for example between 5*1015 cm3 and 5*1016 cm3.

[0040] The pixel 10 further comprises another region 16. The region 16 corresponds to a doped well of the substrate 12. The well 16 is located on the side of the face 12b. Preferably, the well 16 is flush with the face 12b of the substrate 12. The well 16 is made of a semiconductor material, for example the same material as the substrate 12, for example silicon. The well 16 is doped with the type opposite to the doping type of the region 14, for example P type. The well 16 is for example made of a single material, for example homogeneous. The concentration of dopants in the well 16 is for example between 10 cm and 5*10 cm . The upper face of the well 14 is preferably in contact with the lower face of the well 16.

[0041] The pixel 10 comprises a wall 18. The wall 18 is conductive and insulated. In other words, the wall 18 comprises a conductive core, for example made of metal, and an insulating outer sheath surrounding the conductive core at least laterally. The wall 18 surrounds laterally the boxes 14 and 16. The side walls of the boxes 14 and 16 are for example in contact with the side walls of the sheath of the wall 18.

[0042] The wall 18 extends at least over the height of the boxes 14 and 16. In other words, the wall 18 extends at least along the side walls of the boxes 14 and 16. Preferably, the wall 18 extends over the entire height of the substrate 12.

[0043] The electronic components located in the region of the substrate 12 surrounded by the wall 18 are for example components associated with the pixel, for example the components forming the control circuit of the pixel or components of the circuit for processing the information obtained by the pixel.

[0044] The conductive core of the wall 18 is configured to receive a voltage. The core of the wall 18 is for example connected to a node for applying said voltage by conductive tracks and conductive vias of the interconnection network not shown. Said voltage is preferably configured to allow the depletion of the well 14.

[0045] The pixel further comprises an element 20. The element 20 comprises a conductive core 20a and an insulating sheath 20b. The element 20 preferably extends at least over the height of the wells 14 and 16. The element 20 extends for example over the entire height of the substrate 12, that is to say from the face 12a to the face 12b. At the end of the element 20 flush with the face 12a, the conductive core 20a is for example uncovered, that is to say is for example not covered by the sheath 20b, so as to be electrically connected to a voltage source, for example by means of conductive tracks and conductive vias of the interconnection network not shown.

[0046] The conductive core 20a of the element 20 preferably comprises two parts 20a 1 and 20a2. The parts 20a 1 and 20a2 are in contact. Thus, the part 20a 1 comprises a lower end in contact with the upper end of the part 20a2. The part 20a 1 preferably has horizontal dimensions greater than the horizontal dimensions of the part 20a2. By horizontal is meant in a plane parallel to the section plane BB.

[0047] The part 20al is located at the level of the box 16. In other words, the part 20al preferably has a height less than or equal to the height of the box 16. More precisely, the portion of the element 20 comprising the part 20a 1 is surrounded laterally by the box 16. Preferably, the portion of the element 20 comprising the part 20al is not surrounded laterally by the box 14. The upper end of the part 20al is preferably covered by the sheath 20b.

[0048] The part 20a2 is located at the level of the box 14. The part 20a2 preferably extends from the face 12a to the lower end of the part 20a 1, for example located at the level of the interface between the box 14 and the box 16. More precisely, the portion of the element 20 comprising the part 20a2 is surrounded laterally by the box 14, by the portion of the substrate 12 comprising the electronic components not shown, and possibly by a portion of the box 16.

[0049] The element 20 preferably extends in a central portion of the pixel. Thus, the element 20 is separated from the wall 18, preferably from all portions of the wall 18, by portions of the substrate 12.

[0050] The pixel 10 further comprises a photodiode 22. The photodiode is located on the face 12b of the substrate. Preferably, the photodiode 22 is in contact with the face 12b, preferably in contact with the well 16 and with the element 20. Preferably, the photodiode 22 covers the entire portion of the substrate 12 corresponding to the pixel. Thus, the photodiode preferably covers the entire portion of the substrate 12 surrounded by the wall 18.

[0051] The photodiode 22 may be any type of photodiode comprising a semiconductor layer 24 in the same type of doping as the well 14, for example N-type doped. The layer 24 is preferably in contact with the face 12b, preferably in contact with the well 16 and with the element 20. Preferably, the layer 24 covers the entire portion of the substrate 12 corresponding to the pixel 10. Thus, the layer 24 preferably covers the entire portion of the substrate 12 surrounded by the wall 18.

[0052] In the example of figures 1A and 1B, the layer 24 is made of a semiconductor material, for example the same material as the substrate 12, for example silicon. The layer 24 forms a portion of the cathode of the photodiode. The layer 24 is for example made of a single material, for example homogeneous. The concentration of dopants in the layer 24 is for example substantially equal to 1016 dopants per cm 3.

[0053] Pixel 10 comprises a transistor composed of boxes 14, 16, layer 24 and element 20.

[0054] In the example of figures 1A and 1B, the photodiode 22 comprises a layer 26. The layer 26 covers the upper face of the layer 24. More precisely, the layer 26 covers at least the portion of the layer 24 corresponding to the pixel 10, that is to say being located opposite the portion of the substrate 12 surrounded by the wall 18. The layer 26 preferably covers the layer 24. The layer 26 is preferably in contact with the layer 24.

[0055] Layer 26 constitutes another part of the cathode of the pixel photodiode. Layer 26 comprises quantum dots of the same conductivity type as layer 24, for example N-type. Layer 26 constitutes the photosensitive layer of the photodiode.

[0056] A quantum dot or semiconductor nanoparticle is a nanoscopic material structure that produces electron-hole pairs in the presence of the incidence of photons on the nanoscopic material structure.

[0057] A quantum dot comprises a semiconductor core. A quantum dot may also comprise a shell, preferably of a semiconductor material, surrounding the core to protect and passivate the core. A quantum dot further comprises ligands, organic aliphatic compounds, organometallic or inorganic molecules that extend from the shell and passivate, protect, and functionalize the semiconductor surface.

[0058] The composition of a quantum dot can be chosen from the following materials. The core is, for example, made of a material from among the following materials or from an alloy of the following materials: CdSe, CdS, CdTe, CdSeS, CdTeSe, AgS, ZnO, ZnS, ZnSe, CuInS, CuInSe, CuInGaS, CuInGaSe, PbS, PbSe, PbSeS, PbTe, InAsSb, InAs, InSb, InGaAs, InP, InGaP, InAlP, InGaAlP, InZnS, InZnSe, InZnSeS, HgTe, HgSe, HgSeTe, Ge, Si. The shell is, for example, made of a material from among the following materials or from an alloy of the following materials: CdSe, CdS, CdTe, CdSeS, CdTeSe, AgS, ZnO, ZnS, ZnSe, CuInS, CuInSe, CuInGaS, CuInGaSe, PbS, PbSe, PbSeS, PbTe, InAsSb, InAs, InSb, InGaAs, InP, InGaP, InAlP, InGaAlP, InZnS, InZnSe, InZnSeS, HgTe, HgSe, HgSeTe, Ge, Si.

[0059] Preferably, all dimensions of the core are less than 20 nm, for example in the range from 2 to 15 nm. In particular, the diameter of each quantum dot is preferably in the range from 2 to 15 nm. By diameter is meant the diameter of the smallest sphere in which the quantum dot can be inscribed.

[0060] It is possible to choose a size and dimension of quantum dots capable of absorbing, with significant absorption, any wavelength in a wide range of wavelengths. For example, it is possible to find a size and dimension of the quantum dots having an operating wavelength greater than 300 nm, for example between 300 nm and 3000 nm, which includes the visible, the infrared, the near infrared and the short infrared. For example, the layer 26 comprises quantum dots made of lead sulfide, for example quantum dots having a radius of less than 10 nm, to obtain an absorption peak linked to quantum confinement in the infrared, while allowing the absorption of wavelengths in the visible.

[0061] The layer 26 has for example a thickness between 100 nm and 500 nm. The box 16 has for example a thickness between 2 pm and 10 pm.

[0062] The doping of layer 26, for example between 1015 dopants per cm3 and 1016 dopants per cm\ is lower than the doping of layer 24, i.e. the concentration of dopants in layer 24, so as to allow layer 26 to be entirely depleted by layer 24 and a voltage applied to the anode of the photodiode.

[0063] The interface between layer 26 and layer 24 forms a heterojunction. Preferably, the upper face of layer 24 is treated, for example before the formation of layer 26, so as to ensure the formation of the heterojunction. The upper face of layer 24 is for example treated with a self-assembled monolayer (SAM), for example made of Ch3I or one or more other halogenated compounds. The monolayer is for example replaced by a thin layer of metal oxide, for example made of ZnO. The upper face of layer 24 is for example treated with a halogen treatment.

[0064] The pixel 10 further comprises a layer 28. The layer 28 is a hole extraction layer. The layer 28 is of the conductivity type opposite to the conductivity type of the layers 24 and 26, for example of the P type. The layer 28 is for example made of a P type doped metal oxide or comprises for example quantum dots behaving like a P type material due to the position of its Fermi level relative to the Fermi level of the material of the layer 26. The layer 28 corresponds to the anode of the photodiode. The layer 28 is transparent to the operating wavelengths of the pixel.

[0065] Layer 28 covers the upper face of layer 26. Preferably, layer 28 covers at least the portion of layer 26 located opposite layer 24. Layer 28 is preferably in contact with layer 26, for example at least with the portion of layer 26 located opposite wells 14 and 16. The interface between layer 26 and layer 28 corresponds to a PN junction of the photodiode making it possible to extract the photo-generated carriers, the photo-generated carriers being holes in the case of an N-doped layer 24.

[0066] The pixel 10 further comprises a layer 30. The layer 30 is a conductive layer, for example made of metal oxide. The layer 30 is transparent to the operating wavelengths of the pixel. The layer 30 is for example made of MoO3, ITO, Va2O5, NiO, CuO, or sub-stoichiometric WO3. The layer 30 is part of the anode of the photodiode in the case where it is used to collect holes.

[0067] The layer 30 covers the upper face of the layer 28. Preferably, the layer 30 covers at least the portion of the layer 28 located opposite the boxes 14 and 16. The layer 30 is preferably in contact with the layer 28, for example at least with the portion of the layer 26 located opposite the box 16.

[0068] The operation of the pixel comprises first steps during which a first voltage is applied to the element 20 and second steps during which a second voltage is applied to the element 20.

[0069] The first voltage is configured to turn off a vertical insulated gate field effect transistor (MOSFET), said transistor being composed of the element 20 forming the gate and by the wells 14, 16 and the layer 24 serving as a channel. Thus, during the first steps, the charges located in the layer 24 are maintained in the layer 24. For example, the first steps correspond to measurement steps, in which charges are generated by the photodiode 22. Preferably, a part of the charges, for example the electrons if the layer 24 is doped with N type, is stored in the layer 24 and the other part of the charges, for example the holes, are attracted towards the layer 30.

[0070] The second voltage is configured to turn on a MOSFET transistor, said transistor being composed of the element 20 forming the gate and by the wells 14, 16 and the layer 24 serving as a channel. Thus, during the second steps, the charges located in the layer 24 are transmitted into the well 14. For example, the second steps correspond to storage steps.

[0071] For example, the charges stored in the box 14 can be read, that is to say supplied to a reading circuit for example located in the substrate 12, during the first steps.

[0072] The operation of the pixel 10 comprises, for example, an alternation of first and second steps. Thus, the operation of the pixel 10 may comprise, periodically, second steps, the second steps being separated from each other by first steps.

[0073] [Fig.2A] represents a sectional view of another embodiment of an electronic device. [Fig.2B] represents a top view of the embodiment of [Fig.2A]. More specifically, [Fig.2A] is a sectional view along plane AA of [Fig.2B] and [Fig.2B] is a top view along plane BB of [Fig.2A].

[0074] The device is for example, like the device 10 of figures 1A and 1B, an optoelectronic device. The device comprises at least one pixel 32, preferably a plurality of pixels 32, for example at least one hundred pixels, for example at least a thousand pixels. For example, the pixels 32 are arranged in a matrix. The device of figures 2A and 2B is for example configured to generate one or more electrical signals upon reception of light signals. For example, the device is a camera or a light sensor, for example a time-of-flight sensor.

[0075] Pixel 32 comprises elements of pixel 10 which will not be described again in detail. In particular, pixel 32 comprises: - the substrate 12, having faces 12a and 12b; - boxes 14 and 16 in substrate 12; - element 20 located in substrate 12; and - layers 26, 28, 30.

[0076] Pixel 32 differs from pixel 10 in that pixel 32 does not include layer 24, but includes a well 24'. Well 24' is a doped well of the substrate 12. The well 24' is located on the side of the face 12b. Preferably, the well 24' is flush with the face 12b of the substrate 12. The well 24' is made of a semiconductor material, for example the same material as the substrate 12, for example silicon. The well 24' is doped with the same type of doping as the region 14, for example N-type. The well 24' is for example made of a single material, for example homogeneous. The concentration of dopants in the well 24' is for example between 5*1015 cm 3 and 5*1016 cm 3, for example equal to the concentration of dopants of the layer 24 of figures 1A and 1B.

[0077] Thus, in figures 2A and 2B, the box 16 is not flush with the face 12b of the substrate 12. The box 16 is buried in the substrate 12. The box is located between the box 24' and the box 14. The upper face of the box 14 is preferably in contact with the lower face of the box 16. The upper face of the box 16 is preferably in contact with the lower face of the box 24'.

[0078] The element 20 extends, as in figures 1A and 1B, from the face 12a to the upper face of the box 16. In figures 2A and 2B, the element 20 does not extend to the face 12b of the substrate 12. In other words, the element 20 preferably does not extend into the box 24'.

[0079] Pixel 32 differs from pixel 10 further in that pixel 32 does not include wall 18 surrounding wells 14 and 16. Pixel 32 includes an insulating wall 34. Wall 34 is preferably made entirely of an insulating material, for example silicon oxide. Wall 34 replaces wall 18. Thus, wells 14 and 16 are surrounded, as in FIGS. 1A and 1B, by wall 34. Wells 14, 16, 24' are surrounded by wall 34. Like wall 18, wall 34 preferably extends over the entire height of substrate 12, i.e. from face 12a to face 12b. Thus, in Figures 2A and 2B, the wall 34 extends at least over the entire height of the boxes 14, 16, and 24'.

[0080] The pixel 32 further comprises an element 36. The element 36 is for example an insulated conductive via. In other words, the element 36 comprises a conductive core, for example made of metal, and an insulating outer sheath surrounding the conductive core at least laterally. The element 36 passes through the wells 14 and 16. In other words, the element 36 preferably extends at least over the height of the wells 14 and 16. The element 20 extends for example from the face 12a to the upper face of the well 16.

[0081] At the end of the element 36 flush with the upper face of the box 16, the conductive core is for example insulated, i.e. is for example covered by the insulating sheath. At the end of the element 36 flush with the face 12a, the conductive core is for example uncovered, i.e. is for example not covered by the insulating sheath, so as to be electrically connected to a voltage source, for example by means of conductive tracks and conductive vias of the network interconnection not shown. Said voltage is, like the voltage applied to the wall 18 of FIGS. 1A and 1B, preferably configured to allow the depletion of the box 14.

[0082] Alternatively, the element 36 may extend over the entire height of the substrate 12, i.e. from the face 12a to the face 12b.

[0083] The element 36 preferably extends in a central portion of the box 14. Thus, the element 36 is separated from the wall 34, preferably from all portions of the wall 34, by portions of the substrate 12, preferably by portions of the box 14. The element 36 and the element 20 are preferably separated from each other by portions of the substrate 12, preferably by portions of the box 14.

[0084] The pixel 32 comprises, for example, layers 38. The layers 38 are made of an insulating material. The layers 38 are located at the interface between the box 24' and the layer 26. In other words, the layers 38 are located at the PN junction. More precisely, the layers 38 are located between portions of the box 24' and the layer 26. The layers 38 are preferably located so as to be in contact, for example by the lower face, at the upper end of a wall 34. The layers 38 extend, for example, partially opposite the boxes 14, 16, 24'. At least a portion of the boxes 14, 16, 24', corresponding to an illumination window, is not located opposite the layers 38.In other words, a part of the box 24', more precisely of the upper face of the box 24', is for example covered by, preferably in contact with, the layers 38 and another part of the box 24', more precisely of the upper face of the box 24', preferably the rest of the upper face of the box 24', is not covered by the layers 38. Said uncovered part of the box 24' is for example located opposite the boxes 14 and 16. Said uncovered part of the box 24' is for example located opposite the element 20 and / or the element 36.

[0085] The operation of pixel 32 is for example identical to the operation of pixel 10. The operation of pixel 32 comprises for example an alternation of first and second steps as described in relation to figures 1A and 1B.

[0086] [Fig.3] shows a sectional view of another embodiment of an electronic device.

[0087] The device is for example, like the device 10 of figures 1A and 1B, an optoelectronic device. The device comprises at least one pixel 40, preferably a plurality of pixels 40, for example at least one hundred pixels, for example at least one thousand pixels. For example, the pixels 40 are arranged in a matrix. The device of [Fig.3] is for example configured to generate one or more electrical signals upon receiving light signals. For example, the device is a camera or a light sensor, for example a time-of-flight sensor.

[0088] The pixel 40 comprises elements of the pixel 32 which will not be described again in detail. In particular, the pixel 40 comprises: - the substrate 12, having faces 12a and 12b; - boxes 14, 16 and 24' in substrate 12; - element 20 located in substrate 12; - layers 26, 28, 30; - elements 20 and 36; and - layers 38.

[0089] Pixel 40 differs from pixel 32 in that pixel 40 comprises a wall 42. Wall 42 is preferably made of an insulating material. Alternatively, wall 42 may for example be made of a doped semiconductor material of the conductivity type opposite to the conductivity type of well 14, for example P-doped.

[0090] The wall 42 separates the box 14 into two parts 14a and 14b. The parts 14a and 14b are not in contact with each other. The wall 42 extends at least over the entire height of the box 14, preferably from the face 12a to the upper face of the box 14. Preferably, the wall 42 does not extend into the box 16. Preferably, the wall 42 does not extend over the entire height of the box 16. Preferably, the wall 42 does not extend into the box 24'. Preferably, the wall 42 does not extend over the entire height of the box 24'.

[0091] The portion 14b, corresponding to a reset zone, is preferably polarized to ground. For example, the portion 14b of the box 14 extends to the face 12a and comprises a contact pad at the face 12a. Said pad makes it possible, for example, to polarize the portion 14b to ground.

[0092] The elements 20 and 36 extend into the portion 14a. The elements 20 and 36 preferably extend into a central portion of the portion 14a of the box 14. Thus, the elements 20 and 36 are separated from the walls 34 and 42, preferably from all portions of the walls 34 and 42, by portions of the substrate 12, preferably by portions of the box 14. The elements 20 and 36 are preferably separated from each other by portions of the substrate 12.

[0093] The pixel 40 comprises an element 44. The element 44 comprises, like the element 20, a conductive core and an insulating sheath. The element 44 preferably extends at least over the height of the boxes 14 and 16. The element 44 extends for example from the face 12a to the upper face of the box 16. At the end of the element 44 flush with the face 12a, the conductive core of the element 44 is for example uncovered, that is to say is for example not covered by the insulating sheath of the element 44, so as to be electrically connected to a voltage source, for example by means of conductive tracks and conductive vias of the interconnection network not shown.

[0094] Like element 20, the conductive core of element 44 preferably comprises a lower portion and an upper portion. Said lower and upper portions are in contact with each other. Thus, the upper portion comprises a lower end in contact with the upper end of the lower portion. The upper portion preferably has horizontal dimensions greater than the horizontal dimensions of the lower portion. By horizontal is meant in a plane parallel to the section plane BB of Figures 1B and 2B.

[0095] The upper part of the element 44 is located at the level of the box 16. In other words, the upper part of the element 44 preferably has a height less than or equal to the height of the box 16. More precisely, the portion of the element 44 comprising the upper part of the element 44 is surrounded laterally by the box 16. Preferably, the portion of the element 20 comprising the upper part of the element 44 is not surrounded laterally by the box 14. The upper end of the upper part of the element 44 is preferably covered by the sheath of the element 44.

[0096] The lower part of the element 44 is located at the level of the box 14. The lower part of the element 44 preferably extends from the face 12a to the lower end of the upper part, for example located at the level of the interface between the box 14 and the box 16. More precisely, the portion of the element 44 comprising the lower part of the element 44 is surrounded laterally by the box 14, by the portion of the substrate 12 comprising the electronic components not shown, and possibly by a portion of the box 16.

[0097] The element 44 preferably extends in a central portion of the portion 14b of the box 14. Thus, the element 44 is separated from the walls 34 and 42, preferably from all portions of the walls 34 and 42, by portions of the substrate 12, preferably by portions of the box 14.

[0098] [Fig.4A] and [Fig.4B] illustrate the operation of the embodiment of [Fig.3]. More specifically, FIGS. 4A and 4B respectively represent first and second stages of operation of the pixel 40. Preferably, the operation of the pixel 40 comprises an alternation of first and second stages. The operation described in relation to FIGS. 4A and 4B is for example of the "Global Shutter" type.

[0099] During the first step, illustrated by [Fig.4A], charges, more precisely electrons (represented by the symbol and holes (represented by the symbol "+"), are optically generated in layer 26 upon reception of light rays by layer 26. In the case of an N-doped 24' box, the electrons photogenerated in layer 26 are extracted and directed into box 24'.

[0100] During the first step, a voltage, for example negative, is applied to the layer 30 so that the holes are attracted out of the box 24' and towards the layer 28. Furthermore, a voltage, for example negative, is applied to the conductive core of the element 36 so as to deplete the part 14a. A voltage, for example negative, is applied to the conductive core of the element 20 so as to turn on the transistor, composed of the wells 16, 24', the part 14a and the element 20. Thus, the charges, for example the electrons, located in the well 24' are attracted into the well 14a. During the first step, the element 44 is configured to turn off the transistor composed of the wells 16, 24', the part 14b and the element 44.

[0101] During the second step, a voltage, for example negative, is applied to the layer 30 so that the holes are attracted out of the well 24' and towards the layer 28. A voltage, for example negative, is applied to the conductive core of the element 44 so as to turn on the transistor, composed of the wells 16, 24', the part 14b and the element 44. Thus, the charges, for example the electrons, located in the well 24' are attracted into the well 14b. In addition, the part 14b is for example biased to ground, so as to remove the charges located in the part 14b. During the second step, the element 20 is configured to turn off the transistor composed of the wells 16, 24', the part 14a and the element 20. For example, the second step may comprise reading the charges contained in the part 14b of the well.In other words, the second step may comprise the passage of the charges located in the part 14a into a reading circuit connected to the part 14a, the circuit being for example located in the substrate 12 between the part 14a and the face 12a.

[0102] [Fig.5A] represents a sectional view of another embodiment of an electronic device. [Fig.5B] represents another sectional view of the embodiment of [Fig.5A]. [Fig.5C] represents a top view of the embodiment of [Fig.5A]. [Fig.5D] represents another sectional view of the embodiment of [Fig.5A]. More specifically, [Fig.5A] is a sectional view along plane AA of [Fig.5C]. [Fig.5B] is a sectional view along plane BB of [Fig.5C]. [Fig.5C] is a top view along plane CC of FIGS. 5A and 5B. [Fig.5B] is a sectional view along plane DD of [Fig.5C].

[0103] The device is for example, like the device of [Fig. 3], an optoelectronic device. The device comprises at least one pixel 46, preferably a plurality of pixels 46, for example at least one hundred pixels, for example at least a thousand pixels. For example, the pixels 46 are arranged in a matrix. The device of FIGS. 5A to 5D is for example configured to generate one or more electrical signals upon receiving light signals. For example, the device is a camera or a light sensor, for example a time-of-flight sensor.

[0104] The pixel 46 comprises elements of the pixel 40 which will not be described again in detail. In particular, the pixel 46 comprises: - the substrate 12, having faces 12a and 12b; - boxes 14, 16 and 24' in substrate 12; - element 20 located in substrate 12; - layers 26, 28, 30; - layers 38.

[0105] Pixel 46 differs from pixel 40 in that box 14 is divided into several parts, for example into five 14-1, 14-2, 14-3, 14-4, 14-5. One of the parts of box 14, part 14-5 in FIGS. 5A to 5D, corresponds to a reset zone, the other parts, parts 14-1 to 14-4 in FIGS. 5A to 5D, of box 14 corresponding to storage zones. Parts 14-1 to 14-4 are for example arranged in matrices, that is to say form rows and columns, for example two rows and two columns. Part 14-5 is for example located in the center of the matrix formed by parts 14-1 to 14-4.

[0106] The pixel 46 preferably does not include the wall 34 of Figures 2A to 4B. The pixel 46 includes a wall 48. The wall 48 extends at least over the entire height of the box 14. The wall 48 extends, for example, from the face 12a to the upper face of the box 14, preferably from the face 12a to the upper face of the box 16. The wall 48 is, like the wall 18 of Figures 1A to 1C, conductive and insulated. In other words, the wall 48 includes a conductive core, for example made of metal, and an insulating outer sheath surrounding the conductive core at least laterally. The wall 48 laterally surrounds the pixel 46 and further laterally surrounds the parts 14-1, 14-2, 14-3, 14-4, 14-5 of the box 14. Similarly, the portions of the box 16 located on the parts 14-1, 14-2, 14-3, 14-4, 14-5 of the box 14 are laterally surrounded by the wall 48.The side walls of the parts 14-1, 14-2, 14-3, 14-4, 14-5 of the box 14 and the associated portions of the box 16 are for example in contact with the side walls of the sheath of the wall 18.

[0107] The wall 48 thus separates the parts 14-1 to 14-5 from each other. Thus, each of the parts 14-1 to 14-4 is laterally surrounded by the wall 48. The conductive core of the wall 48 is configured to receive a voltage. The core of the wall 48 is for example connected to a node for applying said voltage by conductive tracks and conductive vias of the interconnection network not shown. Said voltage is preferably configured to allow the depletion of the well 14.

[0108] The pixel 46 comprises an element 44 extending into the portion 14-5 of the box 14. As described in relation to [Fig.3], the element 44 preferably extends at least over the height of the boxes 14 and 16. The element 44 extends for example from the face 12a to the upper face of the box 16.

[0109] The pixel 46 comprises as many elements 20 as there are storage parts of the box 14. Thus, in FIGS. 5A to 5C, the pixel 46 comprises four elements 20-1, 20-2, 20-3, 20-4. The elements 20-1 to 20-4 are for example identical to the element 20 described in relation to figures IA and IB. Elements 20-1, 20-2, 20-3, 20-4 extend respectively into parts 14-1, 14-2, 14-3, 14-4.

[0110] In a so-called "Global Shutter" operating mode, the operation of the pixel 46 comprises the first and second steps described in relation to FIGS. 4A and 4B, preferably an alternation of first and second steps.

[0111] In the first steps, a voltage, for example negative, is applied to the layer 30 so that the holes are attracted out of the well 24' and towards the layer 28. In addition, a voltage, for example negative, is applied to the conductive core of the wall 48 so as to deplete the parts 14-1 to 14-4. A voltage, for example negative, is applied to the conductive core of the elements 20-1 to 20-4 so as to turn on the transistors, composed of the wells 16, 24', the parts 14-1 to 14-4 and the elements 20-1 to 20-4. Thus, the charges, for example the electrons, located in the well 24' are attracted into the well 14 in one of the parts 14-1 to 14-4. During the first step, element 44 is configured to turn off the transistor composed of boxes 16, 24', part 14-5 and element 44.

[0112] During the second step, a voltage, for example negative, is applied to the layer 30 so that the holes are attracted out of the well 24' and towards the layer 28. A voltage, for example negative, is applied to the conductive core of the element 44 so as to turn on the transistor, composed of the wells 16, 24', the part 14-5 and the element 44. Thus, the charges, for example the electrons, located in the well 24' are attracted into the well 14b. In addition, the part 14-5 is for example polarized to ground, so as to remove the charges located in the part 14-5. During the second step, elements 20-1 to 20-4 are configured to turn off the transistors composed of boxes 16, 24', parts 14-1 to 14-4 and elements 20-1 to 20-4.

[0113] [Fig.6A] represents a sectional view of another embodiment of an electronic device. [Fig.6B] represents a top view of the embodiment of [Fig.6A]. More specifically, [Fig.6A] is a sectional view along plane AA of [Fig.6B]. [Fig.6B] is a sectional view along plane BB of [Fig.6A],

[0114] The device is for example, like the device of Figures 5A to 5D, an optoelectronic device. The device comprises at least one pixel 50, preferably a plurality of pixels 50, for example at least one hundred pixels, for example at least one thousand pixels. For example, the pixels 50 are arranged in a matrix. The device of Figures 6A and 6B is for example configured to generate one or more electrical signals upon receiving light signals. For example, the device is a camera or a light sensor, for example a time-of-flight sensor.

[0115] Pixel 50 comprises elements of pixel 46 or pixel 32 which will not be described again in detail. In particular, pixel 50 comprises: - wall 34, described in relation to figures 2A and 2B, surrounding pixel 50; - the substrate 12, having faces 12a and 12b; - boxes 16 and 24' in substrate 12; - parts 14-1, 14-2, 14-3, 14-4 of box 14; - the elements 20-1, 20-2, 20-3, 20-4 located in the substrate 12; and - the layers 26, 28, 30.

[0116] Pixel 50 differs from pixel 46 in that pixel 50 does not include portion 14-5 and does not include element 44. Further, pixel 50 does not include layers 38.

[0117] In pixel 50, each part 14-1 to 14-4, corresponding to a storage region, is surrounded by a wall 52. The walls 52 surrounding the different parts 14-1 to 14-4 have, for example, common parts and form, for example, a single wall 52 surrounding each of the parts 14-1 to 14-4.

[0118] The wall 52 is for example similar to the wall 18 of Figures 1A and 1B and to the wall 48 of Figures 5A to 5D. The wall 52 is conductive and insulated. In other words, the wall 52 comprises a conductive core, for example made of metal, and an insulating outer sheath surrounding at least laterally the conductive core. The wall 52 laterally surrounds the parts 14-1 to 14-4. The side walls of the parts 14-1 to 14-4 are for example in contact with the side walls of the sheath of the wall 52.

[0119] The wall 52 extends at least over the height of the parts 14-1 to 14-4. In other words, the wall 52 extends at least along the side walls of the parts 14-1 to 14-4. Preferably, the wall 52 extends from the face 12a to the upper face of the parts 14-1 to 14-4.

[0120] The conductive core of the wall 52 is configured to receive a voltage. The core of the wall 52 is for example connected to a node for applying said voltage by conductive tracks and conductive vias of the interconnection network not shown. Said voltage is preferably configured to allow the depletion of the parts 14-1 to 14-4.

[0121] The wall 52 is for example separated from the wall 34 by a portion 54 of the substrate 12, comprising for example a portion of the box 14.

[0122] During a so-called "Rolling Shutter" operating mode, the operation of the pixel comprises as many steps as there are storage regions 14-1 to 14-4. Thus, in the example of FIGS. 6A and 6B, the operation of the pixel 50 comprises first, second, third and fourth steps. More specifically, the operation of the pixel 50 comprises the repetition of the first, second, third and fourth steps, preferably in this order.

[0123] Each first, second, third and fourth step corresponds to the storage of charges in one of the storage regions. Thus, during each step the charges, for example electrons, are attracted into one of the storage regions, said region being different in each of the first, second, third and fourth steps. More precisely, the transistor allowing passage into said storage region is turned on and the other transistors allowing passage into the other storage regions are kept blocked. The other charges, for example holes, are attracted into layer 28.

[0124] In the first, second, third and fourth steps, a voltage, for example negative, is applied to the layer 30 so that the holes optically generated in the layer 26 are attracted out of the layer 26 and towards the layer 28. Furthermore, a voltage, for example negative, is applied to the conductive core of the wall 52 so as to deplete the parts 14-1 to 14-4.

[0125] Furthermore, during the first step, a voltage, for example positive, is applied to the conductive core of the element 20-1 so as to turn on the transistor, for example a vertical MOSFET transistor, composed of the part of the well 16 surrounding the element 20-1 format the gate, the part of the well 24' adjacent to said part of the well 16, and the part 14-1. Thus, the charges, for example the electrons, previously photogenerated in the layer 26 and extracted in the well 24' are attracted into the part 14-1. During the first step, the elements 20-2 to 20-4 are configured to turn off the transistors composed of the wells 16, 24', the parts 14-2 to 10-4 and the elements 20-2 to 20-4. During the first step, the charges contained in parts 14-2 to 14-4 are for example read by a reading circuit not shown, comprising for example electronic components located in and on the substrate 12.

[0126] Similarly, during the second step, a voltage, for example positive, is applied to the conductive core of the element 20-2 so as to turn on the transistor, composed of the wells 16, 24', the part 14-2 and the element 20-2. Thus, the charges, for example the electrons, located in the well 24' are attracted into the part 14-2. During the second step, the elements 20-1, 20-3 and 20-4 are configured to turn off the transistors composed of the wells 16, 24', the parts 14-1, 14-3 and 10-4 and the elements 20-1, 20-3 and 20-4. During the second step, the charges contained in parts 14-1, 14-3 and 14-4 are for example read by a reading circuit not shown, comprising for example electronic components located in and on the substrate 12.

[0127] Similarly, during the third step, a voltage, for example positive, is applied to the conductive core of the element 20-3 so as to turn on the transistor, composed of the wells 16, 24', the part 14-3 and the element 20-3. Thus, the charges, for example the electrons, located in the well 24' are attracted into the part 14-3. During the third step, the elements 20-1, 20-2 and 20-4 are configured to turn off the transistors composed of the boxes 16, 24', the parts 14-1, 14-2 and 10-4 and the elements 20-1, 20-2 and 20-4. During the third step, the charges contained in the parts 14-1, 14-2 and 14-4 are for example read by a reading circuit not shown, comprising for example electronic components located in and on the substrate 12.

[0128] Similarly, during the fourth step, a voltage, for example positive, is applied to the conductive core of the element 20-4 so as to turn on the transistor, composed of the wells 16, 24', the part 14-4 and the element 20-4. Thus, the charges, for example the electrons, located in the well 24' are attracted into the part 14-4. During the fourth step, the elements 20-1, 20-2 and 20-3 are configured to turn off the transistors composed of the wells 16, 24', the parts 14-1, 14-2 and 10-3 and the elements 20-1, 20-2 and 20-3. During the fourth step, the charges contained in parts 14-1, 14-2 and 14-3 are for example read by a reading circuit not shown, comprising for example electronic components located in and on the substrate 12.

[0129] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the doping types could be reversed. Layer 30 would then be configured to receive a voltage attracting electrons into layer 28 and elements 20 or 20-1 to 20-4 and 44 would then be configured to receive a voltage allowing the passage of holes into well 14.

[0130] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Optoelectronic device comprising at least one pixel (10, 32, 46, 50), the pixel comprising: - a first semiconductor region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5) of a first conductivity type; - a second semiconductor region (16) of a second conductivity type, different from the first conductivity type, lying on the first region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5); - a photodiode (22) resting on the second region (16), the photodiode (22) comprising a third semiconductor region (24, 24', 26) of the first conductivity type, the third region (24, 24', 26) being in contact with the second region (16) and being separated from the first region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5) by the second region (16);and - a first conductive and insulated element (20, 20-1, 20-2, 20-3, 20-4), extending in the second region (16), the first element (20, 20-1, 20-2, 20-3, 20-4) being configured to be polarized by a first voltage, during a first operating step, so as to allow the passage of charges from the third region (24, 24') to the first region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5).;

2. The device of claim 1, wherein the first element (20, 20-1, 20-2, 20-3, 20-4) is a via comprising a conductive core (20a, 20a 1, 20a2) and an insulating sheath (20b) extending through the first (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5) and second regions (16).

3. A device according to claim 2, wherein the conductive core (20a) of the first element comprises a first portion (20a2) surrounded by the first region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5) and a second portion (20al) surrounded by the second region (16), the second portion having horizontal dimensions greater than the horizontal dimensions of the first portion.

4. A device according to any one of claims 1 to 3, wherein the photodiode (22) comprises the third region (24, 24', 26) doped with the first conductivity type and a fourth region (28) doped with the second conductivity type, the third region comprising first (24, 24') and second (26) layers forming a heterojunction, the first layer (24, 24') being made of a material semiconductor and the second layer (26) comprising quantum dots, the fourth region being in contact with the second layer, the dopant concentration of the first layer being higher than that of the second layer.

5. A device according to any one of claims 1 to 4, wherein the pixel comprises a first insulated conductive wall (18) surrounding the first region (14), the first wall (18) being configured to be biased so as to deplete the first region.

6. A device according to any one of claims 1 to 4, wherein the pixel comprises a second insulating wall (34) surrounding the first region (14), and a second insulated conductive element (36) extending into the first region.

7. A device according to any one of claims 1 to 4, wherein the first region (14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5) is divided into first (14a, 14-1, 14-2, 14-3, 14-4) and second portions (14b, 14-5), the first element (20, 20-1, 20-2, 20-3, 20-4) being located in the second region (16), opposite the first portion (14a) of the first region, the first and second portions of the first region being separated by a third insulating wall (42), the pixel comprising a third element (44), the third element being conductive and insulated, the third element extending into the second region opposite the second portion of the first region, the third element being configured to be polarized by a second voltage, during a second stage of operation, so as to allow the passage of charges from the third region to the second part of the first region.

8. A device according to claim 8, wherein the pixel is configured so that, during the first stage of operation, the third element (44) is biased by a third voltage so as to block the passage of charges from the third region to the second part of the first region and wherein the pixel is configured so that, during the second stage of operation, the first element is biased by a fourth voltage so as to block the passage of charges from the third region to the first part of the first region.

9. Device according to any one of claims 1 to 4, wherein the first region is divided into at least two first parts (14-1, 14-2, 14-3, 14-4) and a second part (14-5), the pixel comprising as many first elements (20-1, 20-2, 20-3, 20-4) as first parts, each first element being located in the second region (16) opposite one of the first parts of the first region, the first and second parts of the first region being separated from each other by a third insulating wall (48), the pixel comprising a third element (44), the third element being conductive and insulated, the third element extending in the second region opposite the second part of the first region, the third element being configured to be polarized by a second voltage, during a second operating step, so as to allow the passage of charges from the third region to the second part of the first region.

10. Device according to claim 9, in which the pixel comprises as many second insulated conductive elements (20-1, 20-2, 20-3, 20-4) as first parts of the first region, each second element extending into one of the first parts (14-1, 14-2, 14-3, 14-4) of the first region.

11. A device according to claim 9 or 10, wherein, during the first stage of operation, the third element (44) is biased by a third voltage so as to block the passage of charges from the third region to the second part of the first region and wherein the pixel is configured so that, during the second stage of operation, the first elements are biased by a fourth voltage so as to block the passage of charges from the third region to the first parts of the first region.

12. Device according to any one of claims 1 to 4, in which the first region is divided into at least two first parts (14-1, 14-2, 14-3, 14-4), the pixel comprising as many first elements (20-1, 20-2, 20-3, 20-4) as first parts, each first element being located in the second region opposite one of the first parts of the first region.

13. Device according to claim 12, in which the pixel is configured to comprise a succession of steps, each step comprising the application of a voltage to the first element of one of the first parts so as to allow the passage of charges towards said first part and the application of a voltage to the other first elements so as to block the passage of charges to the other first parts.

14. A device according to claim 12 or 13, wherein each first portion is surrounded by a first insulated conductive wall, the first wall being configured to be biased so as to deplete said first region.

15. Method for controlling an optoelectronic device according to any one of claims 1 to 14, comprising a first operating step during which the conductive core of the first element is polarized by a first voltage so as to allow the passage of charges from the third region (24, 24') to the first region (14, 14a, 14b, 14-1, 14-2, 14-3, 14-4, 14-5).

Images