INTERRUPTION MANAGEMENT OF AN INTEGRATED CIRCUIT MEMORY CONTROLLER

Abstract

According to one aspect, an integrated circuit (IC) is proposed comprising a memory controller (MEM_CTRL) configured to transmit information stored in a memory (ECC_MEM) to a processing unit (PU). The memory controller (MEM_CTRL) comprises: - an error detection circuit (ECC_CTRL) configured to detect an error in said information by implementing an error correction code algorithm, and to generate an interrupt signal (INT) upon detection of at least one error in said information; - a transmission control circuit (INT_CTRL) configured to transmit the interrupt signal (INT) to the processing unit (PU) only when the error is detected for the first time in said information by the error detection circuit. Figure for the abstract: Fig 1

Description

Title of the invention: INTERRUPT MANAGEMENT OF AN INTEGRATED CIRCUIT MEMORY CONTROLLER

[0001] Some embodiments and implementations relate to an integrated circuit memory controller, and more particularly to the management of interrupts of the memory controller within an integrated circuit.

[0002] A memory controller allows a processor to access information, such as instructions or data, stored in memory. In particular, the memory controller can detect an error in the information by implementing an error-correcting code when transmitting that information to the processor.

[0003] When an error in information is detected by the memory controller, the latter can generate an interrupt to indicate to the processor that the transmitted information contains an error.

[0004] However, it may be possible to correct the error in the information read by the memory controller instead of correcting it directly in memory. Indeed, correcting the error in memory may require erasing and rewriting the information, which can be relatively lengthy operations, especially when the memory is non-volatile. Error correction performed by the memory controller is therefore generally faster and preferred, particularly in real-time applications.

[0005] Furthermore, when memory stores several instructions of an instruction sequence, the processor can provide a pre-loading mechanism allowing each of these instructions to be read from this memory in advance in parallel with the execution of other instructions of the instruction sequence in order to improve the performance of the processor.

[0006] More specifically, this preloading mechanism can trigger an interrupt when the instruction read in advance contains an error, thus temporarily stopping the execution of the instruction sequence.

[0007] As long as the instruction is not executed before the interruption of the instruction sequence, the processor will continue to read the same instruction after dealing with the interrupt.

[0008] The preloading mechanism therefore results in repeated triggering of the interrupt until the error contained in this instruction has been corrected in memory.

[0009] In other words, the repeated triggering of the interrupt prevents the processor from continuing to execute the sequence of instructions because the processor will always try to access the same location in the memory of the erroneous instruction after each interrupt.

[0010] In this regard, disabling interrupts could be considered to prevent repeated interrupt triggering for the same error in an instruction, but this solution does not allow the memory location of the erroneous instruction to be determined. Consequently, when this solution is used, erroneous instructions whose memory location cannot be found by the processing unit cannot be corrected.

[0011] Thus, there is a need to propose solutions enabling the detection and correction of an error in information while avoiding repeated access to the same location in memory by the processor during interrupts generated by the memory controller.

[0012] According to one aspect, an integrated circuit is proposed comprising a memory controller configured to transmit information, an instruction or data, for example, stored in memory to a processing unit, such as a processor, the memory controller comprising: - an error detection circuit configured to detect one or more errors in said information by implementing an error correction code algorithm, and to generate an interrupt signal if an error is detected in said information, - a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is first detected in said information by the error detection circuit.

[0013] By transmitting the interrupt signal to the processing unit only the first time the error is detected, we avoid the repeated triggering of the interrupt signal which leads the processing unit to enter an infinite loop in which this same interrupt signal is processed by the processing unit.

[0014] Thus, in the absence of repeated triggering of the interrupt signal, it is no longer necessary to disable interrupts to end this infinite loop and it becomes possible to correct errors in instructions stored in memory during maintenance.

[0015] According to one embodiment, the transmission control circuit includes a memory circuit configured to store the address of the memory location of the last information that triggered an interrupt signal transmission, and a logic circuit configured to compare the address stored by the memory circuit with the address of the memory location of the next information, for which an error is detected, is transmitted by the memory controller after said last information so as to transmit the interrupt signal to the processing unit only when the address of the location in the memory of said next information does not correspond to the address stored by the memory circuit.

[0016] The term "next information" means any instruction or data stored in memory that is transmitted to the processing unit after the last piece of information in the order of information transmission, which may, for example, be the same order as that of the sequence of instructions executed by the processing unit.

[0017] The next piece of information and the last piece of information can be the same information stored in a memory location, for example if the same instruction is transmitted twice consecutively to the processing unit, or two pieces of information stored in two different memory locations.

[0018] The memory circuit is configured to store one address at a time so that the logic circuit can compare the address of the memory location of the next piece of information with a single stored address which is that of said last piece of information.

[0019] The address of the location in memory of the last information that triggered a transmission of the interrupt signal is stored to prevent each new interrupt generated when an error is detected in this information from being transmitted to the processing unit.

[0020] The transmission control circuit advantageously includes a logic circuit enabling the interrupt to be transmitted if the address of said next information is different from the stored address or to block the interrupt if the address of said next information and the stored address match.

[0021] According to one embodiment, the memory circuit comprises: - a first register configured to store the memory address of said information in case an error is detected in said information by the error detection circuit, - a second register configured to store the address contained in the first register before an error is detected in the next piece of information.

[0022] Such a memory circuit can therefore be made simply from two registers for example.

[0023] The logic circuit includes a comparison circuit configured to generate a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and a conditional transmission circuit configured to transmit the interrupt signal only when the address stored in the The first register does not correspond to the address stored in the second register.

[0024] The conditional transmission circuit, for example an "AND" logic gate, makes it possible to filter, according to the result of comparison of the comparison circuit, the interrupts generated by the error detection circuit so as to transmit only the interrupt generated when the error is detected for the first time in said information.

[0025] According to one embodiment, the processing unit is configured to control the logic circuit so that the logic circuit compares the stored address with the address of the location in the memory of the next information as soon as the address of the last information is stored by the storage circuit.

[0026] This prevents the logic circuit from transmitting the interrupt signal again when the address of the last piece of information has not yet been stored by the memory circuit. For example, if the same stored address is compared more than once before being updated, it may trigger the transmission of several interrupt signals generated for the same error, for example, for an error in the same piece of information transmitted several times before the stored address is updated.

[0027] According to one embodiment, the memory controller includes an additional conditional transmission circuit configured to block the transmission of the interrupt signal by the transmission control circuit until the address of said last information is stored by the storage circuit.

[0028] The additional conditional transmission circuit can be considered in particular when the conditional transmission circuit can no longer ensure the blocking of certain interrupts.

[0029] According to one embodiment, the processing unit is configured, upon receiving the interrupt signal, to read the address contained in the second register and to store the read address in additional memory.

[0030] The additional memory therefore makes it possible to store a unique address for each piece of information for which an error was detected during the execution of the instruction sequence by the processing unit.

[0031] According to one embodiment, the integrated circuit further comprises a correction circuit, which may be, for example, the processing unit, configured to correct the information stored in the memory at the corresponding addresses stored in the additional memory.

[0032] These addresses, once stored in the additional memory, make it possible to retrieve all erroneous information directly from memory and to correct it during a maintenance operation, and thus avoid having to correct this information during each interrupt.

[0033] According to one embodiment, the processing unit is configured to erase the contents of the second register after the correction of said information stored in memory by the processing unit.

[0034] Thus, the contents of the second register can be erased after the maintenance operation, for example, during a restart of the integrated circuit. This prevents the address of information already corrected during the maintenance operation from remaining stored in the second register after the maintenance operation.

[0035] According to another aspect, a method is proposed for transmitting at least one piece of information stored in a memory to a processing unit, comprising: - the detection of an error in said information by implementing an error correction code algorithm and, in the event of detection of an error in said information, the generation of an interrupt signal, - transmission of the interrupt signal only when the error is detected for the first time in said information by the error detection circuit.

[0036] According to one embodiment, the method includes storing the address of the memory location of the last piece of information that triggered an interrupt signal transmission and comparing the stored address with the address of the memory location of each piece of information for which an error is detected, transmitted after said last piece of information so as to transmit the interrupt signal to the processing unit only when the address of the memory location of said information does not correspond to the address stored by the storage circuit.

[0037] According to one embodiment, the memorization comprises: - a storage in a first register of the address of the location in memory of said information in case of detection of an error in said information, - a storage in a second register of the address contained in the first register before an error is detected in the next information.

[0038] Said comparison includes generating a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and transmitting the interrupt signal only when the address stored in the first register does not correspond to the address stored in the second register.

[0039] According to one embodiment, said comparison of the stored address with the address of the location in memory of the next information is carried out as soon as the address of the last information is stored.

[0040] According to one embodiment, the method includes blocking the transmission of the interrupt signal until the address of said last information is memorized.

[0041] According to one embodiment, the method includes, upon receiving the interrupt signal by the processing unit, reading the address stored in the second register by the processing unit and storing the address read by the processing unit in an additional memory.

[0042] According to one embodiment, comprising erasing the contents of the second register after the correction of said information stored in memory by the processing unit.

[0043] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is by no means limiting, and the accompanying drawings in which:

[0044] [Fig.l] ;

[0045] [Fig.2] ; and

[0046] [Fig.3] schematically illustrate methods of implementation and realization of the invention.

[0047] Figure 1 schematically illustrates an integrated circuit IC according to an embodiment of the invention. The integrated circuit IC comprises an ECC_MEM memory, such as non-volatile memory, and an additional MEM memory, such as RAM (Random Access Memory).

[0048] The integrated circuit IC also includes a memory controller MEM_CTRL and a processing unit UT, such as a processor for example.

[0049] The ECC_MEM memory typically allows the storage of information, such as an instruction or data, as well as an error-correcting code (known by the acronym "ECC" for "Error-correcting code" in English).

[0050] The MEM_CTRL memory controller is configured to transmit the information stored in the ECC_MEM memory to the UT processing unit.

[0051] Information stored in ECC_MEM memory, for example the MEM_DAT instruction of a sequence of instructions executed by the processing unit UT or data, may contain errors.

[0052] In this regard, the MEM_CTRL memory controller includes an ECC_CTRL error detection circuit configured to detect one or more errors in said information by implementing an error correction code algorithm, and to generate an INT interrupt signal in case of detection of an error in said MEM_DAT information.

[0053] Such an ECC_CTRL error detection circuit is well known to those skilled in the art, who will be able to determine an error correction code algorithm for detecting the presence of an error in an instruction or data based on the error correction code contained in the MEM_ECC memory. These code algorithms Error correction algorithms can be based on Hamming code or Golay code, although these examples of algorithms are not exhaustive.

[0054] The ECC_CTRL error detection circuit allows, for example, the MEM_DAT instruction to be read from the ECC_MEM memory and this MEM_DAT instruction to be corrected before being transmitted to the processing unit UT.

[0055] The ECC_CTRL error detection circuit is configured to generate an INT interrupt signal when an error is detected in the information.

[0056] The interrupt signal INT can be generated in the form of a pulse corresponding to a "high" logic level for a given duration when an error is detected by the error detection circuit ECC_CTRL.

[0057] The interrupt signal INT temporarily interrupts the execution of the instruction sequence by the processing unit UT in order to allow the processing unit UT to react in case of detection of an error in the MEM_DAT information.

[0058] The MEM_CTRL memory controller also includes an INT_CTRL transmission control circuit. The INT_CTRL transmission control circuit is configured to transmit the INT interrupt signal only when the error is first detected in said information by the ECC_CTRL error detection circuit.

[0059] For example, when the error detection circuit ECC_CTRL first detects an error in the MEM_DAT information, the transmission control circuit INT_CTRL transmits the interrupt signal INT to the processing unit UT but prevents the transmission of interrupt signals that could be generated subsequently in the event of error detection in the same MEM_DAT information.

[0060] The INT_CTRL transmission control circuit thus prevents an interrupt from being transmitted to the processing unit UT when an error is detected again by the ECC_CTRL error detection circuit for the same information.

[0061] By transmitting the interrupt signal INT to the processing unit UT only the first time the error is detected, we avoid the repeated triggering of the interrupt signal which leads the processing unit UT to enter an infinite loop in which this same interrupt signal is processed by the processing unit.

[0062] Consequently, the processing unit UT, which has for example the preloading mechanism described above, can continue the execution of the instruction sequence without experiencing repeated triggering of an interrupt.

[0063] [Fig.2] schematically illustrates an example of an INT_CTRL transmission control circuit of the MEM_CTRL memory controller as described previously in relation to [Fig.1].

[0064] The INT_CTRL transmission control circuit includes a memo- MEM_REG is a logic circuit and a LOG_TX logic circuit.

[0065] The MEM_REG memory circuit is configured to store the address of the location in ECC_MEM memory of the last information that triggered a transmission of the INT interrupt signal.

[0066] The MEM_REG memory circuit includes hardware elements for reading the ADD address of the information for which an error has been detected, for example via the ECC_CTRL error detection circuit, and storing this ADD address.

[0067] The LOG_TX logic circuit is configured to compare the address stored by the MEM_REG memory circuit with the address of the location in the ECC_MEM memory of the next piece of information, for which an error is detected, transmitted after said last piece of information.

[0068] During the comparison by the logic circuit LOG_TX, if the address of the location in the ECC_MEM memory of said next information does not correspond to the address stored by the memory circuit MEM_REG, then the interrupt signal INT is transmitted to the processing unit UT.

[0069] In other words, the LOG_TX logic circuit uses the address stored by the storage circuit as a basis for comparison with each address transmitted by the ECC_CTRL error detection circuit in case of error detection in the information, so as to prevent the INT interrupt signal from being transmitted again for an error detected in the same information.

[0070] The INT_CTRL transmission control circuit further includes an ENB_CTRL control register. The UT processing unit is configured to control the LOG_TX logic circuit according to the value stored in the ENB_CTRL control register.

[0071] More specifically, the processing unit UT is configured to modify the value of the control register ENB_CTRL when the address of the last piece of information that triggered the interrupt signal INT is stored by the memory circuit MEM_REG. The processing unit UT generates an ENB enable signal from the value stored in the control register ENB_CTRL, so as to allow the logic circuit LOG_TX to perform the comparison as soon as the address of the last piece of information is stored by the memory circuit MEM_REG.

[0072] The MEM_REG memory circuit includes a first register ERR_ADD_REG and a second register ADD_TAG_REG.

[0073] The first register ERR_ADD_REG is configured to store the ADD address of the location in ECC_MEM of said information in case an error is detected in said information by the ECC_CTRL error detection circuit. Each new address transmitted by the ECC_CTRL error detection circuit can be automatically stored in the first ERR_ADD_REG register in case of error detection in the information, for example by replacing the address contained in the first ERR_ADD_REG register with the new address.

[0074] The second register ADD_TAG_REG is configured to store the address contained in the first register ERR_ADD_REG before an error is detected in the next information.

[0075] For example, the storage of the address in the second register ADD_TAG_REG can be carried out by the processing unit UT in response to the interrupt signal INT.

[0076] During the initialization of the integrated circuit IC, the second register ADD_TAG_REG stores an initialization value which may be different from the values ​​of the addresses of the memory ECC_MEM.

[0077] The LOG_TX logic circuit includes a COMP comparison circuit configured to generate a COMP_CTRL control signal having a value corresponding to the result of the comparison between the address contained in the first ERR_ADD_REG register and the address contained in the second ADD_TAG_REG register.

[0078] The COMP comparison circuit can be a conventionally designed digital comparator allowing a bit-by-bit comparison to be made between the address stored in the first register ERR_ADD_REG and the address stored in the second register ADD_TAG_REG.

[0079] The COMP_CTRL control signal generated by such a COMP comparator can be a signal whose voltage value corresponds to a different logic level depending on the result of the comparison. For example, the COMP_CTRL control signal can have a "high" logic level if the addresses stored in the first register ERR_ADD_REG and the second register ADD_TAG_REG are identical, and a "low" logic level if these addresses are different.

[0080] The LOG_TX logic circuit also includes a conditional transmission circuit AND2 configured to transmit the interrupt signal INT only when the address stored in the first register ERR_ADD_REG does not match the address stored in the second register ADD_TAG_REG.

[0081] The conditional transmission circuit can be a logic gate configured to perform the logical "AND" operation between the interrupt signal INT and the control signal COMP_CTRL. In particular, an inverter can be connected to an input of the logic gate AND2 so as to transmit the inverse logic level of the control signal COMP_CTRL to the logic gate AND2.

[0082] The interrupt signal INT is then retransmitted at the output of the AND2 logic gate according to the logic level of the COMP_CTRL control signal. More specifically, if the inverse logic level of the COMP_CTRL control signal at the input of the AND2 logic gate is "high", for example when the ADD address of If the MEM_DAT information is different from the stored address, then the interrupt signal INT is transmitted to the processing unit UT. Otherwise, that is, if the inverted logic level of the COMP_CTRL control signal at the input of the AND2 logic gate is "low", then the interrupt signal INT is not transmitted to the processing unit UT.

[0083] The MEM_CTRL memory controller includes an additional conditional transmission circuit AND1 configured to block the transmission of the interrupt signal INT by the INT_CTRL transmission control circuit until the address of the last information is stored by the MEM_REG storage circuit.

[0084] The additional conditional transmission circuit AND1 can be a logic gate configured to perform the logical "AND" operation between the interrupt signal INT and the enable signal ENB.

[0085] Upon receiving the interrupt signal INT, the processing unit UT can read the address stored in the second register ADD_TAG_REG and store this address in an additional memory MEM.

[0086] The additional memory MEM allows the address of each piece of information for which an error was detected during the execution of the instruction sequence by the processing unit UT to be stored. These addresses, once stored in the additional memory, can be used to perform a maintenance operation during which each erroneous piece of information stored in the ECC_MEM memory is corrected.

[0087] In this regard, the integrated circuit further includes a correction circuit, which may be, for example, the processing unit UT, configured to correct the information stored in memory at the corresponding addresses stored in the additional memory.

[0088] During the maintenance operation, the processing unit UT can retrieve all erroneous information stored in ECC_MEM memory from addresses stored in additional memory MEM and correct this information. Such a maintenance operation can, in particular, take place after the completion of the instruction sequence by the processing unit UT, so as to avoid correcting this information during each interrupt, for example.

[0089] The integrated circuit (IC) can then restart after the maintenance operation. However, the address of the last piece of information that triggered the interrupt signal INT is still stored in the second register ADD_TAG_REG after the IC restarts, even though this information was corrected during the maintenance operation. The interrupt signal INT that would be generated by the error detection circuit ECC_CTRL upon detection of a new error in this information may not be transmitted to the processing unit UT if the address of this information is still stored in the second register ADD_TAG_REG.

[0090] To avoid this risk, the processing unit UT is configured to clear the contents of the second register ADD_TAG_REG after the correction of said information stored in ECC_MEM memory by the processing unit UT.

[0091] In particular, the INT_CTRL transmission control circuit includes a CLR_REG erase register configured to store a user-defined value.

[0092] For example, an initialization value can be stored in the CLR_REG erase register when the integrated circuit IC is first used so that, at each restart of the integrated circuit IC, the processing unit UT reads the initialization value stored in the CLR_REG erase register and replaces the value stored in the second ADD_TAG_REG register with this initialization value.

[0093] Fig. 3 schematically illustrates a method of transmitting at least one piece of information stored in the ECC_MEM memory to the processing unit UT.

[0094] The method includes a step 100 of detecting an error in said information by implementing an error correction code algorithm and, in the event of detection of an error, or several errors, in said information, a generation of an interrupt signal INT.

[0095] The method includes a step 101 of transmitting the interrupt signal INT, for example by the transmission control circuit INT_CTRL as described previously in relation to Figures 1 and 2, only when the error is detected for the first time in said information by the error detection circuit.

[0096] The method also includes a step 102 of memorizing the address of the location in the ECC_MEM memory of the last information that triggered a transmission of the interrupt signal INT.

[0097] Step 102 includes storing in a first register ERR_ADD_REG the address of the location in ECC_MEM of said information in case of detection of an error in said information.

[0098] Step 102 also includes storing the address contained in the first register, ERR_ADD_REG, in a second register, ADD_TAG_REG, before an error is detected in the next information. An initialization value, which may be different from the ECC_MEM memory address values, may be stored in the second register, ADD_TAG_REG, by default if none of the ECC_MEM memory addresses have been stored, for example, during IC initialization.

[0099] The method includes a step 103 of comparison, for example by a LOG_TX logic circuit, of the stored address with the address of the location in the The ECC_MEM memory location of the next piece of information, for which an error is detected, is transmitted after the last piece of information. If, after this comparison, the address of the location in ECC_MEM of the next piece of information does not correspond to the address stored by the MEM_REG memory circuit, then the interrupt signal INT is transmitted to the processing unit UT.

[0100] Step 103 includes detecting the storage of the address of the last information that triggered a transmission of the interrupt signal INT and generating an activation signal ENB from the value stored in the control register ENB_CTRL so as to allow the logic circuit LOG_TX to perform the comparison as soon as the address of the last information is stored by the storage circuit MEM_REG.

[0101] Step 103 includes the generation of a COMP_CTRL control signal. The COMP_CTRL control signal has a value corresponding to the result of the comparison between the address contained in the first register ERR_ADD_REG and the address contained in the second register ADD_TAG_REG.

[0102] Step 103 also includes transmission of the interrupt signal INT only when the address stored in the first register ERR_ADD_REG does not match the address stored in the second register ADD_TAG_REG.

[0103] The method includes a step 104 of blocking the transmission of the interrupt signal INT by the transmission control circuit INT_CTRL until the address of said last information is stored.

[0104] The method includes a step 105 of receiving the interrupt signal INT by the processing unit UT.

[0105] Step 105 includes reading the address stored in the second register ADD_TAG_REG by the processing unit UT and storing the address read by the processing unit UT in an additional memory MEM.

[0106] The method further includes a step 106 of correcting the information stored in ECC_MEM memory to the corresponding addresses stored in the additional memory. The correction in step 107 can, for example, be performed by the processing unit UT.

[0107] The method includes a step 107 of erasing the contents of the second register ADD_TAG_REG after the correction of said information stored in ECC_MEM memory by the processing unit UT. Such erasure may include, for example, reading an initialization value stored in the erase register CLR_REG and replacing the address stored in the second register ADD_TAG_REG with this initialization value.

Claims

1.

2.

3. Demands Integrated circuit (IC) comprising a memory controller (MEM_CTRL) configured to transmit information stored in a memory (ECC_MEM) to a processing unit (PU), the memory controller (MEM_CTRL) comprising: - an error detection circuit (ECC_CTRL) configured to detect an error in said information by implementing an error correction code algorithm, and to generate an interrupt signal (INT) in case of detection of an error in said information, - a transmission control circuit (INT_CTRL) configured to transmit the interrupt signal (INT) to the processing unit (TU) only when the error is detected for the first time in said information by the error detection circuit. An integrated circuit according to claim 1, wherein the transmission control circuit (INT_CTRL) includes a memory circuit (MEM_REG) configured to store the address of the memory location (ECC_MEM) of the last piece of information that triggered an interrupt signal transmission (INT), and a logic circuit (LOG_TX) configured to compare the address stored by the memory circuit with the address of the memory location (ECC_MEM) of the next piece of information, for which an error is detected, transmitted after said last piece of information so as to transmit the interrupt signal (INT) to the processing unit (PU) only when the address of the memory location (ECC_MEM) of said next piece of information does not correspond to the address stored by the memory circuit. Integrated circuit according to claim 2, wherein the memory circuit (MEM_REG) comprises: - a first register (ERR_ADD_REG) configured to store the address of the memory location (ECC_MEM) of said information in case an error is detected in said information by the error detection circuit (ECC_CTRL), - a second register (ADD_TAG_REG) configured to store the address contained in the first register (ERR_ADD_REG) before an error is detected in the next information, the logic circuit (LOG_TX) including a comparison circuit (COMP) configured to generate a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and a conditional transmission circuit (AND2) configured to transmit the interrupt signal (INT) only when the address stored in the first register does not match the address stored in the second register.

4. Integrated circuit according to any one of claims 2 or 3, wherein the processing unit is configured to control the logic circuit (LOG_TX) so that the logic circuit compares the stored address with the address of the location in the memory of the next information as soon as the address of the last information is stored by the memory circuit (MEM_REG).

5. Integrated circuit according to any one of claims 2 to 4, wherein the memory controller (MEM_CTRL) includes an additional conditional transmission circuit (AND1) configured to block the transmission of the interrupt signal (INT) by the transmission control circuit (INT_CTRL) until the address of said latter information is stored by the storage circuit (MEM_REG).

6. Integrated circuit according to any one of claims 3 to 5, wherein the processing unit (PU) is configured, upon receiving the interrupt signal, to read the address stored in the second register (ADD_TAG_REG) and to store in an additional memory (MEM) the address read by the processing unit (PU).

7. Integrated circuit according to claim 6, comprising a correction circuit configured to correct the information stored in memory (ECC_MEM) at the corresponding addresses stored in additional memory (MEM).

8. Integrated circuit according to claim 7, wherein the processing unit (PU) is configured to clear the contents of the second register (ADD_TAG_REG) after correcting said information stored in memory (ECC_MEM).

9. Method of transmitting at least one piece of information stored in a memory (ECC_MEM) to a processing unit (PU), comprising: - detecting an error in said information by implementing an error correction code algorithm and, in the event of detection of an error in said information, generating an interrupt signal (INT), - transmission of the interrupt signal to the processing unit (PU) only when the error is detected for the first time in said information by the error detection circuit.

10. A method according to claim 9, comprising storing the address of the memory location (ECC_MEM) of the last piece of information that triggered an interrupt signal (INT) transmission and comparing the stored address with the address of the memory location (ECC_MEM) of the next piece of information, for which an error is detected, transmitted after said last piece of information so as to transmit the interrupt signal (INT) to the processing unit (PU) only when the address of the memory location (ECC_MEM) of said next piece of information does not correspond to the stored address.

11. A method according to claim 10, wherein the memorization comprises: - storing in a first register (ERR_ADD_REG) the address of the memory location (ECC_MEM) of said information in case of detection of an error in said information, - storing in a second register (ADD_TAG_REG) the address contained in the first register (ERR_ADD_REG) before an error is detected in the next information, said comparison comprising generating a control signal having a value corresponding to the result of the comparison between the address contained in the first register and the address contained in the second register, and transmitting the interrupt signal (INT) only when the address stored in the first register does not correspond to the address stored in the second register.

12. A method according to any one of claims 10 or 11, wherein said comparison of the stored address with the address of the memory location (ECC_MEM) of the next information is carried out as soon as the address of the last information is stored.

13. A method according to any one of claims 10 to 12, comprising blocking the transmission of the interrupt signal (INT) until the address of said last information is stored.

14. A method according to any one of claims 10 to 13, comprising, upon receipt of the interrupt signal (INT) by the processing unit (PU), reading the address stored in the second register (ADD_TAG_REG) by the processing unit (PU) and storing it in an additional memory (MEM) of the address read by the processing unit (PU).

15. Method according to claim 14, comprising a correction of the information stored in memory (ECC_MEM) at the corresponding addresses stored in additional memory (MEM).

16. Method according to claim 15, comprising erasing the contents of the second register (ADD_TAG_REG) after correcting said information stored in memory (ECC_MEM) by the processing unit (PU).

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