Electronic frequency mixer

Abstract

Electronic frequency mixer The present description relates to an electronic frequency mixer (400) comprising at least one transistor (410, 412, 414, 416), comprising a front gate, a back gate, a source and a drain, wherein: the source is connected to a node for applying a radio frequency input signal (RF+, RF-); the front gate is connected to a node for applying a first periodic signal (LO+, LO-) at a first frequency; and the back gate is connected to a node for applying the first periodic signal (LO+, LO-) or a second periodic signal at the first frequency. Figure for abstract: Fig. 4

Description

Title of the invention: Electronic frequency mixer Technical field

[0001] The present description relates generally to electronic frequency mixers and in particular to mixers comprising transistors. Prior art

[0002] In electronics, a frequency mixer is a device that takes several input signals and generates one or more output signals whose frequencies are functions of the frequencies of the input signals. For example, an output signal is kept having a frequency of interest. This frequency of interest may correspond to the sum or the difference of the input frequencies. In particular, a frequency mixer may be designed using one or more transistors.

[0003] There is a need to improve the gain and / or linearity and / or noise of known frequency mixers. Summary of the invention

[0004] One embodiment overcomes all or part of the drawbacks of known frequency mixers.

[0005] According to one aspect of the present application, a second use is provided of an oscillating signal on the rear gate of MOS (Metal Oxide Semiconductor) transistors of the FDSOI (fully depleted Silicon on insulator) type in the case of frequency mixers.

[0006] One embodiment provides an electronic frequency mixer comprising: - at least one transistor, comprising a front gate, a back gate, a source and a drain, in which: - the source is connected to a node for applying a radio frequency input signal; - the front grid is connected to a node for applying a first periodic signal at a first frequency; and - the rear grid is connected to a node for applying the first periodic signal or a second periodic signal at the first frequency.

[0007] According to one embodiment, the at least one transistor is of the silicon-on-insulator type.

[0008] According to one embodiment, either the front and rear grids receive the first periodic signal, either the front grid receives the first periodic signal, and the rear grid receives the second periodic signal, the first and second periodic signals being in phase.

[0009] According to one embodiment, the front grid receives the first periodic signal, and the rear grid receives the second periodic signal, the first and second periodic signals being in phase opposition.

[0010] According to one embodiment, the at least one transistor comprises at least four transistors.

[0011] According to one embodiment, the four transistors are organized into two pairs in which: - the sources of the first pair of transistors are connected to a node for applying a first radio frequency input signal; - the sources of the second pair of transistors are connected to a node for applying a second radio frequency input signal, the first and second radio frequency input signals being differential signals; - the front and rear gates of a first transistor of each pair of transistors are connected to a node for applying a first periodic signal; and - the front and rear gates of a second transistor of each pair of transistors are connected to a node for applying a second periodic signal, the first and second periodic signals being differential signals.

[0012] According to one embodiment, the mixer is a passive mixer.

[0013] According to one embodiment, the mixer is an active mixer.

[0014] According to one embodiment, the input signal is generated by a stage amplification.

[0015] According to one embodiment, the duty cycle of the first periodic signal is identical to the duty cycle of the second periodic signal to within 5%.

[0016] According to one embodiment, the drain of the at least one transistor is connected to the output of the mixer.

[0017] Another embodiment provides an electronic circuit comprising: - an antenna; and - at least one mixer as described above.

[0018] According to one embodiment, the electronic circuit further comprises: - a circuit for receiving a radio frequency signal comprising: (a) a low-noise amplifier having an input connected to the antenna; and b) the at least one mixer comprising a first and a second mixer, the radio frequency input signal of each of the first and second mixers being a signal from the low noise amplifier, and the first and / or second periodic signal of the first mixer being 90° out of phase with respect to the first and / or second periodic signal of the second mixer.

[0019] According to one embodiment, the electronic circuit further comprises: - a circuit for transmitting a radio frequency signal comprising: (a) a power amplifier having an output connected to the antenna; b) the at least one mixer comprising a third and a fourth mixer, an output of each of the third and fourth mixers being connected to the power amplifier, the first and / or second periodic signal of the third mixer being phase shifted by 90° relative to the first and / or second periodic signal of the fourth mixer. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] schematically represents a cross-section of a fully stripped silicon-on-insulator (FDSOI) n-channel MOS transistor;

[0022] [Fig.2] represents a frequency mixer comprising a single transistor according to an embodiment of the present description;

[0023] [Fig.3] represents a graph illustrating the variation of the threshold voltage of the transistor of [Fig.2] as a function of the voltage applied to the rear gate of this transistor;

[0024] [Fig.4] represents a passive frequency mixer according to an embodiment of the present description;

[0025] [Fig.5] represents an active frequency mixer according to an embodiment of the present description;

[0026] [Fig.6] represents an electronic circuit comprising at least one frequency mixer according to an embodiment of the present description;

[0027] [Fig.7] represents the noise figure of the frequency mixer of [Fig.4] as a function of the power of the input signal;

[0028] [Fig.8] represents the gain of the frequency mixer of [Fig.4] as a function of the power of the input signal;

[0029] [Fig.9] represents the compression points at - IdB at the input and output of the frequency mixer of [Fig.4] as a function of the back gate voltage applied to the transistors of the circuit;

[0030] [Fig. 10] shows the input compression points at - IdB and the corresponding first-order output power of the active frequency mixer of [Fig.5] as a function of the phase difference between the signals applied to the front and rear gates of the transistors in the circuit; and

[0031] [Fig.l 1] represents the gain of the frequency mixer of [Fig.5] as a function of the power of the input signal and of the signals applied to the front and rear gates of the transistors of the mixer. Description of the embodiments

[0032] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the methods for manufacturing silicon-on-insulator type transistors are well known to those skilled in the art; they are not detailed in the present description.

[0034] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0037] [Fig.l] schematically represents a cross-section of a 100 MOS n-channel transistor of the silicon on insulator (SOI) type, for example a fully stripped silicon on insulator (FDSOI) type transistor.

[0038] The n-channel transistor 100 is formed on an n-type doped region 125. The transistor 100 has four connection nodes: a source S, a front gate G, a drain D and a back gate 130, configured to receive a bias voltage VBBN. The drain D of the n-channel transistor 100 corresponds to an n-type doped region 135, and similarly, the source S of the n-channel transistor 100 corresponds to an n-type doped region 140. A channel layer 145 separates the doped regions 135 and 140. The channel layer 145 is for example a thin layer of a semiconductor material.

[0039] An insulating layer of oxide (BOX, from the English buried oxide or “burried oxide”), for example silicon oxide, is formed between the zone 125 on the one hand and the channel layer 145, and for example the source and the drain 135 and 140, on the other hand. The thickness of the channel connecting the source and the drain is thus constrained by the BOX layer.

[0040] The front gate G is connected to a gate stack comprising a gate conductor 160 and an oxide insulating layer 165.

[0041] The transistor 100 is delimited by two shallow trench isolations 175 (in English “Shallow Trench Isolation”) and the rear gate 130 is surrounded by an additional shallow trench isolation 175.

[0042] Although an SOI type n-channel transistor is illustrated in [Fig.l], the counterpart exists for an SOI type p-channel MOS transistor.

[0043] Compared to a MOS transistor without an oxide insulating layer, the SOI configuration described above makes it possible to bias the doped zone 125 of a transistor 100 with a significant voltage range, for example a larger range than that used for the substrate of a transistor without an oxide insulating layer. The contact of the rear gate 130 is likened to a second gate which will influence the conduction of the channel 145, with a gain lower than the gain of the front gate G.

[0044] [Fig.2] represents a frequency mixer 200 comprising a single transistor 210 according to an embodiment of the present description.

[0045] The mixer 200 comprises for example a silicon-on-insulator (SOI) n-channel transistor 210, which is for example produced in the same way as the transistor 100 of [Fig. 1]. The mixer takes as input a radio frequency signal RF applied to its source (S), a first periodic signal LO applied to its front gate (G) and a second periodic signal LO' applied to its rear gate (BB), corresponding to the contact of the substrate 130 of the transistor 100 of [Fig. 1]. The first and second periodic signals LO, LO' may in certain cases be the same signal duplicated on the two gates. In other embodiments, the first and second periodic signals are two distinct signals and have for example the same frequency to within 5% and are for example derived from the same generator. The first and second periodic signals may also be derived from two distinct generators. A phase shift between the first and second periodic signals is possible.

[0046] The RF signal corresponds for example to an input signal of the mixer, configured to be modulated by the mixer 200, and the LO signal corresponds for example to a periodic signal configured to modulate the RF signal.

[0047] The signal provided by the mixer is the IF signal present at the drain (D) of the transistor 210. The frequency of the IF signal corresponds to the difference of the input frequencies applied to the RF source and to the front gate LO of the transistor.

[0048] The conversion of the input frequencies into an output frequency can be characterized by several parameters of the mixer 200 including gain, noise and linearity.

[0049] Gain is the ratio of the amplitudes of the RF and IF signals (in power, voltage or current) and quantifies the loss or amplification of power that a signal undergoes when passing through a mixer. The noise factor NF quantifies the addition of noise in the signal due to a mixer. These two parameters are directly dependent on the threshold voltage of the transistors present in the mixer, as detailed below for the circuit of [Fig.4].

[0050] A mixer similar to that of [Fig.2] could be realized with a p-channel transistor instead of the n-channel transistor.

[0051] [Fig. 3] represents a graph illustrating the variation of the threshold voltage of an n-channel SOI transistor such as transistor 100 of [Fig. 1] and of a corresponding p-channel SOI transistor, as a function of the voltage applied to the back gate of these transistors. The graph of [Fig. 3] represents in particular the threshold voltage (VTH) of the p-channel (VTH_P) and n-channel (VTH_N) SOI transistor as a function of the voltage applied to the back gate of the transistor (VBBP, VBBN).

[0052] The BOX insulating layer present in an SOI transistor makes it possible to apply a relatively high back gate voltage VBBN, VBBP and to modify the threshold voltage of the transistor.

[0053] For the n-channel transistor, the threshold voltage VTH_N is continuously reduced for a voltage on the positive rear gate (FBB, from the English forward body biasing) and continuously increased for a voltage on the negative rear gate (RBB, from the English reverse body biasing).

[0054] In blocked mode, that is to say when the voltage between the front gate and the source is lower than the threshold voltage, increasing the threshold voltage makes it possible to reduce the residual current flowing between the source and the drain.

[0055] On the contrary, in passing mode, that is to say when the voltage between the front gate and the source is higher than the threshold voltage, reducing the threshold voltage allows a greater electric current to flow between the source and the drain of the transistor. Thus, using the back gate voltage of SOI transistors in a mixer allows an increase in the gain of the mixer.

[0056] For the p-channel transistor, the threshold voltage VTH_P also varies with the voltage applied to the back gate VBBP but positively. The threshold voltage increases with a voltage on the positive back gate (RBB) and decreases with a voltage on the negative back gate (FBB).

[0057] [Fig.4] represents a passive frequency mixer 400 according to an embodiment of the present description.

[0058] In the embodiment illustrated in [Fig.4], the input and output signals are differential mode signals, the RF input signal being composed of the RF+ and RF- differential signals, the LO periodic signal being composed of the LO+ and LO- differential signals and the IF output signal being composed of the IF+ and IF- differential signals.

[0059] The operating principle of this mixer 400 is similar to the mixer 200 described in relation to [Fig.2] but this one comprises four transistors 410, 412, 414, 416 to account for differential signals. In this embodiment, the four transistors are SOI-type n-channel MOS transistors. In another embodiment, a similar mixer could be realized with SOI-type p-channel MOS transistors.

[0060] The RF+ input signal is applied to a node connected, preferably connected, to the sources S of the transistors 410 and 412.

[0061] The RF- input signal is applied to a node connected, preferably connected, to the sources S of the transistors 414 and 416.

[0062] The periodic signal LO+ is connected, preferably connected, to the front and rear gates of the transistors 410 and 416.

[0063] The periodic signal LO- is connected, preferably connected, to the front and rear gates of the transistors 412 and 414.

[0064] The drains of transistors 410 and 414 are connected, preferably connected, to a first output terminal 420 of the mixer providing the output signal IF+.

[0065] The drains of transistors 412 and 416 are connected, preferably connected, to a second output terminal 430 of the mixer providing the output signal IF-.

[0066] Electronic components configured to process the IF+, IF- output signals may be connected between the output terminals 420 and 430 of the mixer 400 and are represented by an impedance ZLOAD.

[0067] For the mixer 400 of [Fig.4], to the first order, the gain G is dependent on the equivalent resistance of a transistor in on-mode (R0N) and the equivalent impedance of a transistor in off-mode (ZOFF) specific to the transistor.

[0068] The noise factor NF is dependent on R0N and the gain.

[0069] The equivalent resistance of a transistor in on-mode, R0N, is inversely proportional to the difference between VGS and VTH.

[0070] Thus, by using SOI type transistors 210, 215 in a frequency mixer 400, the voltage applied to the rear gates VBBN, VBBP varies the threshold voltage VTH of the transistors and influences the quality parameters of the frequency mixer.

[0071] [Fig.5] represents an active frequency mixer 500 according to an embodiment of the present description.

[0072] Certain elements of [Fig.5] are similar to those of [Fig.4] and have been referenced with the same reference numbers and will not be described again in detail.

[0073] The frequency mixer 500 comprises four MOS transistors of SOI types 410, 412, 414, 416 connected in a similar manner to the frequency mixer 400.

[0074] Transistors 410 and 416 receive at their front gate a first periodic signal LO+, and transistors 410 and 416 receive at their rear gate a second periodic signal LO+ periodic signal, which may or may not be out of phase with the first LO+ periodic signal.

[0075] Transistors 412 and 414 receive at their front gate a first periodic signal LO-, and transistors 412 and 414 receive at their rear gate a second periodic signal LO-, which may or may not be out of phase with the first periodic signal LO-.

[0076] The differential radio frequency signal RF+ and RF- is, in the frequency mixer 500, amplified for example by an amplification circuit. In the example of [Fig.5], the amplification circuit comprises two MOS transistors 550 and 555 and load or adaptation or degeneration elements.

[0077] For example, the drain of transistor 550 is connected to a node 562 which is connected to the sources of transistors 410 and 412. The RF+ signal is applied to the front gate of transistor 550 and its source is for example connected to a node 566 via a first of the two impedances Zs. Similarly, the drain of transistor 555 is connected to a node 564 which is connected to the sources of transistors 414 and 416. The RF- signal is applied to the front gate of transistor 555 and its source is for example connected to node 566 via a second of the two impedances Zs. Node 566 may for example also be connected to a ground rail or to the drain of a transistor. The source of said transistor is for example connected to the ground of circuit 500 and its front gate is for example biased by a fixed voltage to modulate the gain applied to the RF+ and RF- signals.

[0078] As for the mixer 400, the drains of the transistors 410 and 414 are connected, preferably connected, to the output terminal 430 providing the output signal IF- and the drains of the transistors 412 and 416 are connected, preferably connected, to the output terminal 420 providing the output signal IF+.

[0079] Electronic components configured to process the IF+, IF- output signals can be connected between the output terminals 420 and 430 of the mixer 500 and are represented by two ZLOAD impedances 570, connected between the output terminals 420, 430 and a supply voltage rail VDD.

[0080] Although in the examples of Figures 4 and 5, the same LO+ signal is applied to the front and rear gates of the transistors 410, 416, in other embodiments, it would be possible to apply two separate signals to the front and rear gates, these signals having for example the same frequency to within 5%. Similarly, although in the examples of Figures 4 and 5, the same LO- signal is applied to the front and rear gates of the transistors 412, 414, in other embodiments, it would be possible to apply two separate signals to the front and rear gates, these signals having for example the same frequency to within 5%.

[0081] An example of a transceiver is described below in relation to [Fig.6] in as a possible example of application of the active or passive mixer of the present description. Of course, other possible applications of this mixer are known to those skilled in the art.

[0082] [Fig.6] represents an electronic circuit 600 comprising at least one frequency mixer according to an embodiment of the present description.

[0083] The circuit 600 is a transceiver for receiving or transmitting information. For example, the circuit 600 makes it possible to receive or transmit encoded binary information, for example by phase-shift keying.

[0084] The information is received by an Rx input or transmitted from a Tx output of the circuit by an antenna 610. The Rx / Tx input / output is for example connected to a reception chain 615 and to a transmission chain 616.

[0085] The reception chain 615 comprises a low noise amplifier LNA configured to receive an RF signal from the antenna 610, and to amplify this signal. The output of the low noise amplifier LNA is connected to the input of a first mixer 620 of a first sub-chain for processing a first component I of the RF input signal and to the input of a second mixer 622 of a second sub-chain for processing a second component Q of the RF input signal. The mixers 620 and 622 are for example produced by the mixers 300, 400 or 500 described previously.

[0086] The circuit 600 comprises, for example, a phase-locked loop (PLL) configured to generate the periodic signal LO. In the differential case, the periodic signal generated by the PLL is composed of a LO+ component and a LO- component. The output of the PLL is connected to the front and rear gates of the mixer 620.

[0087] The mixer 620 is configured to modulate the RF input signal by the LO periodic signal coming from the PLL. The output of the mixer 620 is connected to the input of a first programmable gain amplifier PGA configured to amplify the IF output signal of the mixer 620. The output of the first PGA is connected to the input of a first low-pass filter LPF configured to filter the output signal of the PGA. The output of the first LPF is connected to the input of a first analog-to-digital converter ADC configured to convert the analog signal at the output of the first LPF into a first digital signal BB_I.

[0088] The output of the PLL is also connected to the input of an ir / 2 module configured to phase shift the periodic signal generated by the PLL by 90°. In the differential case, the two components are phase shifted by 90°. The output of the ir / 2 module is connected to the front and rear gates of the mixer 622 of the sub-chain for processing the Q component of the RF signal.

[0089] The mixer 622 is configured to modulate the RF input signal by the 90° phase-shifted LO periodic signal coming from the ji / 2 module. The output of the mixer 622 is connected to the input of a second programmable gain amplifier PGA configured to amplify the IF output signal of the mixer 622. The output of the second PGA is connected to the input of a second low-pass filter LPF configured to filter the output signal of the second PGA. The output of the second LPF is connected to the input of a second analog-to-digital converter ADC configured to convert the analog signal at the output of the second LPF into a second digital signal BB_Q.

[0090] The RF analog signal received by the antenna 610 is therefore separated by the processing chain 615 into two digital signals BB_I and BB_Q, corresponding to the I and Q components of the demodulated signal, the components being phase-shifted by 90° relative to each other.

[0091] Conversely, the transmission of an RF signal by the antenna 610 comprises for example the processing of two digital components BB_F and BB_Q' by the second processing chain 616.

[0092] The signal BB_F is processed by a first processing sub-chain and the signal BB_Q' is processed by a second processing sub-chain.

[0093] The signal BB_F is received by a first digital to analog converter DAC configured to convert the signal BB_I' into an analog signal and whose output is connected to the input of a third LPF configured to filter the output signal of the first DAC. The output of the third LPF is connected to the input of a third PGA configured to amplify the output signal of the third LPF. The output of the third PGA is connected to the input of the mixer 625. The output of the module ir / 2 is also connected to the front and rear gates of the mixer 625 which is configured to modulate the signal corresponding to the component I by the periodic signal LO phase-shifted by 90° by the module ji / 2. The output of the mixer 625 is connected to the input of a power amplifier PA.

[0094] The signal BB_Q' is received by a second digital to analog converter DAC configured to convert the signal BB_Q' into an analog signal and whose output is connected to the input of a fourth LPF configured to filter the output signal of the second DAC. The output of the fourth LPF is connected to the input of a fourth PGA configured to amplify the output signal of the fourth LPF. The output of the fourth PGA is connected to the input of the mixer 627. The output of the PLL is also connected to the front and rear gates of the mixer 627 which is configured to modulate the signal corresponding to the Q component by the periodic signal LO generated by the PLL. The output of the mixer 627 is connected to the input of the power amplifier PA.

[0095] The output signals of mixers 625 and 627 are superimposed on the input of the power amplifier which is configured to amplify the combined analog signal. The output of the PA is connected to the Tx output of the circuit 600 configured to transmit the signal through the antenna 610.

[0096] Figures 7 to 9 represent characteristic quantities of the circuit described in relation to [Fig.4] resulting from simulations carried out with a continuous rear gate voltage VBB “DC VBB” or a rear gate voltage VBB comprising a continuous component and a periodic component “DC + dynamic VBB”.

[0097] [Fig.7] represents the noise figure NF of the frequency mixer of [Fig.4] as a function of the power of the input signal PRF in dBm for a continuous back gate voltage VBB (“DC VBB”) or periodic with a continuous offset (“DC + dynamic VBB”) for three continuous values 0V (“VBB=0”), 0.3V (“VBB=0.3”) and 0.5V (“VBB=0.5”). The noise figure is the degradation of the signal to noise ratio between the input and the output of a device.

[0098] For input power ranging from -20dB to 7dB, the noise figure is reduced by using a back gate voltage oscillating at a frequency close to or equal to the frequency of the input RF signal.

[0099] [Fig.8] represents the gain G of the passive frequency mixer 400 of [Fig.4] as a function of the power of the input signal PRF for a continuous VBB back gate voltage “DC VBB” or periodic with a continuous offset “DC + dynamic VBB” for three continuous values 0V (“VBB=0”), 0.3V (“VBB=0.3”) and 0.5V (“VBB=0.5”). The gain of the circuit represents the ratio between the amplitudes of the input and output signals of the circuit.

[0100] For input power ranging from -20dB to 15dB, the gain is higher for a periodic back gate voltage.

[0101] [Fig.9] represents the compression points at -IdB at input IIP1 and output OIP1 of the passive frequency mixer 400 of [Fig.4] as a function of the DC back gate voltage applied to the transistors of the circuit for a DC back gate voltage VBB "DC VBB" or periodic with a DC offset "DC + dynamic VBB". The compression point at -IdB corresponds to the input or output power level resulting from a 1 dB attenuation of the output power compared to the straight line obtained at low power of the output power as a function of the input power in dBm.

[0102] For a back gate voltage ranging from -200mV to 500mV, the compression points IIP1 and OIP1 are higher for a periodic back gate voltage. These parameters are representative of the compression of a signal caused by a circuit.

[0103] In conclusion, the use of SOI transistors coupled with the application of a periodic signal on the back gate of the transistors allows a reduction of the noise generated by the frequency mixer and / or an increase in the gain and / or linearity.

[0104] Figures 10 and 11 illustrate the impact of the phase difference between the periodic signals applied to the front and back gates of the SOI transistors in the active frequency mixer 500 of [Fig.5]. The behavior is, in these examples, different for the example of the passive mixer 400 and the example of the active mixer 500.

[0105] [Fig. 10] represents the compression points at -IdB at input IIP1 and the corresponding output power OIP1 of the first order of the active frequency mixer of [Fig.5] as a function of the phase difference between the signals applied to the front and rear gates ("Phase shift") of the transistors of the circuit for a continuous rear gate voltage VBB "DC VBB" or periodic with a continuous offset "DC + dynamic VBB". In the case of the active circuit of [Fig.5], two periodic signals in phase (Phase shift=1) generate compression points IIP1 and OIP1 higher than the values obtained with continuous signals. On the contrary, two periodic signals in phase opposition (Phase shift=0) generate compression points IIP1 and OIP1 lower than the values obtained with continuous signals.In other embodiments, with a different definition of the LO signals, one could also have an improvement in linearity with two periodic signals in phase opposition.

[0106] [Fig. 11] represents the gain G of the frequency mixer of [Fig. 5] as a function of the power of the input signal PRF for a continuous rear gate voltage VBB "DC VBB", for periodic front and rear gate voltages with a continuous and in-phase offset "DC + dynamic VBB, in phase" and for periodic front and rear gate voltages with a continuous and out-of-phase offset "DC + dynamic VBB, out of phase". In the example of the mixer of [Fig. 5], the gain of the circuit is maximum for periodic and out-of-phase signals and in particular greater than continuous signals and it is minimum for periodic and in-phase signals.

[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, circuits made with n-channel transistors could be adjusted for p-channel transistors.

Claims

Claims

1. Electronic frequency mixer (400, 500) comprising: - at least one transistor (210, 410, 412, 414, 416), comprising a front gate (G), a back gate (BB), a source (S) and a drain (D), wherein: - the source is connected to a node for applying a radio frequency input signal (RF, RF+, RF-); - the front gate is connected to a node for applying a first periodic signal (LO, LO+, LO-) at a first frequency; and - the back gate is connected to a node for applying the first periodic signal (LO, LO+, LO-) or a second periodic signal (LO') at the first frequency.

2. An electronic frequency mixer according to claim 1, wherein the at least one transistor is of the silicon-on-insulator type.

3. An electronic frequency mixer according to any one of claims 1 to 2, wherein either the front and rear grids receive the first periodic signal (LO, LO+, LO-), or the front grid receives the first periodic signal (LO, LO+, LO-), and the rear grid receives the second periodic signal (LO'), the first and second periodic signals being in phase.

4. An electronic frequency mixer according to any one of claims 1 to 2, wherein the front grid receives the first periodic signal (LO, LO+, LO-), and the rear grid receives the second periodic signal (LO'), the first and second periodic signals being in phase opposition.

5. An electronic frequency mixer according to any one of claims 1 to 4, wherein the at least one transistor comprises at least four transistors (410, 412, 414, 416).

6. Electronic frequency mixer according to claim 5, wherein the four transistors (410, 412, 414, 416) are organized in two pairs in which: - the sources of the first pair of transistors (410, 412) are connected to a node for applying a first radio frequency input signal (RF+); - the sources of the second pair of transistors (414, 416) are connected to a node for applying a second radio frequency input signal (RF-), the first and second radio frequency input signals being

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13. differential signals; - the front and rear gates of a first transistor of each pair of transistors (410, 416) are connected to a node for applying a first periodic signal (LO+); and - the front and rear gates of a second transistor of each pair of transistors (412, 414) are connected to a node for applying a second periodic signal (LO-), the first and second periodic signals being differential signals. An electronic frequency mixer according to any one of claims 1 to 6, wherein the mixer (400) is a passive mixer. An electronic frequency mixer according to any one of claims 1 to 6, wherein the mixer (500) is an active mixer. An electronic frequency mixer according to claim 8, wherein the input signal is generated by an amplification stage. An electronic frequency mixer according to any one of claims 1 to 9, wherein the duty cycle of the first periodic signal is identical to the duty cycle of the second periodic signal to within 5%. Electronic frequency mixer according to any one of claims 1 to 10, wherein the drain of the at least one transistor (210, 410, 412, 414, 416) is connected to the output of the mixer (420, 430). Electronic circuit comprising: - an antenna (610); and - at least one mixer (620, 622, 625, 627) according to any one of claims 1 to 11. Electronic circuit according to claim 12, further comprising: - a circuit for receiving (615) a radio frequency signal comprising: (a) a low noise amplifier (LNA) having an input connected to the antenna; and b) the at least one mixer (620, 622, 625, 627) comprising a first (622) and a second (620) mixer, the radio frequency input signal of each of the first and second mixers being a signal from the low noise amplifier (LNA), and the first and / or second periodic signal of the first mixer being phase shifted by 90° (ji / 2) relative to the first and / or second periodic signal of the second mixer.

14. Electronic circuit according to claim 12 or 13, further comprising: - a circuit for transmitting (616) a radio frequency signal comprising: a) a power amplifier (PA) having an output connected to the antenna (610); b) the at least one mixer (620, 622, 625, 627) comprising a third (625) and a fourth (627) mixer, an output of each of the third and fourth mixers being connected to the power amplifier (PA), the first and / or the second periodic signal of the third mixer being phase shifted by 90° (ji / 2) relative to the first and / or the second periodic signal of the fourth mixer.

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