DDC phase synchronization method and system based on multi-channel sampling of FPGA system

Abstract

The application discloses a DDC phase synchronization method and system based on FPGA system multi-channel sampling, and relates to the technical field of signal processing, and comprises the following steps: a plurality of analog-to-digital converters collect original multi-channel AD data by using a common clock; phase errors between channel data are calculated by using pre-cached partial AD data; if the phase errors are within a transmission error range, a plurality of digital mixers with uniform start signals are used to respectively perform digital down-conversion on the AD data after phase error calibration, so that the phases of output signals of the digital mixers are all from 0 degrees, and the phases of multi-channel AD data after mixing are consistent. When the application deals with multi-channel AD sampling, phase calibration is performed on original data, digital down-conversion is used to synchronously start mixers, and the mixing output phases are consistent. Compared with a traditional channelization mode, the same effect of output data phase synchronization is achieved, and the digital down-conversion configuration is more flexible.

Description

Technical Field

[0001] The present invention relates to the field of signal processing technology, in particular to a DDC phase synchronization method and system based on FPGA system multi-channel sampling. Background Art

[0002] With the continuous advancement of electronic information technology, channelization techniques have gradually matured in signal processing. Fast Fourier transform (FFT)-based channelization schemes offer a simple implementation structure and can maintain multi-channel channelized phase synchronization, but their filtering performance is limited. This significantly increases resource usage and reduces flexibility when acquiring data from multi-channel analog-to-digital converters (ADCs). This makes them less suitable for multi-channel ADC acquisition scenarios. Digital down-conversion (DDC) technology, due to its flexibility, is more suitable for phase synchronization of multi-channel ADC data. Digital down-conversion (DDC) is a core technology in software-defined radio (SDR) systems. It converts the mixed intermediate frequency (IF) signal at the receiver into a baseband signal through a process involving digital mixing, filtering, and decimation. Its core technical principles include orthogonal mixing, digital filter design, and sampling rate control. Spectrum shifting is achieved through the generation of local carriers using numerically controlled oscillators (NCOs). Multi-stage filter banks are used to eliminate image interference and reduce the data rate. Compared to traditional analog down-conversion techniques, it offers advantages such as strong interference immunity, flexible parameter adjustment, and high phase stability. It is widely used in communication systems, radar receivers, and 5G base station RF front-end modules. When multiple analog-to-digital converters (ADCs) in a communication system acquire the same signal, transmission delays or other factors often lead to phase inconsistencies in the acquired AD signals. This results in larger phase errors in the output DDCs, affecting direction-finding and positioning accuracy. While traditional channelization can synchronize the phases of individual signals, each set of AD signals requires significant resources. Summary of the Invention

[0003] The purpose of the present invention is to provide a DDC phase synchronization method and system based on multi-channel sampling of an FPGA system, which is used to solve the problem that the traditional channelized method can synchronize the phase of a single signal, but each group of AD signals requires resources. When facing multi-channel AD sampling, there are many output channels, which occupies a lot of resources and is not flexible enough.

[0004] The present invention solves the above problems through the following technical solutions:

[0005] A DDC phase synchronization method based on multi-channel sampling of an FPGA system, comprising:

[0006] Step S1: multiple analog-to-digital converters acquire original multi-channel analog-to-digital (AD) data using the same clock source, and pre-cache part of the multi-channel AD data;

[0007] Step S2: Use some pre-cached multi-channel AD data to calculate the phase error between the channel data. If the phases between the channel data are inconsistent and the phase error is within the transmission error range, jump to step S3; if the phases between the channel data are consistent, jump to step S4; if the phase error is not within the error range, check whether the front-end hardware uses the same source clock synchronization. After confirmation, repeat step S1;

[0008] Step S3, performing phase error calibration on the original multi-channel AD data;

[0009] Step S4: using multiple digital mixers to perform digital down-conversion on the multi-channel AD data respectively. The multiple digital mixers use a unified start signal to ensure that the phase of the output signal of each digital mixer starts from 0 degrees, ensuring that the phase of the multi-channel AD data after mixing is consistent;

[0010] Step S5: low-pass filter the data output by the digital mixer and then output it.

[0011] Compared with the existing method, each group of AD signals needs to be multi-phase filtered and divided into multiple sub-channels. In order to avoid signal loss, the sub-channels need to overlap by 50%, and then DDC down-conversion is performed. Each group of AD signals needs to occupy resources. When facing multi-channel AD sampling, there are many output channels, many resources are occupied, and the use is not flexible. The present invention performs phase calibration at the multi-channel AD data, reducing the process of multi-phase filtering to decompose the channel, and taking advantage of the flexible setting of multi-channel DDC, only two-thirds of the number of channels of traditional channelization is needed to monitor the frequency band signals required for acquisition. The amount of FPGA resources used is smaller, the detection of the target signal is more complete, and the situation where the signal cannot be detected at the sub-band boundary in the channelization scheme will not occur.

[0012] Furthermore, the method for calibrating the phase error of the original multi-channel AD data is: fixing one of the channels as a reference channel, and making the phase amplitudes of the remaining channels consistent with the reference channel.

[0013] Furthermore, the specific method of fixing one of the channels as a reference channel and making the phase amplitudes of the remaining channels consistent with the reference channel is:

[0014] Perform fast Fourier transform (FFT) on the multi-channel AD data, set one of the channels as the reference channel, and obtain the amplitude and phase differences between the remaining channels and the reference channel, which are used to correct the phase and amplitude after subsequent frequency conversion;

[0015] Multichannel ADC data is mixed at 1 / 4*Fs and then low-pass filtered to generate IQ signals. The center frequency of the IQ signals is IF – 1 / 4*Fs. These signals are then multiplied by the amplitude and phase differences and up-converted by 1 / 4*Fs to convert them into real signals with a center frequency of IF and the same amplitude and phase as the reference channel. Fs is the sampling rate, and IF is the intermediate frequency. The amplitude and phase difference outputs are used here to scale the original signals to uniform amplitude and phase.

[0016] A DDC phase synchronization system based on multi-channel sampling of an FPGA system, comprising:

[0017] Analog-to-digital converter module, used for collecting multi-channel AD data and pre-caching part of the multi-channel AD data;

[0018] Phase difference data calculation module, used to calculate the phase error between channel data using part of the pre-cached multi-channel AD data and determine whether the phase error is within the transmission error range;

[0019] The phase calibration module is used to calibrate the phase error of the original multi-channel AD data according to the phase error calculation result of the phase difference calculation module;

[0020] A digital mixer module, comprising the same number of digital mixers as the number of channels, configured to digitally down-convert the data of each channel using a unified start signal when the phase difference calculation module calculates that the phases of the channel data are consistent, or after the phase calibration module calibrates the phase errors of the data of each channel;

[0021] A low-pass filter module, comprising the same number of low-pass filters as the number of digital mixers, for performing low-pass filtering on the data output by the digital mixers and then outputting the data;

[0022] The synchronous signal control module is used to generate switching signals and reset signals for simultaneously controlling multiple digital mixers.

[0023] Furthermore, the phase calibration module includes:

[0024] The amplitude and phase difference calculation unit is used to perform fast Fourier transform (FFT) on the multi-channel AD data, set one of the channels as the reference channel, and obtain the amplitude and phase differences between the remaining channels and the reference channel and output them for subsequent phase and amplitude correction after frequency conversion;

[0025] The mixing unit is used to perform 1 / 4*Fs mixing processing on the multi-channel AD data, where Fs is the sampling rate;

[0026] A low-pass filtering unit is used to perform low-pass filtering on the mixed data to obtain an IQ signal with a center frequency of IF–1 / 4*Fs, where IF is an intermediate frequency;

[0027] The up-conversion unit is used to multiply the IQ signal with a center frequency of IF-1 / 4*Fs by the amplitude-phase difference and then up-convert it by 1 / 4*Fs to obtain a real signal with a center frequency of IF and the same amplitude and phase as the reference channel.

[0028] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0029] (1) When dealing with multi-channel AD sampling, the present invention performs phase calibration at the original data and uses digital down-conversion to synchronously start the mixer to make the mixed output phase consistent. Compared with the traditional channelization method, the output data phase synchronization effect is also achieved, and the digital down-conversion configuration is more flexible.

[0030] (2) The present invention performs phase calibration at the channel AD data, reducing the process of polyphase filtering to decompose the channel. The DDC center frequency is configurable, requiring fewer channels to monitor the desired frequency band signal. This reduces the amount of FPGA resources used and improves target signal detection, eliminating the problem of signals being unable to be detected at sub-band boundaries, as in channelized solutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a flow chart of the present invention;

[0032] Figure 2 This is a flow chart of the digital down conversion of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the examples, but the embodiments of the present invention are not limited thereto.

[0034] Example 1:

[0035] Combined with attachment Figure 1 and Figure 2 As shown, a DDC phase synchronization method based on multi-channel sampling of an FPGA system includes:

[0036] Step S1: multiple analog-to-digital converters acquire original multi-channel analog-to-digital (AD) data using the same clock source, and pre-cache part of the multi-channel AD data;

[0037] Step S2: Use some pre-cached multi-channel AD data to calculate the phase error between the channel data. If the phases between the channel data are inconsistent and the phase error is within the transmission error range, jump to step S3; if the phases between the channel data are consistent, jump to step S4; if the phase error is not within the error range, check whether the front-end hardware uses the same source clock synchronization. After confirmation, repeat step S1;

[0038] Step S3, phase error calibration is performed on the original multi-channel AD data.

[0039] Step S4, a plurality of digital mixers are used to respectively perform digital down-conversion on the multi-channel AD data, the plurality of digital mixers use a unified start signal, so that the phases of the output signals of the digital mixers are all from 0 degrees, and the phases of the multi-channel AD data after mixing are consistent; the consistent phases of the output signals of the mixers and the start from 0 degrees ensure that the phases of the data of the channels after mixing remain consistent, and the subsequent low-pass filtering has no effect on the phases, so that the consistency of the phases after digital down-conversion can be ensured.

[0040] Step S5, the data output by the digital mixer is subjected to low-pass filtering and then output.

[0041] Compared with the prior art, in which each group of AD signals needs to be subjected to polyphase filtering, divided into a plurality of sub-channels, and overlapped by 50% between the sub-channels to avoid signal loss, and then subjected to DDC down-conversion, each group of AD signals needs to occupy resources, and in the case of multi-channel AD sampling, the output channels are more, the resources are more occupied, and the use is not flexible. The application performs phase calibration on the multi-channel AD data, reduces the process of polyphase filtering and sub-channel decomposition, and uses the flexible feature of multi-channel DDC, so that only two-thirds of the number of traditional channels are needed to monitor the frequency band signals required to be collected. The amount of FPGA resources used is less, and the detection of the target signal is more perfect, and the situation that the signal cannot be detected at the sub-band junction in the channelization scheme does not occur.

[0042] Further, the method for performing phase error calibration on the original multi-channel AD data is that one of the channels is fixed as a reference channel, and the phases and amplitudes of the remaining channels are consistent with the reference channel.

[0043] Further, the specific method for fixing one of the channels as a reference channel and making the phases and amplitudes of the remaining channels consistent with the reference channel is that:

[0044] The multi-channel AD data is subjected to fast Fourier transform (FFT), one of the channels is set as a reference channel, the amplitude and phase differences between the remaining channels and the reference channel are obtained respectively, and the amplitude and phase differences are output for subsequent correction after frequency conversion;

[0045] The multi-channel AD data is subjected to 1 / 4*Fs mixing processing, and then subjected to low-pass filtering to obtain an IQ signal, the center frequency of the IQ signal is IF-1 / 4*Fs, the IQ signal is converted into a real signal with the center frequency IF and the same amplitude and phase as the reference channel by multiplying the amplitude and phase differences and then performing 1 / 4*Fs up-conversion, wherein Fs is a sampling rate, and IF is an intermediate frequency.

[0046] Example 2:

[0047] A DDC phase synchronization system based on multi-channel sampling of an FPGA system, comprising:

[0048] Analog-to-digital converter module, used for collecting multi-channel AD data and pre-caching part of the multi-channel AD data;

[0049] Phase difference data calculation module, used to calculate the phase error between channel data using part of the pre-cached multi-channel AD data and determine whether the phase error is within the transmission error range;

[0050] The phase calibration module is used to calibrate the phase error of the original multi-channel AD data according to the phase error calculation result of the phase difference calculation module; this module works once at the beginning of the process to complete the phase calibration between the AD data of each channel.

[0051] The digital mixer module includes the same number of digital mixers as the number of channels. When the phase difference calculation module calculates that the phases between the channel data are consistent, or after the phase calibration module calibrates the phase errors of the channel data, the multiple digital mixers use a unified start signal to digitally down-convert the data of each channel. The difference from traditional digital down-conversion control is that the mixers of the multiple digital down-conversion modules use a unified switch and reset control signal.

[0052] A low-pass filter module, comprising the same number of low-pass filters as the number of digital mixers, for performing low-pass filtering on the data output by the digital mixers and then outputting the data;

[0053] The synchronization signal control module is used to generate switching signals and reset signals for simultaneously controlling multiple digital mixers to ensure the synchronization of subsequent processing.

[0054] Furthermore, the phase calibration module includes:

[0055] The amplitude and phase difference calculation unit is used to perform fast Fourier transform (FFT) on the multi-channel AD data, set one of the channels as the reference channel, and obtain the amplitude and phase differences between the remaining channels and the reference channel;

[0056] The mixing unit is used to perform 1 / 4*Fs mixing processing on the multi-channel AD data, where Fs is the sampling rate;

[0057] A low-pass filtering unit is used to perform low-pass filtering on the mixed data to obtain an IQ signal with a center frequency of IF–1 / 4*Fs, where IF is an intermediate frequency;

[0058] The up-conversion unit is used to multiply the IQ signal with a center frequency of IF-1 / 4*Fs by the amplitude-phase difference and then up-convert it by 1 / 4*Fs to obtain a real signal with a center frequency of IF and the same amplitude and phase as the reference channel.

[0059] Although the present invention is described herein with reference to illustrative embodiments of the present invention, the above embodiments are merely preferred embodiments of the present invention, and the embodiments of the present invention are not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and implementations, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A DDC phase synchronization method based on multi-channel sampling of FPGA system, characterized in that: include: Step S1: multiple analog-to-digital converters acquire original multi-channel analog-to-digital (AD) data using the same clock source, and pre-cache part of the multi-channel AD data; Step S2: Use part of the pre-cached multi-channel AD data to calculate the phase error between the channel data. If the phases between the channel data are inconsistent and the phase error is within the transmission error range, jump to step S3; If the phases between the channel data are consistent, jump to step S4; if the phase error is not within the error range, check whether the front-end hardware uses the same clock synchronization. After confirmation, repeat step S1; Step S3, performing phase error calibration on the original multi-channel AD data; Step S4: using multiple digital mixers to perform digital down-conversion on the multi-channel AD data respectively. The multiple digital mixers use a unified start signal to ensure that the phase of the output signal of each digital mixer starts from 0 degrees, ensuring that the phase of the multi-channel AD data after mixing is consistent; Step S5, performing low-pass filtering on the data output by the digital mixer and then outputting the result; The method for calibrating the phase error of the original multi-channel AD data is: fixing one of the channels as a reference channel and making the phase amplitudes of the remaining channels consistent with the reference channel. The specific method is: Perform fast Fourier transform (FFT) on the multi-channel AD data, set one of the channels as the reference channel, and obtain the amplitude and phase differences between the remaining channels and the reference channel; The multi-channel AD data is mixed with 1 / 4*Fs and then low-pass filtered to obtain an IQ signal. The center frequency of the IQ signal is IF-1 / 4*Fs. The IQ signal is multiplied by the amplitude and phase difference and then up-converted with 1 / 4*Fs to convert it into a real signal with a center frequency of IF and the same amplitude and phase as the reference channel, where Fs is the sampling rate and IF is the intermediate frequency.

2. A DDC phase synchronization system based on multi-channel sampling of FPGA system, characterized in that: include: Analog-to-digital converter module, used for collecting multi-channel AD data and pre-caching part of the multi-channel AD data; Phase difference data calculation module, used to calculate the phase error between channel data using part of the pre-cached multi-channel AD data and determine whether the phase error is within the transmission error range; The phase calibration module is used to calibrate the phase error of the original multi-channel AD data according to the phase error calculation result of the phase difference calculation module; A digital mixer module, comprising the same number of digital mixers as the number of channels, configured to digitally down-convert the data of each channel using a unified start signal when the phase difference calculation module calculates that the phases of the channel data are consistent, or after the phase calibration module calibrates the phase errors of the data of each channel; A low-pass filter module, comprising the same number of low-pass filters as the number of digital mixers, for performing low-pass filtering on the data output by the digital mixers and then outputting the data; A synchronization signal control module, used to generate switching signals and reset signals for simultaneously controlling multiple digital mixers; The phase calibration module includes: The amplitude and phase difference calculation unit is used to perform fast Fourier transform (FFT) on the multi-channel AD data, set one of the channels as the reference channel, and obtain the amplitude and phase differences between the remaining channels and the reference channel and output them for subsequent phase and amplitude correction after frequency conversion; The mixing unit is used to perform 1 / 4*Fs mixing processing on the multi-channel AD data, where Fs is the sampling rate; A low-pass filtering unit is used to perform low-pass filtering on the mixed data to obtain an IQ signal with a center frequency of IF–1 / 4*Fs, where IF is an intermediate frequency; The up-conversion unit is used to multiply the IQ signal with a center frequency of IF-1 / 4*Fs by the amplitude-phase difference and then up-convert it by 1 / 4*Fs to obtain a real signal with a center frequency of IF and the same amplitude and phase as the reference channel.

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