computer device

Abstract

The present invention relates to a computer device equipped with at least one memory card, and more particularly to a memory card comprising a plurality of memory circuits, each of these circuits being equipped with an internal processor. The present invention proposes a memory card architecture compatible with existing protocols, and in particular the DDR5 protocols, while implementing internal memory controllers, hereinafter referred to as internal controllers, and allowing complete read or write commands to be associated with a single memory circuit. Figure 3

Description

Title of the invention: computer device FIELD OF THE INVENTION

[0001] The present invention relates to the field of computer devices equipped with memories, and in particular memories equipped with internal processors (hereinafter "PIM memory circuit"). These internal processors give said memories a capacity for processing and / or calculating the data they contain.

[0002] More particularly, the present invention relates to an architecture and a protocol adapted to better take into account the presence of internal processors. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Figure 1 illustrates a computer device 1 known from the prior art. In particular, this computer device comprises a main processor 2, a memory controller 3 and a memory card 4.

[0004] The main processor 2 is, for example, a processing and control unit of an electronic device such as a computer, calculator, or other equipment capable of performing logical functions. In particular, the main processor 2 may be a central processing unit (CPU). In the present case, the main processor 2 is intended to generate read and / or write requests to the memory card 4.

[0005] The memory controller 3 is interposed between the main processor 2 and the memory card 4 and is configured to translate requests from the main processor 2 (symbolized by arrow "A" in [Fig. 1]) according to a specific memory protocol before forwarding them to the memory card 4. The memory controller 3 is also configured to forward responses to requests from the memory card 4 back to the main processor 2 (symbolized by arrow "B" in [Fig. 1]). Among the known memory protocols, the DDR5 protocol ("Double Data Rate" in Anglo-Saxon terminology) is of particular interest since it allows for a reduction in power consumption compared to the DDR4 protocol while doubling the bandwidth.

[0006] The memory card 4 comprises a plurality of memory circuits, for example four memory circuits 5a, 5b, 5c and 5d. Each of these memory circuits 5a, 5b, 5c and 5d comprises one or more memory banks 6a, 6b, 6c and 6d. Each memory bank 6a, 6b, 6c and 6d comprises a plurality of rank k of memory cells.

[0007] Each of these memory circuits 5a, 5b, 5c and 5d is connected to the memory controller 3 by a first and a second bus. In particular, the first bus, called the channel 8 control and address bus, connects all of the control and address ports of each memory circuit 5a, 5b, 5c and 5d, while the second bus, called data bus 9, only partially connects each of the data ports of said memory circuits 5a, 5b, 5c and 5d.

[0008] Thus, by way of example, a memory card, in particular of the DDR5 type and having a 32-bit channel, may comprise 4 memory circuits 5a, 5b, 5c and 5d, each comprising an 8-bit wide data port. According to this configuration, memory circuit 5d may be connected to bits [31:24] of the data bus 9, memory circuit 5c may be connected to bits [23:16] of the data bus 9, memory circuit 5b may be connected to bits [15:8] of the data bus 9, and memory circuit 5a may be connected to bits [7:0] of the data bus 9.

[0009] According to this architecture, the main processor 2 perceives a continuous block of memory cells, although these are distributed across a plurality of distinct memory circuits 4. For example, writing 64 bytes of data can be distributed across each of the 4 memory circuits 5.

[0010] As illustrated in [Fig.2], it may be a question of implementing PIM memory circuits 5a, 5b, 5c and 5d. These, like the memory circuits 5a, 5b, 5c and 5d described in relation to [Fig.1], comprise one or more memory banks 6a, 6b, 6c and 6d, but are each also provided with an internal processor 7a, 7b, 7c and 7d.

[0011] Thus, the architecture shown in [Fig.2] differs from that shown in [Fig.1] in that the PIM memory circuits 5a, 5b, 5c and 5d each include an internal processor 7a, 7b, 7c and 7d. Such PIM memory circuits are described in patent application WO 2017 / 055732 A1.

[0012] The implementation of a standard memory protocol, such as the DDR5 protocol, on an architecture conforming to that shown in [Fig.2] remains problematic.

[0013] Indeed, each internal processor 7a, 7b, 7c, and 7d is only sensitive to (i.e., can only process or read) data written to the PIM memory circuit 5a, 5b, 5c, and 5d in which it is integrated. In other words, information distributed across several memory circuits, as envisaged by the standard memory protocol, can only be processed, calculated, or read by a single internal processor 7a, 7b, 7c, and 7d.

[0014] Furthermore, and still in relation to the architecture represented in [Fig.2], the implementation of a standard memory protocol of the DDR5 type does not allow hardware arbitration between requests from the main processor 2 and requests from an internal processor 7a, 7b, 7c and 7d.

[0015] In order to overcome the aforementioned problems, software solutions have been proposed in patent application WO 2017 / 055732 A1 and patent EP 3 259 674 Bl.

[0016] However, these solutions, although effective, are difficult to use.

[0017] Alternatively, it could be considered to modify the standard memory protocols extensively. However, this alternative remains lengthy and costly and therefore cannot be considered a preferred solution.

[0018] One object of the invention is therefore to propose an architecture, and in particular a computer device equipped with PIM memory circuits, enabling the aforementioned problems to be solved without significantly modifying the memory controller and the internal processors. BRIEF DESCRIPTION OF THE INVENTION

[0019] The present invention relates to a computer device comprising:

[0020] - a memory card provided with a set of n memory circuits, each called a circuit i for i from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0021] - a main processor configured to issue requests, called queries primary ik, each primary ik query targeting an address, called address ik, of one or more ranks of one or more banks of circuit i;

[0022] - a memory controller implementing an access protocol, known as a native protocol, said native protocol being configured to allow the memory controller to access the n circuits i in parallel;

[0023] - at least one bus configured to carry commands, addresses and data ;

[0024] The computer device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, referred to as internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, referred to as primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit, via the memory controller,This set of secondary execution acknowledgments to the pre-controller, which is also configured to reconstruct the primary execution acknowledgment from the set of secondary execution acknowledgments, the pre-controller is also configured to provide the main processor with primary results ik in response to a primary request ik from , reading data, called ik data, stored in circuit i, the primary results ik forming a primary execution confirmation and include the ik data; each internal controller i is further configured to also execute memory access requests, called internal requests, from the internal processor, the internal controller i is also configured to generate, for the execution of primary requests as well as internal requests, all the operations necessary to access the memory of memory circuit i, and when necessary, in place of the memory controller, preload the banks, activate the memory ranks as well as the memory rank refresh operations when such operations are necessary.

[0025] The native protocol, configured to allow the memory controller to access the n circuits i in parallel, implies that said native protocol allows the memory controller to execute requests, including send requests described later in this statement, by generating commands. In particular, and this will become clearer later in this statement, a send request can be formed from several sub-requests, each sub-request targeting a different circuit i and potentially being executed in parallel on the different circuits i actually targeted. Furthermore, it is understood that a read or write command of the native protocol is addressed to all circuits i.

[0026] According to one implementation mode, the primary execution confirmation of a primary read query ik includes the data read by the corresponding read operation.

[0027] According to one embodiment, the pre-controller is configured to encode each secondary request of a set of secondary requests ik into a send request, a send request being able to include up to n secondary requests each targeting a different circuit i, the pre-controller is also configured to send each send request to the memory controller, the memory controller is for its part configured to generate a sequence of commands of its native protocol, said sequence of commands enabling the execution of the send request, the sequence of commands including at least one command, said send command, for writing memory of the native protocol.

[0028] It is understood that the sequence of commands considered above allows the transmission of each secondary request forming the send request within the circuit i targeted by said secondary request.

[0029] It is understood that a send request can only include one secondary request from a given set of secondary requests ik.

[0030] According to one embodiment, the internal controller of a circuit i is configured to extract secondary requests from the send commands it receives and targeting the circuit i under consideration.

[0031] According to one embodiment, the pre-controller is configured so that, when it expects, in return to send commands that it has previously sent, that execution acknowledgments are pending in one or more circuit i, it generates read requests, called response requests, and transmits them to the memory controller, so that the latter executes them by generating sequences of commands of the native protocol on the bus or buses linking the memory controller to the circuits i, this sequence of commands comprising at least one command, called a response command, each response command being a memory read command of the native protocol.

[0032] According to one embodiment, the internal controller i is configured to encode secondary execution acknowledgments in the responses it provides to native protocol read commands, and because a response to a read command consists of the responses generated by the plurality of circuits i, such a response is likely to include several secondary execution acknowledgments issued by different circuits i.

[0033] According to one implementation method, the send requests have the same format and encoding as primary write requests.

[0034] According to one implementation method, the response requests have the same format and encoding as primary read requests.

[0035] According to one embodiment, a secondary request targeting circuit i is encoded, totally or partially, in the data to be written intended for circuit i, of a send request, this data to be written subsequently being conveyed by at least one send command.

[0036] According to one implementation mode, the internal controller of circuit i is configured to ignore, in a series of commands issued by the memory controller, the commands of the native protocol responsible for preloading one or more memory banks and those responsible for activating one or more memory ranks.

[0037] According to one implementation mode, the internal controller of circuit i is configured to ignore native protocol commands, issued by the memory controller, in charge of refreshing one or more memory ranks.

[0038] According to one embodiment, the pre-controller includes a buffer memory, called pre-controller memory, in which each primary request ik is recorded in a register, called pre-register tik, before its processing, and in which each internal controller i includes a buffer memory called intermediate buffer i.

[0039] According to one embodiment, said computer device is configured to assign an identifier, called the primary identifier, to each primary query ik, and one or more identifiers, called secondary identifiers, to each of the secondary queries in a set of secondary queries ik, the set of primary and secondary identifiers allowing each primary query ik to be associated with the set of secondary queries ik resulting from the decomposition of said primary query ik and to associate in return a primary execution confirmation ik with the set of secondary execution confirmation ik resulting from the decomposition of said primary execution confirmation.

[0040] According to one implementation, the internal controller is configured to reconstruct a primary request ik by recording in an intermediate buffer, as they are received, the secondary requests ik, or at least sufficient elements thereof, the internal controller also being configured to execute a primary request once it has been fully reconstructed.

[0041] According to one embodiment, the internal controller is configured to record a primary execution acknowledgment in the intermediate buffer that contained the corresponding primary request, and then to release this intermediate buffer, allowing it to be used to reconstruct another primary request, when the primary execution acknowledgment has been fully sent, via a secondary execution acknowledgment set.

[0042] According to one embodiment, the primary and secondary identifiers are used by the internal controller i to reassemble the secondary queries into a primary query in the correct order when the memory controller executes the send queries in a different order than in which it received them from the pre-controller.

[0043] According to one embodiment, the pre-controller is configured to reconstruct a primary execution acknowledgment ik by recording in a pre-register tik, as they are received, the secondary execution acknowledgments ik, or at least sufficient elements thereof; the pre-controller is also configured to transmit to the main processor the primary execution acknowledgments corresponding to primary results once these primary execution acknowledgments have been reconstructed, and to release the corresponding pre-register tik in such a way that they can be used to record new primary requests generated by the main processor.

[0044] According to one embodiment, the pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution acknowledgment corresponding to that primary write request has arrived, the register thus released becoming available to record a new primary request generated by the main processor.

[0045] According to one implementation method, the primary and secondary identifiers are used by the pre-controller to reassemble secondary execution acknowledgments into primary execution acknowledgments in the correct order when the memory controller executes response requests in a different order than it received them from the pre-controller.

[0046] According to one embodiment, at least one bus comprises a control and address bus and a data bus.

[0047] According to one embodiment, the at least one bus comprises a single bus.

[0048] The invention also relates to another computer device which comprises:

[0049] - a memory card provided with a set of n memory circuits, each called a circuit i for i from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0050] - a main processor configured to issue requests, called queries primary ik, each primary ik query targeting an address, called address ik, of one or more ranks of one or more banks of circuit i;

[0051] - a memory controller implementing an access protocol, known as a native protocol, said native protocol being configured to allow the memory controller to access the n circuits i in parallel;

[0052] - at least one bus configured to carry commands, addresses and data ;

[0053] The computer device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, called internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, each internal controller i is further configured to perform, when necessary, in place of the memory controller, the pre-loading of banks,the activation of memory locations in circuit i for the execution of the primary query ik.

[0054] According to one implementation, the pre-controller comprises a plurality of command generation units dedicated to decomposing the primary requests ik into a set of secondary requests ik; the pre-controller further comprises a command sending unit configured to send the secondary requests

[0055] According to one implementation, the pre-controller includes a buffer, called pre-controller memory, in which each primary request ik is in recorded in a register, called pre-register tik, before its processing, and in which each internal controller i includes a buffer memory called intermediate buffer i.

[0056] According to one embodiment, said computer device is configured to assign an identifier, called primary identifier, to each primary query ik, and one or more identifiers, called secondary identifiers, to each of the secondary queries of a set of secondary queries ik, the set of primary and secondary identifiers allowing each primary query ik to be associated with the set of secondary queries ik resulting from the decomposition of said primary query ik.

[0057] According to one embodiment, the pre-controller is configured to perform in parallel the decomposition of a plurality of primary requests ik each targeting a different memory circuit, the pre-controller is also configured to simultaneously issue several secondary requests, each of these secondary requests belonging to a set of secondary requests ik each targeting a different memory circuit.

[0058] It is understood that the simultaneous issuance of several secondary requests, each of these secondary requests belonging to a set of secondary requests ik, each targeting a different memory circuit, can in particular implement a send request. This send request comprises, in this respect, several secondary requests ik, each targeting a different memory circuit. This send request can be transmitted to the memory circuit via the memory controller.

[0059] According to one embodiment, the pre-controller is configured so that following the decomposition of a primary request ik into a set of secondary requests ik, said set of secondary requests ik includes secondary requests ikl for 1 ranging from 0 to m, the address ik in the circuit i targeted by the primary request ik being carried by at least one of the secondary requests ikl.

[0060] According to one implementation, when the primary request ik is a write request, the internal controller i is configured to record, as they are received, the secondary requests ikl for 1 going from 0 to m of the set of secondary requests ik in a register ik of the intermediate buffer i, the internal controller i is also configured to, when all the secondary requests ikl have been recorded in the register ik, reconstruct the primary request ik and execute said primary request ik.

[0061] According to one implementation, the pre-controller, when it receives at least two primary write requests ik and jh, j being different from i, and targeting circuit i and circuit j respectively, decomposes said primary requests ik and jh, respectively, into a set of secondary requests ik and a set of secondary requests jh, the pre-controller being configured to simultaneously send a request se A secondary request ikl, where 1 is between 0 and m, is sent to circuit i; a secondary request jht, where t is between 0 and m, is sent to circuit j; and a NOP command is sent to circuits h not targeted by a primary request. A NOP command is a command with no effect. It is understood that simultaneous sending is done via a send request as described above.

[0062] According to one implementation mode, the internal controller i is configured to issue an execution confirmation of the primary request ik to the pre-controller, and reset the intermediate buffer i register ik, the pre-controller being configured to reset the pre-register ik upon receipt of the execution confirmation.

[0063] According to one embodiment, when the primary request ik is a read request of L bytes of data at address ik, the internal controller i is configured to reassemble the primary request ik upon receipt of all the secondary requests from the secondary request set ik, and then to execute said primary request ik in order to write into a register tik of its intermediate buffer the L bytes read as a result of the execution by said internal controller i of the primary request ik.

[0064] According to one embodiment, the internal controller is also configured to decompose the L bytes read and recorded in the register tik into a secondary result set ik and communicate them to the pre-controller, said pre-controller being configured to assemble the secondary results of the secondary result set ik into a primary result ik forming both a response to the primary query ik being read and an acknowledgment of the execution of the latter.

[0065] According to one embodiment, the pre-controller, when it receives at least two primary requests ik and jh for reading, j being different from i, and targeting, respectively, circuit i and circuit j, translates said primary requests ik and jh, respectively, into a set of secondary requests ik and into a set of secondary requests jh, the pre-controller being configured to simultaneously send at least one secondary request from the set of secondary requests ik to circuit i, and at least one secondary request from the set of secondary requests jh to circuit j.

[0066] According to one embodiment, at least one bus comprises a control and address bus and a data bus.

[0067] According to one embodiment, the at least one bus comprises a single bus.

[0068] According to one implementation, the secondary queries of a query set are secondary ik transmitted by the pre-controller to a circuit i, pass through the memory controller. Brief description of the drawings

[0069] Other features and advantages of the invention will become apparent from the description The following detailed explanation will be provided with reference to the attached figures, on which:

[0070] [Fig.1] Fig.1 is a schematic representation of a computer device equipped with a memory card known from the prior art and adapted to the implementation of a standard memory protocol, in particular the memory card of this computer device includes memory circuits without an internal processor;

[0071] [Fig.2] Fig.2 is a schematic representation of a computer device equipped with a memory card and each memory circuit includes an internal processor;

[0072] [Fig. 3] Fig. 3 is a schematic representation of a computer device in accordance with the principles of the present invention, in particular the computer device shown in [Fig.3] includes, without limiting the invention to this aspect alone, four memory circuits. DETAILED DESCRIPTION OF THE INVENTION

[0073] The present invention relates to a computer device equipped with at least one memory card, and more particularly to a memory card comprising a plurality of memory circuits, each of these circuits being equipped with an internal processor. In particular, and according to the terms of the present invention, an internal processor is a microelectronic device configured to execute instructions and, for example, perform calculations, on data stored in the memory circuit to which it belongs. In this regard, those skilled in the art may refer to patent application WO 2017 / 055732 A1, which describes an example of a memory circuit equipped with an internal processor. It is understood, however, that the functionalities and architectures provided in patent application WO 2017 / 055732 A1 are given only by way of example and shall in no way limit the scope of the present invention.

[0074] The present invention proposes a memory card architecture compatible with existing protocols, and in particular DDR5 protocols, while implementing internal memory controllers, hereinafter referred to as internal controllers.

[0075] Thus, the present invention relates to a computer device comprising:

[0076] - a memory card provided with a set of n memory circuits, each called a circuit i for i from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor, each bank, among one or more banks, comprising a plurality of ranks, each rank comprising memory cells;

[0077] - a main processor configured to issue requests, called queries primary ik, each primary ik query targeting an address, called address ik, of one or more ranks of one or more banks of circuit i;

[0078] - a memory controller implementing an access protocol, called a native protocol, said native protocol being configured to allow the memory controller to access in parallel to the n circuits i;

[0079] - at least one bus configured to carry commands, addresses and data ;

[0080] The computer device further comprises a pre-controller interposed between the main processor and the memory controller, while each circuit i is provided with an internal memory controller, referred to as internal controller i, the pre-controller being configured to, upon receiving a primary request ik from the main processor, decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller, this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, referred to as primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit, via the memory controller,This set of secondary execution acknowledgments to the pre-controller, which is also configured to reconstruct the primary execution acknowledgment from the set of secondary execution acknowledgments, the pre-controller is also configured to provide the main processor with primary results ik in response to a primary data read request ik, called data ik, stored in circuit i, the primary results ik forming a primary execution acknowledgment and including the data ik; each internal controller i is further configured to also execute memory access requests, called internal requests, from the internal processor, the internal controller i is also configured to generate, for the execution of primary requests as well as internal requests, all the operations necessary to access the memory of memory circuit i, and when necessary, in place of the memory controller,preload the memory banks, activate the memory ranks, and perform memory rank refresh operations when such operations are necessary.

[0081] The native protocol, configured to allow the memory controller to access the n circuits i in parallel, implies that said native protocol allows the memory controller to execute requests, including send requests described later in this statement, by generating commands. In particular, and this will become clearer later in this statement, a send request can be formed from one or more sub-requests, each of the sub-requests of said send request targeting a different circuit i and being capable of being executed in parallel at the level of the different circuits i actually targeted. Furthermore, it is understood that a read or write command of the native protocol is addressed to all the circuits i.

[0082] Thus, according to the present invention, each memory circuit comprises an internal controller having functions equivalent to those of a memory controller. However, an internal controller only performs these functions within the memory circuit in which it is integrated.

[0083] Furthermore, and according to the present invention, each primary request issued by the main processor is allocated via the pre-controller to a single memory circuit.

[0084] Thus, a primary request allocated to a given memory circuit can be entirely processed by the internal controller of that memory circuit. This configuration makes it possible to take advantage of the computing and data processing capabilities of each memory circuit through its internal processor.

[0085] The remainder of this description of the present invention is limited to the description of a computer device and the various functionalities of its component parts. However, it is understood that the invention is not limited to the computer device alone but also relates to the process(es) implemented by the computer device in question.

[0086] Furthermore, the remainder of the statement refers to at least one bus which includes a control and address bus and a data bus. However, it is understood that at least one bus may include a single bus.

[0087] In this regard, a person skilled in the art, upon reading this statement alone, will understand that the present invention may relate to a method for routing a primary request, from its emission by the main processor to its execution at the memory circuit level by the internal controller of the memory circuit in question. It is also understood that such a method may consider both primary write requests and primary read requests. Finally, it is also understood that the invention may also relate to a computer program which, when implemented, executes all the steps of the method in question. This computer program may, in particular, include subroutines, for example, a subroutine stored and executed by the pre-controller and a subroutine stored and executed by the internal controllers.

[0088] The following description considers memory circuits equipped with internal processors. However, a person skilled in the art, upon reading this statement alone, may consider that the invention is also applicable to memory circuits lacking said internal processors.

[0089] Thus, in [Fig.3], we can see a schematic representation of a computer device 10 conforming to the principles set forth in the present invention.

[0090] In particular, the computer device 10 includes a main processor 100. The main processor 100 may include, for example, a processing unit and Control of an electronic device such as a computer, calculator, or other equipment capable of executing logical functions. In particular, the main processor 100 can be a central processing unit (CPU). In this specific case, the main processor 100 is intended to generate primary requests for memory circuits described later in this document.

[0091] In particular, primary queries may include primary write queries and / or primary read queries.

[0092] In this regard, a primary write request corresponds to the writing of data, for storage purposes, into a memory circuit, while a primary read request corresponds to the reading of data stored in a memory circuit and their communication to the main processor 100.

[0093] The computer device 10 also includes a 300 memory card. By "Memory card" refers to a support element, such as a printed circuit board, on which one or more memory circuits are arranged. A 300 memory card may include connection means allowing, in particular, interfacing the said 300 card with a computer or a processing unit.

[0094] The memory card 300 according to the present invention comprises n memory circuits, each referred to as circuit i for i ranging from 1 to n. It is understood, without needing to specify it, that n is an integer.

[0095] Each circuit i comprises one or more memory banks, each memory bank comprises a plurality of ranks, each rank comprising memory cells.

[0096] The memory cells may include dynamic random access memory (DRAM). However, the invention is not limited to this aspect alone, and those skilled in the art may consider any type of memory cell, in particular static random access memory (SRAM).

[0097] Each circuit i includes at least one internal processor.

[0098] In [Fig.3], given by way of non-limiting example, the memory card comprises four memory circuits labeled circuit 1, circuit 2, circuit 3 and circuit 4. In particular, in [Fig.3], circuit 1 bears the reference 301, circuit 2 bears the reference 302, circuit 3 bears the reference 303 and circuit 4 bears the reference 304.

[0099] As illustrated in [Fig. 3], each circuit 301, 302, 303 and 304 comprises a internal processor labeled 311, 312, 313 and 314 and one or more memory banks labeled 321, 322, 323 and 324.

[0100] Each circuit i, for i ranging from 1 to n, includes an internal memory controller, each called internal controller i. An internal controller is notably configured to to execute primary requests recomposed from secondary requests it receives via the bus(es), and also to execute requests, generated by the internal processor i, to access the memory contained in the bank(s). As illustrated in [Fig. 3], each circuit 301, 302, 303, and 304 includes an internal controller labeled 331, 332, 322, and 334.

[0101] The computer device 10 according to the present invention also includes a memory controller 200. In particular, the memory controller 200 according to the present invention incorporates the technical characteristics of memory controllers known in the prior art. Specifically, the memory controller 200 according to the present invention is configured to issue bank preload, memory row activation, and / or memory row refresh commands. However, the computer device 10 according to the present invention is configured so that certain commands that could be issued by the memory controller 200 are ignored by the memory circuits, in particular the bank preload, row activation, and row refresh commands. This latter aspect makes it possible, in particular, to limit the protocol adaptations related to the operation of the computer device 10.

[0102] The computer device 10 according to the present invention comprises a data bus 500 connecting the memory controller 200 and the memory card 300, and a control and address bus 400 connecting the memory controller 200 and the memory card 300. It is further known that each memory circuit is only partially connected to the data bus 500. More specifically, the width (for example, measured in "bits" or "bytes") of the data bus is greater than the data port width (for example, measured in "bits" or "bytes") of each of the memory circuits. Thus, according to the present invention, all the memory circuits can have the same data port width. Advantageously, the sum of the data port widths of all the memory circuits on the memory card can be equal to the data bus width.

[0103] For example, the data port of each memory circuit can be equal to p (p being an integer) while the data bus width can be equal to the product of p by n (n being the number of memory circuits carried by the memory card).

[0104] It is thus understood that a write request of a length equal to the product of n by p, or a multiple of this value, cannot pass through the data port of a memory circuit without modifications.

[0105] The computer device 10 also includes a pre-controller 600 interposed between the main processor 100 and the memory controller 200. In operation, the main processor 100 is configured to issue requests, and in particular primary requests ik for i from 1 to n, a primary request i targeting an address , The address i, of one or more ranks of one or more banks of circuit i. The first index "i", allocated to the primary request ik, designates the circuit i targeted by said request. The second index "k" (it being understood that other letters may be considered in the rest of the statement) designates the request itself and allows, in particular, differentiation between the primary request ik and the primary request ih, both of which target circuit i.

[0106] According to the present invention, the pre-controller 600 is adapted to receive and perform pre-processing of primary requests ik issued by the main processor 100. In particular, the pre-controller 600 is configured to decompose a primary request ik (for i from 1 to n), targeting an address ik of the circuit i (issued by the main processor 100), into a set of secondary requests ik.

[0107] Secondary requests are sent by encoding them in write requests, also called send requests. In particular, several secondary requests, destined for different memory circuits i, can be encoded in a single send request. The send requests are transmitted to the memory controller 200, which executes each send request by generating a sequence of commands on the control and address bus 400 and by transmitting data on the data bus 500.

[0108] In this respect, the command sequence comprises:

[0109] - possibly a bench preload control as well as a control rank activation, (however, each internal controller is configured to ignore these two commands.)

[0110] - one or more write commands, these commands carrying, on the bus of 500 data, data which are normally, in the DDR5 protocol, the data to be written, but which in the context of the invention are data encoding secondary requests.

[0111] Each internal controller i is further configured to extract secondary queries from the write command data generated by the memory controller when the latter executes send queries. The internal controller i reconstructs primary queries from the sets of secondary queries thus extracted, and executes the primary queries once they are reconstructed, performing bank preloads and rank activations as necessary, as well as refresh operations when required.

[0112] For each primary query executed, the internal controller i will generate an execution confirmation, the latter corresponding for a primary read query, to the data read by that primary read query, and for primary write queries, to a secondary query identifier.

[0113] Each time the internal controller i receives a response command, the Internal controller i provides: - either a secondary result, that is to say a part of a confirmation of execution of a primary read query, this secondary result including a secondary identifier as well as a part of the data read following this primary read query; - either one or more confirmations of execution of primary writing queries; - either a value encoding the absence of execution confirmation, the controller having either already fully confirmed all the primary queries it has already executed, or not yet being able to confirm the execution of primary queries in one or the other of the following cases: • He has not yet received confirmation of full execution • it has not yet executed a primary request in its entirety

[0114] According to a particularly advantageous embodiment, the 600 pre-controller may include n command generation units, each called generation unit i for i ranging from 1 to n. Each generation unit i is specifically dedicated to decomposing a primary request ik targeting circuit i into a set of secondary requests ik. Also according to this embodiment, the 600 pre-controller may include a send request generation unit configured to encode several secondary requests in each send request, these secondary requests having been generated by different generation units i, thus targeting different memory circuits.The resulting send requests are provided to memory controller 200, which executes them by controlling buses 400 and 500; Pre-controller 600 will then send, via memory controller 200, the secondary requests of each set of secondary requests ik to the memory circuit i, and therefore to the internal controllers i.

[0115] Advantageously, the pre-controller 600 may include a buffer, called the pre-controller memory, in which each primary request ik is recorded in a register, called the pre-register tik, before being processed. Advantageously, each internal controller i may also include a buffer, called the intermediate buffer i, for i from 1 to n.

[0116] In particular, and by way of example, the tik pre-register in which the primary query ik is recorded may include a plurality of fields among which one may count, an identifier, a state of the allocated buffer, the address ik, a data table.

[0117] The state of the allocated buffer may include a free state, a state in which a primary read request is logged, and a state in which a primary write request is logged. The state in which a primary read request ik is logged may be a measure of the progress of sending the query set se secondary requests ik (decomposition of the primary read request) to circuit i. Equivalently, the state for which a primary write request ik is recorded can be a measure of the progress of sending the set of secondary requests ik (decomposition of the primary write request) to circuit i.

[0118] The computer device 10 can be configured to assign an identifier, called the primary identifier, to each primary query ik, and one or more identifiers, called secondary identifiers, to each of the secondary queries in a set of secondary queries ik. The set of primary and secondary identifiers allows, in particular, each primary query ik to be associated with the set of secondary queries ik resulting from the decomposition of said primary query ik. In other words, the secondary identifiers assigned to the secondary queries in a given set of secondary queries allow the primary query to be associated with the set of secondary queries formed from the primary query in question.

[0119] This last aspect also makes it possible to associate in return a primary execution confirmation ik with the set of secondary execution confirmations ik resulting from the decomposition of said primary execution confirmation.

[0120] According to an advantageous embodiment, the pre-controller 600 can be configured to perform in parallel the decomposition of a plurality of primary requests ik, each targeting a different memory circuit i. Also according to this embodiment, the pre-controller 600 can be configured to encode several secondary requests in a single send request, each of these secondary requests belonging to a set of secondary requests ik, each targeting a different memory circuit i.

[0121] The pre-controller 600 can be configured so that following the decomposition of a primary request ik into a set of secondary requests ik, said set of secondary requests ik includes secondary requests ikl for 1 ranging from 0 to m, the secondary request ikO carrying the address ik in the circuit i targeted by the primary request ik.

[0122] The computer device 10 also includes a data bus 500 connecting the memory controller and the memory card, and a control and address bus 400 connecting the memory controller and the memory card.

[0123] The control and address bus 400 is a unidirectional bus which, via appropriate encoding, carries control information and address information. It is understood that control information indicates an action to be performed, for example, executing a request, while address information indicates an address within a circuit i where the request in question is to be executed.

[0124] The 500 data bus is a bidirectional bus which includes several data communication fields i, and more particularly n data communication fields i (i ranging from 1 to n), each data communication field i being dedicated to circuit i.

[0125] It is understood that the data communicated between a circuit i and the pre-controller 600 pass through the data communication field i.

[0126] Secondary ikl requests in writing or reading carrying requests, respectively, for writing and reading, can also pass through the data communication field i.

[0127] Secondary requests ikO in writing or reading carrying an address, respectively, of writing and reading, can also pass through the data communication field i or through the address communication field ik, or in a distributed manner over these two fields.

[0128] The internal controller i is configured to record, as they are received, the secondary queries ikl from the secondary query set ik in a register tik of the intermediate buffer i. The internal controller i is also configured to, once all the secondary queries ikl have been recorded in the register tik, reconstruct the primary query ik and execute said primary query ik. By executing the primary query ik, we mean, for all ranks targeted by the query where it would be necessary, a preloading of the bank where the rank in question is located and the activation of that rank, and then, for all ranks targeted by the query, the reading or writing of the cells of the rank specified by the query address.

[0129] Advantageously, the pre-register tik allocated to the primary request ik in the pre-controller memory will report the progress of sending the secondary requests ikl to the internal controller i. The internal controller i also allocates a register tik in its intermediate buffer i to the set of secondary requests ik. In particular, this register tik reports the progress in terms of receiving the secondary requests ikl of the secondary request set.

[0130] The internal controller is also configured to record a primary execution acknowledgment in the intermediate buffer that contained the corresponding primary request, and then release that intermediate buffer. This latter aspect allows said intermediate buffer (in other words, the register in question) to be used to reconstruct another primary request, once the primary execution acknowledgment has been fully sent, via a secondary execution acknowledgment set.

[0131] According to the present invention, the primary and secondary identifiers can also be used by the internal controller i to reassemble the secondary requests into primary requests in the correct order when the memory controller executes the send requests in a different order than in which it received them from the pre-controller.

[0132] According to the present invention, the primary and secondary identifiers can be used by the pre-controller to reassemble the secondary execution acknowledgments become primary execution acknowledgments when the memory controller executes response requests in a different order than in which it received them from the pre-controller.

[0133] The pre-controller is configured to reconstruct a primary execution acknowledgment ik by recording secondary execution acknowledgments ik, or at least sufficient elements thereof, in a pre-register tik as they are received. The pre-controller is also configured to transmit to the main processor the primary execution acknowledgments corresponding to primary results once these primary execution acknowledgments have been reconstructed, and to release the corresponding pre-registers tik so that they can be used to record new primary requests generated by the main processor.

[0134] The pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution acknowledgment corresponding to that primary write request has arrived, the pre-register thus released becoming available to record a new primary request generated by the main processor.

[0135] A person skilled in the art, on the basis of their general knowledge alone, will be able to design the architecture of the tik pre-register and the tik register.

[0136] Each internal controller i can be configured to, upon receiving all the secondary requests from the secondary request set ik, reassemble said secondary requests in order to reform the primary request and execute the latter.

[0137] The internal controller i is also configured to decompose the data read and recorded in the register tik into a secondary result set ik and communicate them to the pre-controller, in response to response requests issued by the latter, said pre-controller being configured to extract, from the data returned by the response requests (which are read requests from the point of view of the DDR5 protocol), the secondary results of the secondary result set ik, and reassemble these secondary results into a primary result ik forming both a response to the primary read request ik and an acknowledgment of the execution of the latter.

[0138] Advantageously, the pre-controller, 600, when it receives at least two primary read requests ik and jh, j being different from i, and targeting, respectively, circuit i and circuit j, translates said primary requests ik and jh, respectively, into a set of secondary requests ik and into a set of secondary requests jh, the pre-controller being configured to simultaneously send a secondary request ikl to circuit i, a secondary request jht to circuit j. The pre-controller is configured, once it has written all the data (in particular the read data) to the pre-register, to send said data to the main processor.

[0139] The computer device 10 is therefore configured to process a plurality of primary requests, each of the primary requests targeting a different memory circuit.

[0140] Thus, and according to the present invention, the consideration of secondary queries (of reduced size compared to primary queries), or of secondary results makes it possible to execute a primary query entirely within a single circuit and consequently to be able to benefit from the full potential offered by the presence of an internal processor in the memory circuit considered.

[0141] The remainder of the statement deals with the path of a primary write request within a computer device in which the memory card comprises four memory circuits. In this example, the data bus 500 is 32 bits, distributed equally across each of the circuits 301, 302, 303, and 304.

[0142] The path of a primary write request includes the generation of said primary request by the main processor. This primary request may include, in particular, a request identifier, a destination address i aligned with 64 bytes of circuit i, and 64 bytes of data to be written, called data i, to address i.

[0143] Upon receipt of the primary request, the pre-controller 600 allocates to said primary request i a pre-register tik in its buffer memory.

[0144] The 600 pre-controller then translates the primary request ik into five secondary requests ik, for k ranging from 0 to 4. The 600 pre-controller can be equipped with four command generation units, each dedicated to translating the primary requests targeting its own memory circuit. In other words, the primary request ik, targeting circuit i, will be translated into five secondary requests ikl (1 ranging from 0 to 4) by the command generation unit dedicated to circuit i. The address ik targeted in circuit i is contained in the secondary request i0 along with a small portion of the data to be written, while the secondary requests ik, for k ranging from 1 to 4, include the remainder of the data to be written.

[0145] These different secondary requests ik (k ranging from 0 to 4) are sent by the command sending unit via 5 secondary write requests.

[0146] Secondary requests to different memory circuits can be sent simultaneously. In particular, once it is considered, the command sending unit can send four secondary requests from four different sets of secondary requests. In other words, write commands to the four memory circuits can be implemented at the same time.

[0147] Thus, the execution of the primary write request of the main processor will require five write accesses instead of 1, but up to 4 write requests of the main processor, each targeting different memory circuits, can be carried out in parallel, achieving, from the point of view of bandwidth, an efficiency of 80%.

[0148] When internal controller i receives the secondary request i0 and the secondary requests ik for k from 1 to 4, it updates the register tik. Once the state of the register tik reaches the value indicating that all the secondary requests ikl (for 1 from 0 to 4) have been received by internal controller i, the 64 bytes of data i are written to the address ik targeted by the primary request ik in circuit i.

[0149] The pre-controller, determining that an execution confirmation must be pending in memory circuit i, for example, not limiting because sufficient time has elapsed since the sending of the last secondary request in the set of secondary requests corresponding to the primary write request under consideration, will issue a response command. Internal controller i will then issue an execution confirmation for writing data i in response to this response command and reset the tik register. If the internal controller is not ready to provide this execution confirmation upon receiving the response command, said internal controller provides a non-response value and will provide this execution confirmation in response to a subsequent response command. The pre-controller, upon receiving a non-response, generates another response request, which, once executed by the memory controller, generates yet another response command.

[0150] In the end, the execution confirmation is received by the pre-controller (via the memory controller) which in turn resets the tik pre-register, the latter being able to be allocated to the execution of another primary request.

[0151] The remainder of the statement deals with the path of a primary read request within a computer device in which the memory card comprises four memory circuits. In this example, the data bus 500 is 32 bits distributed equally across each of the circuits 301, 302, 303 and 304.

[0152] The path of a primary read request includes the generation of said primary request by the main processor. This primary request may include, in particular, a request identifier, a 64-byte aligned destination address ik of circuit i.

[0153] Upon receipt of the primary request, the pre-controller 600 allocates to said primary request ik a pre-register tik in its buffer memory.

[0154] The destination address i is used to determine the memory circuit i involved in the primary read request. In this particular case, the destination address ik could, for example, be circuit 302. The pre-controller then generates the set of secondary requests ik, for example, using a command generation unit dedicated to circuit i.

[0155] In this case, since it is a read request, the secondary request set ik includes a single secondary request iO which is sent to circuit 302 via the data bus, and in particular the data communication field associated with circuit 302. The secondary request iO includes the read address ik in circuit 302.

[0156] The internal controller i of circuit 302, when it receives the secondary request iO, updates the tik register, and executes the corresponding read command as soon as possible, filling the tik register with the read data.

[0157] The pre-controller, determining that a read execution confirmation must be pending in the memory circuit i, for example non-limiting because sufficient time has elapsed since the sending of the secondary request iO corresponding to the primary read request under consideration, will issue a series of response commands in order to retrieve the set of secondary execution confirmations containing the read data.

[0158] The internal controller i then issues this secondary execution acknowledgment set, in fact the secondary result set, in response to this series of response commands, thereby transferring the read data, and resets the tik register.

[0159] As with a write command, the internal controller has the option, when it is not ready at the time it receives a response command, to provide a non-response value to a response command, the latter being reissued later in a manner similar to that described in the path of a write request.

[0160] Data passing through bus 500 is transported via data blocks ("DATA BURST" according to Anglo-Saxon terminology), a data block typically comprising 64 bytes.

[0161] Secondary results ik, emitted by circuit i, are received by the pre-controller 600. These can be of a compact size of 8 bytes, for example (equal to half the number of bytes belonging to a data block passing through a data communication field), or of a normal size of 16 bytes, for example (equal to the number of bytes belonging to a data block passing through a data communication field). Typically, the data can thus be communicated to the pre-controller 600 in the form of one secondary result of compact size and four secondary results of normal size, each secondary result comprising, in addition to the data it carries, an identifier, for example, an identifier relating to the pre-register tik in which the primary request i is stored.

[0162] For example, and without limitation, the internal controller i encodes the type of response it provides to a response command in a 4-bit field placed at the beginning of the response. This 4-bit field encodes, in particular, the following types: a no-response type, a write acknowledgment type, a compact result type, and a normal result type.

[0163] The non-response, write confirmation and compact result types fit on 8 bytes while the normal result type fits on 16 bytes.

[0164] Consequently, the 16 bytes provided by the internal controller i in response to a response command may comprise one of the following combinations: - two non-responses; - a non-response and a confirmation of writing; - a non-response and a compact result; - two confirmations of writing; - a writing confirmation and a compact result - two compact results - a normal result

[0165] Still within the framework of the non-limiting example, a compact result also includes an 8-bit identifier and 6 bytes of data and a normal result also includes an 8-bit identifier and 14.5 bytes of data: 1 compact result (6 bytes) and 4 normal results (4 x 14.5 bytes) carrying a total of 64 bytes of data.

[0166] Once all the results i (all the data to be read) are received by the pre-controller 600, the latter assembles them to transmit them to the main processor 100. The assembled data may be accompanied by the identifier of the primary request i.

[0167] It is understood that a compact size (in bytes) corresponds to half the amount of data passing through the data port of a memory circuit during a read or write command, while a normal size (in bytes) corresponds to the entire amount of this data.

[0168] The consideration of compact sizes makes it possible to group and send two compact-sized results simultaneously in response to a single response command, said two compact-sized results corresponding to different read requests. This aspect allows for an improvement.

[0169] Equivalently, secondary read requests iO, which only have one address to carry, can be of compact size, so that sending two such requests, corresponding to different primary read requests, can be sent simultaneously to memory circuit i, via a single send command.

[0170] Thus, in the present case, the implementation of a primary read query will involve: • the sending of a compact secondary request (8 bytes) • the output of a compact secondary result (8 bytes) • the transmission of 4 normal-sized secondary results (16 bytes each)

[0171] These transmissions together therefore correspond to the equivalent of 5 commands on the bus (one half-command + one half-command + 4 commands). The computer system is thus able to parallelize up to 4 commands as long as they concern different memory circuits, thereby achieving a bandwidth efficiency of 80% (4 accesses in 5 commands).

[0172] The examples of the path of a primary write request or a read request given above can be generalized to any number of memory circuits. Furthermore, throughout this description, the number of secondary requests ik has been a function of the nature of the primary request (read or write) as well as the number of memory circuits included in the computer system. However, those skilled in the art will understand that this aspect should not be considered a limiting factor. Indeed, the principles of the invention described above took into account the width of the address and control bus, and the width of the data bus. These widths are not fixed, however, so a different number of secondary requests can be considered.

[0173] The computer device 10 can also be configured to handle read errors when executing a primary read query.

[0174] In the example described above, the data bus is only 32-bit wide and is not protected against errors that may transiently affect it.

[0175] Thus, it may be advantageous to implement an optional Cyclical Redundancy Check (CRC) mechanism as specified by the DDR5 protocol. Each circuit i provides, in addition to the 16 response bytes, 2 additional bytes, containing 2 8-bit CRCs, each CRC being generated from half of the 16 response bytes, such that the 2 CRCs protect all 16 bytes of the response of each circuit i.

[0176] If a transmission error occurs, for example a temporary inversion of a signal on the data bus linking the memory controller to circuit i: - the memory controller will detect this error, because one of the two CRCs associated with the 16 bytes emitted by circuit i is incorrect; Although only 8 bytes of data are affected, the memory controller, for the sake of simplicity, will reject all 64 bytes of data returned in response to its read request. - the memory controller will re-emit the said read command

[0177] However, the internal operation of the memory controller may cause this read request not to be immediately reissued, and other read or write requests to be issued in the meantime.

[0178] The problem is that a read request, therefore a response request, modifies the state of the internal controller: the latter, when it chooses a response to send, also modifies its own internal state, in particular the state of the tik register of the buffer concerned, so that it no longer chooses this response when it receives other response commands.

[0179] Each of the secondary results to a read secondary query identifies the of destination of the data bytes it contains. A read error between the memory circuit and the memory controller affecting a secondary result: - does not mean that bytes intended for primary read requests ik / jl / kv / lw are mistakenly assigned to other primary read requests ia / jb / kc / ld. - but this means that bytes intended for primary queries ik / jl / kv / lw are lost and will not arrive.

[0180] Thus, the pre-controller, noting after a sufficiently long time that all the bytes expected by the primary requests ik / jl / kv / lw have not arrived, will consider that they have been lost and proceeds as follows and in order: - The pre-controller issues commands to cancel the primary requests ik / jl / kv / lw - The pre-controller awaits confirmation of the execution of the cancellation commands for the primary queries ik / jl / kv / lw - The pre-controller reissues a primary request cancellation command (ik / jl / kv / lw) if the execution confirmation takes too long to arrive. - finally, the pre-controller completely restarts the process of executing the primary queries ik / jl / kv / lw.

[0181] The computer device 10 can also be configured to handle write errors when executing a primary write query.

[0182] When the memory controller issues a primary write request, it generates CRC bytes in the same way as memory circuits 301, 302, 303, 304 when they respond to a primary read request.

[0183] If a transmission error occurs, for example a temporary inversion of a signal on the data bus linking the memory controller to circuit i: - The memory controller will detect this error because one of the two CRCs associated with the 16 bytes emitted by circuit i is incorrect. Circuit i ignores the command carried by the secondary write request; this command could originally be a read address command, a data write command, a cancellation command, or a command without instructions. - some of the bytes, intended for the primary request i, are lost and will not arrive: • Access, whether for reading, writing, or cancellation, will never occur. • The pre-controller, observing after a sufficiently long time that the primary request i has still not been executed, will consider that some of the bytes that constitute it have been lost and will proceed as follows and in order: • The pre-controller issues a command to cancel the primary request i • The pre-controller awaits confirmation of the execution of the primary request cancellation command i • The pre-controller reissues a primary request cancellation command i if this execution confirmation takes too long to arrive. • the pre-controller restarts the entire execution process of the primary query i.

[0184] Alternatively, the memory circuit could explicitly indicate that a transmission error has been encountered via a response of a specific type.

[0185] Of course, the invention is not limited to the embodiments described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

1. Demands Computer device (10) which includes: - a memory card (300) provided with a set of n memory circuits (301, 302, 303, 304) each called circuit i for i from 1 to n, each circuit i comprising one or more memory banks and at least one internal processor (311, 312, 313, 314), each bank, among one or more banks, comprising a plurality of ranks, each rank comprising memory cells; - a main processor (100) configured to issue requests, called primary requests ik, each primary request ik targeting an address, called address ik, of one or more ranks of one or more banks of circuit i; - a memory controller (200) implementing an access protocol, called the native protocol, said native protocol being configured to allow the memory controller (200) to access the n circuits i in parallel; - at least one bus (400, 500) configured to carry commands, addresses and data; The computer device (10) further includes a pre-controller (600) interposed between the main processor (100) and the memory controller (200), while each circuit i is provided with an internal memory controller (331, 332, 333, 334), called internal controller i, the pre-controller (600) being configured to, upon receiving a primary request ik from the main processor (100), decompose said primary request ik into a set of secondary requests ik, and send, via the memory controller (200), this set of secondary requests to the memory circuit i, each internal controller i being configured to reconstruct the primary request ik from the set of secondary requests ik, execute said primary request ik, generate in return an execution confirmation, called primary execution confirmation, decompose said primary execution confirmation into a set of secondary execution confirmations, and transmit, via the memory controller (200),This set of secondary execution acknowledgments to the precontroller, which is also configured to reconstruct the primary execution acknowledgment from the set of secondary execution acknowledgments, the precontroller is also configured to provide the main processor (100) with primary results ik in response to a primary data read request ik, called data ik, stored, in circuit i, the primary results ik form a primary execution confirmation and include the data ik; each internal controller i is further configured to also execute memory access requests, called internal requests, from the internal processor (311, 312, 313, 314), the internal controller i is also configured to generate, for the execution of primary requests as well as internal requests, all the operations necessary to access the memory of memory circuit i, and when necessary, in place of the memory controller (200), preload the banks, activate the memory ranks as well as the memory rank refresh operations when such operations are necessary.

2. Computer device (10) according to claim 1, wherein the primary execution confirmation of a primary read request ik includes the data read by the corresponding read operation.

3. A computer device (10) according to claim 1 or 2, wherein the pre-controller is configured to encode each secondary request of a set of secondary requests ik into a send request, a send request being able to include up to n secondary requests each targeting a different circuit i, the pre-controller is also configured to send each send request to the memory controller (200), the memory controller (200) is for its part configured to generate a sequence of commands of its native protocol, said sequence of commands enabling the execution of the send request, the sequence of commands comprising at least one command, said send command, for writing memory of the native protocol.

4. Computer device (10) according to claim 3, wherein the internal controller of a circuit i is configured to extract secondary requests from the send commands it receives and targeting the circuit i under consideration.

5. A computer device (10) according to claim 3 or 4, wherein the pre-controller is configured so that, when it expects, in response to send commands it has previously sent, that execution acknowledgments are pending in one or more circuits i, it generates read requests, called response requests, and transmits them to the memory controller (200), so that the latter executes them by generating sequences of native protocol commands on the bus(es) connecting the memory controller (200) to the circuits i, this sequence commands comprising at least one command, called a response command, each response command being a memory read command of the native protocol.

6. Computer device (10) according to claim 5, wherein the internal controller i is configured to encode secondary execution acknowledgments in the responses it provides to native protocol read commands, and because a response to a read command consists of the responses generated by the plurality of circuits i, such a response is likely to include several secondary execution acknowledgments issued by different circuits i.

7. Computer device (10) according to claim 6, wherein the send requests have the same format and encoding as primary write requests.

8. Computer device (10) according to claim 7, the response requests have the same format and encoding as primary read requests.

9. Computer device (10) according to claim 8, wherein a secondary request targeting circuit i is encoded in the data to be written intended for circuit i, of a send request, this data to be written being subsequently conveyed by at least one send command.

10. Computer device (10) according to claim 9, wherein the precontroller includes a buffer memory, called precontroller memory, in which each primary request ik is recorded in a register, called pre-register tik, before processing, and in which each internal controller i includes a buffer memory called intermediate buffer i.

11. Computer device (10) according to claim 10, wherein said computer device (10) is configured to assign an identifier, called primary identifier, to each primary request ik, and one or more identifiers, called secondary identifiers, to each of the secondary requests in a set of secondary requests ik, the set of primary and secondary identifiers enabling each primary request ik to be associated with the set of secondary requests ik resulting from the decomposition of said primary request ik and to be associated in return with a primary execution confirmation ik with the set of secondary execution confirmation ik resulting from the decomposition of said primary execution confirmation.

12. Computer device (10) according to claim 11, wherein the The internal controller is configured to reconstruct a primary query ik by storing secondary queries ik in an intermediate buffer as they are received, the internal controller also being configured to execute a primary query once it has been fully reconstructed.

13. Computer device (10) according to claim 12, wherein the internal controller is configured to record a primary execution acknowledgment in the intermediate buffer that contained the corresponding primary request, and then to release this intermediate buffer.

14. Computer device (10) according to claim 13, wherein the primary and secondary identifiers are used by the internal controller i to reassemble the secondary requests into primary requests in the correct order when the memory controller (200) executes the send requests in a different order than in which it received them from the pre-controller.

15. Computer device (10) according to claim 14, wherein the pre-controller is configured to reconstruct a primary execution acknowledgment ik by recording secondary execution acknowledgments ik in a pre-register tik as they are received; the pre-controller also being configured to transmit to the main processor (100) the primary execution acknowledgments corresponding to primary results once these primary execution acknowledgments have been reconstructed, and to release the corresponding pre-register tik in such a way that they can be used to record new primary requests generated by the main processor (100).

16. Computer device (10) according to claim 15, wherein the pre-controller is configured to release a tik pre-register containing a primary write request when the primary execution acknowledgment corresponding to that primary write request has arrived.

17. Computer device (10) according to claim 16, wherein the primary and secondary identifiers are used by the pre-controller to reassemble in the correct order the secondary execution acknowledgments into primary execution acknowledgments when the memory controller executes the response requests in a different order than in which it received them from the pre-controller.

18. Computer device (10) according to any one of claims 3 to 17, in in which the internal controller of circuit i is configured to ignore, in a series of commands issued by the memory controller (200), the commands of the native protocol responsible for preloading one or more memory banks and those responsible for activating one or more memory ranks.

19. Computer device (10) according to any one of claims 3 to 18, wherein the internal controller of circuit i is configured to ignore native protocol commands, issued by the memory controller (200), in charge of refreshing one or more memory ranks.

20. Computer device (10) according to any one of claims 1 to 19, wherein at least one bus comprises a control and address bus and a data bus.

21. Computer device (10) according to any one of claims 1 to 19, wherein the at least one bus comprises a single bus.

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