Optoelectronic device

Abstract

Optoelectronic Device The present description relates to an optoelectronic device (10) comprising a plurality of avalanche diodes (12) formed in a substrate (14), each diode comprising in the substrate: a. a first region (22) doped with a first conductivity type, flush with a first face of the substrate, and b. a second region (24) doped with a second conductivity type, the second region extending from the first region to a second face of the substrate, in which the second region comprises: - a first zone flush with the second face of the substrate, - a second zone in contact with the first region, and in which the device comprises, on the side of the second face of the substrate, a common electrode comprising a metallic element in contact with at least part of the flanks of the first zones of the diodes, and in which the first zone is more heavily doped than the second zone. Figure for abstract: Fig. 1

Description

Title of the invention: Optoelectronic device Technical field

[0001] The present description relates generally to optoelectronic devices and more particularly to optoelectronic devices comprising a plurality of pixels each comprising a single photon avalanche diode, also called SPAD, from the English "Single Photon Avalanche Diode". Prior art

[0002] A SPAD photodiode is essentially constituted by a PN junction reverse-biased at a voltage higher than its avalanche threshold. When no electrical charge is present in the depletion zone or space charge zone of the PN junction, the photodiode is in a pseudo-stable, non-conducting state. When a photogenerated electrical charge is injected into the depletion zone, if the speed of movement of this charge in the depletion zone is sufficiently high, that is to say if the electric field in the depletion zone is sufficiently intense, the photodiode is likely to enter an avalanche. A single photon is thus capable of generating a measurable electrical signal, and this with a very short response time. SPAD photodiodes make it possible to detect radiation of very low light intensity and are notably used for the detection of single photons and photon counting.

[0003] We are interested here in the production of an image sensor comprising a plurality of pixels each comprising a SPAD photodiode. Summary of the invention

[0004] One embodiment overcomes all or part of the drawbacks of devices comprising known SPADs.

[0005] One embodiment provides an optoelectronic device comprising a plurality of avalanche diodes formed in a semiconductor substrate, each diode comprising in the substrate: a first doped region of a first conductivity type, flush with a first face of the semiconductor substrate, and a second region doped with a second conductivity type opposite to the first conductivity type, the second region extending into the semiconductor substrate from the first region to a second face of the semiconductor substrate, opposite the first face of the semiconductor substrate, wherein the second region comprises: - a first zone flush with the second face of the semiconductor substrate, - a second zone in contact with the first region, and - a third zone extending between the first and second zones, in which the device comprises, on the side of the second face of the substrate, a common electrode comprising a metallic element in contact with at least part of the sides of the first zones of the diodes, and wherein the first zone is more heavily doped than the second zone of the second region.

[0006] According to one embodiment, the metal element is made of aluminum.

[0007] According to one embodiment, the metallic element is formed in the extension of isolation trenches separating the avalanche diodes from each other.

[0008] According to one embodiment, the insulation trenches comprise an electrically conductive core surrounded by an electrically insulating sheath.

[0009] According to one embodiment, the insulation trenches are all extended by the metal element.

[0010] According to one embodiment, only a portion of the insulation trenches is extended by the metal element.

[0011] According to one embodiment, the metallic element is continuous.

[0012] According to one embodiment, the metallic element comprises several parts disjointed.

[0013] According to one embodiment, the different parts of the metallic element are electrically connected to each other by conductive elements.

[0014] According to one embodiment, the conductive elements are opaque.

[0015] Another embodiment provides a time-of-flight measuring sensor. comprising the optoelectronic device described above.

[0016] Another embodiment provides a method of manufacturing an optoelectronic device comprising a plurality of avalanche diodes formed in a semiconductor substrate, each diode comprising in the substrate: a first doped region of a first conductivity type, flush with a first face of the semiconductor substrate, and a second region doped with a second conductivity type opposite to the first conductivity type, the second region extending into the semiconductor substrate from the first region to a second face of the semiconductor substrate, opposite the first face of the semiconductor substrate, wherein the second region comprises: - a first zone flush with the second face of the semiconductor substrate, - a second zone in contact with the first region, and - a third zone extending between the first and second zones, the method comprising forming, on the side of the second face of the substrate, a common electrode comprising a metallic element in contact with at least part of the sides of the first zones of the diodes, and wherein the first zone is more heavily doped than the second zone of the second region.

[0017] According to one embodiment, the formation of the metallic element comprises the following successive steps: a) the formation of an isolation trench in the conductive substrate, over the entire thickness of the semiconductor substrate by the second face of the substrate; b) etching an upper part of the isolation trench on the side of the second face of the semiconductor substrate, so as to form an opening and reveal part of the sides of the semiconductor substrate; and c) the deposition of a metallic layer in the previously formed opening.

[0018] According to one embodiment, the method comprises: - between steps a) and b), a step c) of depositing a transparent layer on the side of the second face of the semiconductor substrate, the etching of step b) comprising the etching of the transparent layer, and - after step c), a step of forming conductive elements on and in contact with the metal layer.

[0019] According to one embodiment, the method comprises, after step c), a step of depositing a transparent layer on the side of the second face of the semiconductor substrate and a step of forming conductive elements on and in contact with the transparent layer. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] is a partial and schematic sectional view of an example of an optoelectronic device comprising SPADs according to one embodiment;

[0022] [Fig.2] is another partial and schematic sectional view of the optoelectronic device of [Fig.l];

[0023] [Fig.3A] is a partial and schematic view of an example of the optoelectronic device of FIGS. 1 and 2 according to a first embodiment;

[0024] [Fig.3B] is a partial and schematic view of an example of the optoelectronic device of figures 1 and 2 according to a second embodiment;

[0025] [Fig.3C] is a partial and schematic view of an example of the optoelectronic device of figures 1 and 2 according to a third embodiment;

[0026] [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F], [Fig.4G] and [Fig.4H] ​​are sectional views illustrating steps of an example of a method of forming the device of Figures 1 and 2; and

[0027] [Fig.5A], [Fig.5B], [Fig.5C], [Fig.5D] and [Fig.5E], are sectional views illustrating steps of another example of a method of forming the device of Figures 1 and 2. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the production of the pixel control circuits of the devices described has not been detailed.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0033] [Fig.l] is a partial and schematic sectional view of an optoelectronic device 10 comprising SPADs 12 according to one embodiment. The device 10 is for example an image sensor.

[0034] The device 10 comprises for example a plurality of pixels P, for example arranged in a matrix. By way of example, each pixel P comprises a single SPAD 12. In [Fig.l], three pixels P are represented, two of which are only partially represented. By way of example, within the matrix, the repetition pitch of the SPADs 12 is less than 5 pm, for example less than 3 pm.

[0035] The SPADs 12 are formed in a semiconductor substrate 14. The semiconductor substrate 14 comprises a front face 14f, the upper face in the orientation of [Fig.l]. The semiconductor substrate 14 comprises a rear face 14b, opposite the front face 14f, the lower face in the orientation of [Fig.l]. In this example, the substrate 14 is intended to be illuminated by its rear face 14b.

[0036] Each SPAD 12 is for example separated from the neighboring SPADs 12 by isolation trenches 16 extending from the front face 14f of the substrate 14 in the thickness of the semiconductor substrate 14. The isolation trenches 16 form for example a grid making it possible to laterally isolate each SPAD 12. Each SPAD 12 is for example entirely surrounded laterally and separated from the neighboring SPADs 12 by the isolation trenches 16. The isolation trenches 16 make it possible for example to electrically and optically isolate each SPAD 12 from the neighboring SPADs 12. For example, the isolation trenches 16 open onto the rear face 14b of the substrate 14. The semiconductor substrate 14 is for example made of silicon. The substrate 14 has, for example, a thickness of between 1 μm and 20 μm, for example of between 5 and 15 μm, for example of the order of 10 μm.

[0037] The insulation trenches 16 comprise, for example, a core 18 surrounded by a sheath 20. The core 18 is preferably entirely surrounded laterally by the sheath 20. The side walls of the core 18 are preferably entirely covered by the sheath 20. By way of example, the upper face of the core 18 and the upper face of the sheath 20 open onto the upper face of the substrate 14.

[0038] For example, the core 18 is made of an electrically conductive material, for example metallic. Preferably, the core 18 is made of an opaque material. The core 18 is for example made of aluminum.

[0039] The sheath 20 makes it possible, for example, to provide electrical insulation for the SPADs 12. The sheath 20 is, for example, made of a dielectric material. The sheath 20 comprises, for example, an oxide having a high dielectric permittivity. For example, the sheath 20 is made of alumina (A12O3) and / or silicon dioxide (SiO2) and / or hafnium oxide (HfO2).

[0040] The SPAD 12 comprises a first region 22 of the substrate 14, flush with the front face 14f of the substrate 14. The first region 22 is doped with a first conductivity type, for example of the N type. For example, each SPAD 12 comprises a single first region 22. The first region 22 extends for example in the substrate 14 over a thickness of between 200 nm and 800 nm, for example of the order of 500 nm. For example, the first region 22 is substantially round in top view. Alternatively, the first region 22 may be substantially square in top view. The first region 22 extends for example in top view over a surface smaller than the surface of the SPAD 12 so that the first region 22 is not in contact with the isolation trenches 16. The first region 22 is for example very heavily doped. The first region 22 has for example a dopant concentration of between 1019 atoms / cm3 and 1020 atoms / cm3.

[0041] The SPAD 12 further comprises a second region 24 of the substrate 14, extending in the substrate 14 from the front face 14f of the substrate to its rear face 14b. More precisely, the second region 24 extends from the lower face of the first region 22 to the rear face 14b of the substrate 14 and also around the first region 22 at the front face 14f of the substrate 14, flush with the front face 14f of the substrate 14. The second region 24 is doped with a second conductivity type opposite to the first conductivity type, for example P type.

[0042] The second region 24 comprises a first zone 24a flush with the rear face 14b of the substrate 14. The first zone 24a extends, for example, in top view, over the entire surface of the SPAD 12. For example, the first zone 24a is in contact via its lateral flanks with the lateral flanks of the isolation trenches 16 surrounding it. The first zone 24a has, for example, a gradual dopant concentration which increases near the rear face 14b of the substrate 14. In other words, the first zone 24a is more heavily doped on the side of its lower face than on the side of its upper face. The first zone 24a is, for example, very heavily doped. The first zone 24a has, for example, a dopant concentration in the vicinity of its lower face substantially equal to the dopant concentration of the first region 22.The first zone 24a has, for example, in the vicinity of its lower face, a dopant concentration of between 1018 atoms / cm3 and 1020 atoms / cm3.

[0043] The second region 24 further comprises a second zone 24b in contact with the first region 22. The second zone 24b extends for example in the substrate 14 from the front face 14f of the substrate 14 to an intermediate level located under the lower face of the first region 22. The second zone 24b extends for example around the first region 22, that is to say in the second region 24 between the first region 22 and the isolation trenches 16 in the second region 24. The second zone 24b further extends under the first region 22 between the lower face of the first region 22 and the intermediate level of the substrate 14. By way of example, the side walls of the first region 22 and the bottom of the first region 22 are in contact with the second zone 24b of the second region 24. The junction between the first region 22 and the second zone 24b of the second region 24 corresponds to the PN junction of the SPAD 12.The first zone 24a is more heavily doped than the second zone 24b of the second region 24. The second zone 24b is, for example, heavily doped. The second zone 24b has, for example, a dopant concentration of between 1017 atoms / cm3 and 1018 atoms / cm3.

[0044] The second region 24 further comprises a third zone 24c extending between the first zone 24a and the second zone 24b. The third zone 24c is for example in contact by its lower face with the upper face of the first zone 24a. The third zone 24c is for example in contact by its upper face with the lower face of the second zone 24b. The third zone 24c extends for example over the entire surface of the SPAD 12. The third zone 24c is for example in contact by its sides with the sides of the isolation trenches 16. The third zone 24c is for example very lightly doped. The third zone 24c is for example less heavily doped than the second zone 24b. The third zone 24c has for example a dopant concentration of the order of 1014 atoms / cm3.

[0045] For example, the insulation trenches 16 extend over the entire height of the second zone 24b and the third zone 24c. For example, the insulation trenches 16 extend over a portion of the height of the first zone 24a.

[0046] For example, the first region 22 corresponds to a cathode region of the SPAD and the second region 24 corresponds to an anode region of the SPAD.

[0047] The device 10 comprises, for example, a cathode contact connection on the front face of the substrate 14 via a metal pad 26. The metal pad 26 corresponds, for example, to a cathode electrode. For example, the metal pad 26 is in contact, via its lower face, with the upper face of the first region 22. The metal pad 26 is, for example, centered on the first region 22.

[0048] The device 10 further comprises an anode contact connection on the side of the rear face of the substrate 14 by means of a metal element 28. The metal element 28 corresponds, for example, to an anode electrode. The metal element 28 is in contact, by its flanks with the flanks of the first zone 24a of the second region 24. The metal element 28 is for example formed opposite the insulation trenches 16 or, in other words, directly above the insulation trenches 16. The metal element 28 is arranged at least partially in a trench extending vertically in the substrate 14 from the rear face of the substrate 14, for example in the extension of the insulation trenches 16. The metal element 28 extends for example over all or part of the height of the first zone 24a of the second region 24.

[0049] The metal element 28 extends for example over the entire width of the insulation trenches 16 so as to electrically contact the first zones of two neighboring SPADs 12. For example, the metal element 28 is in contact, by its upper face with the lower face of the insulation trenches 16. More particularly, the metal element 28 is for example in mechanically and electrically contact with the core 18 of the insulation trenches 16. As a variant, the lower face of the insulation trenches 16 and the upper face of the metal element 28 are separated by a layer, for example electrically insulating, for example an oxide layer.

[0050] The first zones 24a of the SPADs 12 of the device 10 are thus all connected to each other by a common electrode formed by the metal element 28. The first zones 24a of the SPADs 12 can be polarized at the same voltage via the common electrode 28. The metallic element 28 is for example a P-type doping metal. The use of such a metal makes it possible to increase the doping of the first zones 24a in the vicinity of the metallic element 28 by diffusion of the metal in the silicon of the substrate, thus improving the ohmic contact between the metallic element 28 and the first zone 24a. The metallic element 28 is for example made of aluminum (Al). The high concentration of dopants in the first zone 24a makes it possible to improve the ohmic contact between the metallic element 28 and to ensure good contact recovery of the anode. In addition, the proposed solution makes it possible to provide that the second zone 24b is less heavily doped than the first region 22.More generally, the proposed solution, in which the contact on the anode region 24a is taken from the side of the rear face of the substrate 14, allows greater freedom as to the choice of the concentration of doping elements of the second zone 24b, and thus as to the adjustment of the avalanche threshold of the PN junction of the SPAD.

[0051] In this example, the device does not include an anode contact recovery element in contact with the zone 24b on the side of the upper face of the substrate.

[0052] This makes it possible to reduce the size associated with the resumption of contact on the anode region of the SPAD photodiodes.

[0053] Preferably, the metal element 28 does not extend over the lower face of the first zones 24a.

[0054] Each SPAD 12 is for example connected, or connected individually by its cathode electrode 26, to a node for applying a potential VC. The SPADs 12 are for example connected or connected collectively by the common anode electrode 28, to a node for applying a potential VA. The potentials VA and VC allow the polarization of the SPADs 12. For example, the potential VA is zero and the potential VC is a positive potential.

[0055] [Fig.2] is another partial and schematic sectional view of the optoelectronic device 10 of [Fig.l].

[0056] The device 10 corresponds for example to a time of flight (ToF) sensor.

[0057] In the example of [Fig.2], each pixel P comprises a lens 32, for example a microlens, arranged opposite the SPAD 12. The microlens 32 is for example formed on the rear face 14b of the semiconductor substrate 14.

[0058] The pixel matrix P further comprises, between the SPADs 12 and the microlenses 32, a layer 34 made of an optically transparent material in which opaque elements 36 are formed. The layer 34 is for example made of silicon dioxide. By way of example, the elements 36 optically delimit each pixel P and make it possible to limit cross-detections, i.e. the detection by a SPAD 12 of a radiation passing through the microlens 32 of the neighboring pixel P. For example, the elements 36 form a grid superimposed on the grid of the isolation trenches 16, for example a grid coinciding in top view with the grid of the isolation trenches 16. The elements 36 are for example metallic, for example made of tungsten (W).

[0059] In the example of [Fig.2], the elements 36 are not in contact with the metal element 28. As a variant, it can be provided that the elements 36 are in contact by their upper faces with the lower face of the metal element 28.

[0060] The device 10 of [Fig. 2] further comprises, on the side of the upper face of the substrate 14, an interconnection stack 38. By way of example, the interconnection stack 38 comprises a stack of dielectric layers and conductive levels, for example metallic, in which connection elements are formed intended to individually connect the cathode electrodes of the SPAD photodiodes to a control circuit.

[0061] At the periphery of the pixel matrix P, the device 10 comprises for example one or more pads 40. The pads 40 are for example located on the side of the rear face 14b of the substrate 14. The pads 40 are for example intended to be connected to an external device, for example by means of electrically conductive wires, for example metal wires.

[0062] The pads 40 are preferably arranged out of line with the SPADs 12 so as not to mask them. For example, the pads 40 are made of a metallic material, for example aluminum.

[0063] The pads 40 are electrically connected to the common anode electrode 28 via conductive connection and routing elements detailed below. At the periphery of the pixel matrix P, the device 10 further comprises several other isolation trenches 16 formed in the substrate 14.

[0064] Some of these isolation trenches, referenced 16(1) in the figure, make it possible, for example, to electrically isolate the pixel matrix P from the rest of the substrate 14.

[0065] Others of these isolation trenches, referenced 16(2) in the figure, can be used as isolated conductive vias (i.e. conductive vias surrounded by an insulating envelope) passing through the substrate 14. In the example of [Fig.2], these latter isolation trenches 16(2), are for example extended by portions of the metallic element 28, which extend laterally outside the pixel matrix P. They thus contribute to ensuring electrical contact between the pad 40 and the metallic element, for example by means of conductive tracks.

[0066] By way of example, the electrical connection between the anode electrode 28 and the pad(s) 40 is made via the portions of the element 28 extending laterally outside the pixel matrix, via the conductive cores. trenches 16(2), via one or more conductive tracks 41 of the interconnection stack 38 and via one or more isolated conductive vias 43 crossing the substrate 14.

[0067] [Fig.3A], [Fig.3B] and [Fig.3C] are partial and schematic horizontal sectional views of examples of the optoelectronic device of Figures 1 and 2 according to different embodiments. More particularly, these figures are bottom views along a horizontal sectional plane corresponding to the plane of the face 14b of the substrate 14.

[0068] In [Fig.3A], [Fig.3B] and [Fig.3C], only the isolation trenches 16, the metallic element 28 and the first zones 24a of the second regions 24 of the SPADs of the pixels P are visible. The first regions 22 of the SPADs (not visible in the section plane) have also been represented schematically by broken lines.

[0069] According to a first embodiment, illustrated in [Fig.3A], the metal element 28 is formed opposite all of the insulation trenches 16. The metal element 28 then forms a grid substantially coinciding (view from below) with the grid formed by the insulation trenches 16 around the SPADs 12. The metal element 28 is continuous and is not interrupted.

[0070] According to a second embodiment, illustrated in [Fig.3B], the metal element 28 is formed opposite only a portion of the isolation trenches 16. In the second embodiment, the SPADs 12 are all in contact, via the sides of the first zone 24a, with the metal element 28. In this embodiment, each SPAD 12 does not have all the lateral sides of its first zone 24a in contact with the metal element 28. In other words, in this embodiment, each SPAD 12 has only a portion of the lateral sides of its first zone 24a in contact with the metal element 28. By way of example, provision is made for the metal element 28 to extend, in top view, around the periphery of the matrix of pixels P and only between lines of pixels P. As a variant, provision may be made for the metal element 28 to extend, in top view, around the periphery of the matrix of pixels P and only between lines of pixels P. from above on the perimeter of the P pixel matrix and only between columns of P pixels.In this embodiment, the metal member 28 is continuous such that the portions of the metal member 28 are all connected together.

[0071] According to a third embodiment, illustrated in [Fig.3C], the metal element 28 comprises several separate parts. Thus, the third embodiment differs from the second embodiment in that the metal element 28 is not continuous. In this embodiment, the different parts of the metal element 28, and thus the zones 24a, are electrically connected to each other by conductive elements of another conductive level, for example corresponding to the element 36 described in relation to [Fig.2]. The different parts of the metal element 28 are thus all electrically connected to each other via the element 36.

[0072] [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F], [Fig.4G] and [Fig.4H] ​​are sectional views illustrating steps of an example of a method of forming the device of Figures 1 and 2.

[0073] More particularly, FIGS. 4A to 4H illustrate steps of a method of manufacturing the metal element 28 opposite the insulation trenches 16.

[0074] In Figures 4A to 4H, the orientation of the figures is reversed compared to what was shown in Figures 1 and 2. The upper face of the structure of Figures 4A to 4H corresponds to the rear face of the structure and the lower face of the structure of Figures 4A to 4H corresponds to the front face of the structure.

[0075] [Fig.4A] illustrates a starting structure in which isolation trenches 16 have been formed in the semiconductor substrate 14.

[0076] This starting structure corresponds for example to a semiconductor substrate 14 on which an interconnection stack 38 (not shown in [Fig.4A]) has been produced on the front face side. After the interconnection stack has been produced, the substrate has been turned over and then thinned by its rear face, then the isolation trenches 16 have been formed on the rear face side of the thinned substrate.

[0077] The formation of the isolation trenches 16 comprises, for example, a step of etching the substrate 14 via its rear face so as to create openings opening, for example onto the interconnection stack 38. The formation of the trenches 16 further comprises a step of depositing a first sub-layer 201, in contact with the semiconductor substrate 14 and of depositing a second sub-layer 203 in contact with the first sub-layer 201. The first sub-layer 201 is, for example, deposited in the bottom of the openings, for example in contact with the interconnection stack, and on the sides of the openings and the rear face of the substrate 14, in contact with the substrate 14. The second sub-layer 203 is, for example, deposited, in the openings and on the side of the rear face of the substrate 14, in contact with the first sub-layer 201.The first sub-layer 201 and the second sub-layer 203 form, for example, in the openings, the insulating sheath 20 of the insulation trenches 16. The first sub-layer 201 is, for example, made of alumina. The second sub-layer 203 is, for example, made of silicon dioxide. The formation of the trenches 16 further comprises a step of depositing a metal layer in the openings and on the side of the rear face of the substrate 14, in contact with the second sub-layer, then a polishing step so that the metal layer is only retained in the openings. The metal layer then corresponds to the core 18 of the insulation trenches 16.

[0078] [Fig.4B] illustrates a structure obtained at the end of a step of depositing a masking layer 42 on the upper face of the structure illustrated in [Fig.4A]. The masking layer 42 is for example made of a material sensitive to light rays, for example example to ultraviolet (UV). The masking layer 42 is for example made of a resin. For example, the masking layer is made of a positive resin. During this step, the masking layer 42 is for example deposited full plate.

[0079] [Fig.4C] illustrates a structure obtained at the end of a photolithography step of the structure illustrated in [Fig.4B]. More particularly, during this step, the structure illustrated in [Fig.4B], more precisely the masking layer 42, is exposed by its upper face to radiation, for example a UV ray. By way of example, the exposure is carried out through a mask so as to expose the masking layer 42 only locally. This step is for example followed by a rinsing step making it possible to remove the part of the masking layer 42 which has been exposed and to form in the masking layer 42, one or more openings 44.

[0080] [Fig.4D] illustrates a structure obtained at the end of an etching step of the structure illustrated in [Fig.4C]. More particularly, during this step, a portion of the isolation trench 16 is removed opposite the opening 44 made in the masking layer 42. During this step, an upper portion of the second sub-layer 203 and of the core 18 is thus removed locally opposite the opening 44. By way of example, the etching is, here, selective with respect to the first sub-layer 201 of the cladding 20 of the isolation trench 16. This sub-layer 201 is for example preserved during this step. During this step, the masking layer 42 is for example consumed.

[0081] [Fig.4E] illustrates a structure obtained at the end of another etching step of the structure illustrated in [Fig.4D]. More particularly, during this step, an upper part of the first sub-layer 201 of the cladding 20 of the insulation trench 16 is removed opposite what has been removed from the second sub-layer 203. During this step, the sub-layer 203 is for example used as an etching mask. At the end of this step, a part of the sides of the semiconductor substrate 14 is then revealed and free. For example, during this step, cleaning is also carried out so as to clean the sides of the substrate 14. This cleaning step makes it possible, for example, to remove particles resulting from the etching steps and present on the sides of the substrate 14. Such particles can, for example, reduce the ohmic contact between the substrate 14 and the metal element 28 if they are not removed.The cleaning step corresponds, for example, to a basic cleaning of the SCI type (from the English "Standard Cleaning 1"). For example, an SCI type cleaning corresponds to a cleaning with ammonia and hydrogen peroxide.

[0082] [Fig.4F] illustrates a structure obtained at the end of a step of depositing a layer in a metallic material 46. For example, the deposition of the metallic layer 46 is carried out by chemical vapor deposition (CVD). The metallic layer 46 is for example deposited on the upper face of the structure illustrated in [Fig.4E] and more particularly, in the openings previously formed in the layers 201 and 203. During this step, the metal layer 46 is for example deposited in contact with the sides of the substrate 14. By way of example, during this step, the metal layer 46 is deposited in contact with the upper face of the core 18. As a variant, it can be provided that the metal layer 46 is not in direct contact (electrical and mechanical) with the core 18 of the isolation trench 16 but that it is by means of an insulating layer. The insulating layer is for example an oxide layer, for example formed during the various cleaning operations described above. The step of depositing the metal layer 46 is for example carried out at a temperature of between 200°C and 400°C, for example of the order of 300°C.

[0083] [Fig.4G] illustrates a structure obtained at the end of a step of polishing the upper face of the structure illustrated in [Fig.4F]. More precisely, during this step, a portion of the metal layer 46 is removed so as to reveal the upper face of the second sub-layer 203 of the sheath 20 of the insulation trench 16. This removal is for example carried out by chemical mechanical polishing (CMP). At the end of this step, what remains of the metal layer 46 corresponds to the metal element 28. In the example shown at the end of this step, the upper face of the metal element 28 is slightly set back relative to the upper face of the second sub-layer 203 of the sheath 20 of the insulation trench 16.This shrinkage is due to the fact that the polishing step is chemically assisted and that the solution used tends to etch the metal layer 46 more than the second sub-layer 203 of the sheath 20.

[0084] [Fig.4H] ​​illustrates a structure obtained at the end of a step of removing the second sub-layer 203 from the cladding 20 formed on the surface of the substrate 14 and a step of depositing three successive layers 48, 50 and 52. By way of example, during this step, the part of the second sub-layer 203 of the cladding 20 present on the upper face of the semiconductor substrate 14, around the metal element 28, is removed.

[0085] At the end of the removal step, a first layer 48 is, for example, deposited on the upper face of the structure. The first layer 48 is, for example, deposited as a full plate. The first layer 48 is, for example, deposited so as to cover the upper face of the first sub-layer 201 of the cladding 20 and the upper face and part of the sides of the metal element 28. For example, the first layer 48 is in contact with the upper face of the sub-layer 201 and the upper face and the sides of the metal element 28. The first layer 48 is, for example, an anti-reflective layer. The first layer 48 is, for example, made of a material having a high dielectric permittivity. For example, the first layer 48 is in alumina and / or silicon dioxide and / or hafnium oxide.

[0086] During this step, a second layer 50 is also deposited on the upper face of the layer 48. The second layer 50 is for example deposited in contact with the layer 48. For example, the layer 50 is deposited full wafer. For example, the layer 50 makes it possible to ensure sufficient distance between the SPADs and the microlenses, which will be formed subsequently on the side of the rear face of the structure. The layer 50 is for example made of silicon dioxide.

[0087] During this step, a third layer 52 is also deposited on the upper face of the layer 50. The third layer 52 is for example deposited in contact with the layer 50. For example, the layer 52 is deposited full plate. For example, the layer 52 corresponds, at the end of an etching step, to the elements 36 illustrated in [Fig.2].

[0088] The method illustrated in relation to Figures 4A to 4H can for example be implemented to manufacture the device of Figures 1 and 2 according to the embodiments of Figures 3A and 3B.

[0089] [Fig.5A], [Fig.5B], [Fig.5C], [Fig.5D], [Fig.5E] and [Fig.5F] are sectional views illustrating steps of another example of a method of forming the device of Figures 1 and 2.

[0090] More particularly, Figures 5A to 5F illustrate steps of a method of manufacturing the metal element 28 opposite the insulation trenches 16, different from the method illustrated in relation to Figures 4A to 4H in that, in the manufacturing method illustrated in Figures 5A to 5F, the elements 36 are formed in contact with the metal element 28.

[0091] In Figures 5A to 5F, similarly to what was described in connection with Figures 4A to 4H, the orientation of the structures is reversed from what was shown in Figures 1 and 2.

[0092] [Fig.5A] illustrates a starting structure identical to the starting structure illustrated in [Fig.4A].

[0093] [Fig.5B] illustrates a structure obtained at the end of a step of etching the second sub-layer 203 of the cladding 20 and the core 18 of [Fig.5A]. This step is for example similar to the step of etching these same layers, which was described in relation to [Fig.4D], with the difference that the etching described in relation to [Fig.5B] is carried out without an etching mask.

[0094] [Fig.5C] illustrates a structure obtained at the end of a step of depositing two layers 48 and 50 similar to the layers 48 and 50 illustrated in [Fig.4H], with the difference that they are, in the step illustrated in relation to [Fig.5C], deposited before the formation of the metallic element 28.

[0095] [Fig.5D] illustrates a structure obtained at the end of an etching step of the layers 48, 50 and 201. More particularly, during this step, three successive etching steps are carried out so as to form an opening 54 successively in layer 50, layer 48, and the first sub-layer 201. The etching of layer 50 is for example carried out through a resin masking layer (not shown) previously deposited on the upper face of the structure illustrated in [Fig.5C]. For example, at the end of this step, part of the sides of substrate 14 are revealed and free.

[0096] [Fig.5E] illustrates a structure obtained at the end of a step of forming the metallic element 28 in the opening 54. During this step, for example, a layer 46' of a metallic material is deposited on the upper face of the structure illustrated in [Fig.5D] and more particularly on the upper face of the layer 50 and in the opening 54 similarly to what was described with the layer 46 in relation to [Fig.4F]. Polishing is then carried out in order to keep the layer 46' only in the opening 54 similarly to what was described in relation to [Fig.4G]. What remains of the layer 46' then corresponds to the metallic element 28.

[0097] [Fig.5F] illustrates a structure obtained at the end of a step of forming a layer 52 similar to the layer 52 illustrated in [Fig.4H] ​​except that it is deposited on and in contact with the upper face of the metal element 28.

[0098] The method illustrated in relation to Figures 5A to 5F can for example be implemented to manufacture the device of Figures 1 and 2 according to the embodiments of Figures 3A, 3B and 3C.

[0099] An advantage of the embodiments described is that the resumption of contact of the anode by the rear face 14b of the substrate 14 makes it possible to reduce the surface area of ​​the SPADs 12 and thus reduce the surface area of ​​the sensors.

[0100] Another advantage of the embodiments described is that the contact resumption of the anode by the rear face 14b of the substrate 14 makes it possible to maintain a distance between the contact resumption of the anode and that of the cathode which makes it possible to ensure good operation of the SPAD by limiting the risks of short circuits, despite the reduction in the surface area of ​​the SPAD 12.

[0101] Yet another advantage of the embodiments described is that the resumption of contact of the anode by the sides of the substrate 14 in the extension of the insulation trenches 16 makes it possible not to mask the rear face 14b of the substrate 14, which therefore remains accessible to light.

[0102] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the cathode and the anode may be exchanged. The first region 22 may thus be the anode of the SPAD 12 and be P-doped. The second region 24 can then be the cathode of SPAD 12 and be N-doped.

[0103] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Optoelectronic device (10) comprising a plurality of avalanche diodes (12) formed in a semiconductor substrate (14), each diode (12) comprising in the substrate (14): a. a first region (22) doped with a first conductivity type (N), flush with a first face (14f) of the semiconductor substrate (14), and b.a second region (24) doped with a second conductivity type (P) opposite to the first conductivity type (N), the second region (24) extending in the semiconductor substrate (14) from the first region (22) to a second face (14b) of the semiconductor substrate (14), opposite to the first face (14f) of the semiconductor substrate (14), in which the second region (24) comprises: - a first zone (24a) flush with the second face of the semiconductor substrate (14), - a second zone (24b) in contact with the first region (22), and - a third zone (24c) extending between the first (24a) and the second zone (24b), in which the device comprises, on the side of the second face (14f) of the substrate (14), a common electrode comprising a metal element (28) in contact with at least part of the flanks of the first zones (24a) of the diodes (12), and wherein the first region (24a) is more heavily doped than the second region (24b) of the second region (24).

2. The optoelectronic device (10) of claim 1, wherein the metal element (28) is aluminum.

3. Optoelectronic device (10) according to claim 1 or 2, wherein the metallic element (28) is formed in the extension of isolation trenches (16) separating the avalanche diodes (12) from each other.

4. An optoelectronic device (10) according to claim 3, wherein the isolation trenches (16) comprise an electrically conductive core (18) surrounded by an electrically insulating sheath (20).

5. An optoelectronic device (10) according to claim 3 or 4, wherein the isolation trenches (16) are all extended by the metallic element (28).

6. An optoelectronic device (10) according to claim 3 or 4, wherein only a portion of the isolation trenches (16) is extended by the metal element (28).

7. An optoelectronic device (10) according to claim 5 or 6, wherein the metallic element (28) is continuous.

8. An optoelectronic device (10) according to claim 6, wherein the metallic element (28) comprises several separate parts.

9. An optoelectronic device (10) according to claim 8, wherein the different parts of the metallic element (28) are electrically connected to each other by conductive elements (36).

10. The optoelectronic device (10) of claim 9, wherein the conductive elements (36) are opaque.

11. A time-of-flight sensor comprising the optoelectronic device (10) according to any one of claims 1 to 10.

12. A method of manufacturing an optoelectronic device (10) comprising a plurality of avalanche diodes (12) formed in a semiconductor substrate (14), each diode (12) comprising in the substrate (14): a first region (22) doped with a first conductivity type (N), flush with a first face (14f) of the semiconductor substrate (14), and a second region (24) doped with a second conductivity type (P) opposite the first conductivity type (N), the second region (24) extending in the semiconductor substrate (14) from the first region (22) to a second face (14b) of the semiconductor substrate (14), opposite the first face (14f) of the semiconductor substrate (14), wherein the second region (24) comprises: - a first zone (24a) flush with the second face of the semiconductor substrate (14), - a second zone (24b) in contact with the first region (22),and - a third zone (24c) extending between the first (24a) and the second zone (24b), the method comprising the formation, on the side of the second face (14f) of the substrate (14), of a common electrode comprising a metallic element (28) in contact with at least part of the flanks of the first zones (24a) of the diodes (12), and in which the first zone (24a) is more heavily doped than the, second zone (24b) of the second region (24).

13. A method of manufacturing a device according to claim 12, wherein the formation of the metallic element (28) comprises the following successive steps: a) the formation of an isolation trench (16) in the conductive substrate (14), over the entire thickness of the semiconductor substrate by the second face (14b) of the substrate (14); b) the etching of an upper part of the isolation trench (16) on the side of the second face (14b) of the semiconductor substrate (14), so as to form an opening and reveal a part of the sides of the semiconductor substrate (14); and c) the deposition of a metallic layer (46; 46') in the previously formed opening (44; 54).

14. A method of manufacturing a device according to claim 13, comprising: - between steps a) and b), a step c) of depositing a transparent layer (50) on the side of the second face (14b) of the semiconductor substrate (14), the etching of step b) comprising the etching of the transparent layer (50), and - after step c), a step of forming conductive elements (38) on and in contact with the metal layer (46').

15. A method of manufacturing a device according to claim 13, comprising after step c), a step of depositing a transparent layer (50) on the side of the second face (14b) of the semiconductor substrate (14) and a step of forming conductive elements (38) on and in contact with the transparent layer (50).

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