Electronic device-Electronic device

Abstract

Electronic device The present description relates to a device comprising a transistor (10, 40), the transistor comprising: - a first P-doped semiconductor layer (15); - a second piezoelectric semiconductor layer (16), covering the first layer (15); - a third piezoelectric semiconductor layer (18), covering the second layer (16); - a fourth piezoelectric semiconductor layer (20), covering the third layer (18); - a fifth piezoelectric semiconductor layer (22), covering the fourth layer (20), the transistor being configured to generate a first two-dimensional gas of electrons (36) between the fourth and fifth layers (20, 22); and - a gate pattern (24) passing through the fifth layer (22) and at least a part of the fourth layer (20). Figure for abstract: Fig. 1

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more particularly to electronic devices comprising power transistors based on semiconductors. Prior art

[0002] In the field of power electronics, the development of power transistors based on "wide bandgap" semiconductors, such as GaN, constitutes a major challenge.

[0003] Different architectures have been specifically developed for these GaN-based transistors. Architectures based on the use of a two-dimensional electron gas (2 DEG) generally allow operation with high source-drain bias voltages. A positive threshold voltage advantageously simplifies the transistor control circuit and ensures the safety of the conversion system in the event of failure. Summary of the invention

[0004] One embodiment provides a device comprising a transistor, the transistor comprising: - a first P-doped semiconductor layer; - a second piezoelectric semiconductor layer, covering the first layer; - a third piezoelectric semiconductor layer, covering the second layer; - a fourth piezoelectric semiconductor layer, covering the third layer; - a fifth piezoelectric semiconductor layer, covering the fourth layer, the transistor being configured to generate a first two-dimensional gas of electrons between the fourth and fifth layers; and - a gate pattern passing through the fifth layer and at least a portion of the fourth layer.

[0005] According to one embodiment, the transistor is configured to generate a second two-dimensional electron gas between the second and third layers, the first layer being configured to suppress the second electron gas.

[0006] According to one embodiment, the grid pattern passes through the third, fourth and fifth layers and at least a portion of the second layer.

[0007] According to one embodiment, the second and fourth layers are made of the same material.

[0008] According to one embodiment, the second and fourth layers are made of GaN.

[0009] According to one embodiment, the third and fifth layers are made of same material.

[0010] According to one embodiment, the third and fifth layers are made of AlGaN, AsGa, AIN or InGaN.

[0011] According to one embodiment, the first layer is made of GaN doped with magnesium, carbon or iron.

[0012] According to one embodiment, the first layer is configured not to be polarized.

[0013] According to one embodiment, the grid pattern separates at least the fifth layer into a first part and a second part.

[0014] According to one embodiment, the grid pattern separates the third, fourth and fifth layers into a first part and a second part.

[0015] According to one embodiment, the device comprises a first electrode in contact with the first part of the fifth layer and a second electrode in contact with the second part of the fifth layer.

[0016] According to one embodiment, the first layer is configured to be biased with the same voltage as one or the other of the first and second electrodes. Brief description of the drawings

[0017] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0018] [Fig.l] represents an example of an electronic device comprising a semiconductor-based power transistor;

[0019] [Fig.2] represents an embodiment of an electronic device comprising a semiconductor-based power transistor;

[0020] [Fig.3] represents the behavior of the electronic device of [Fig.2]; and

[0021] [Fig.4] shows another embodiment of an electronic device comprising a semiconductor-based power transistor. Description of the embodiments

[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0024] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by through one or more other elements.

[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0026] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0027] [Fig.l] shows an example of an electronic device comprising a semiconductor-based power transistor.

[0028] More specifically, [Fig.l] schematically represents a part of a device comprising the power transistor 10. The transistor 10 is a HEMT (High Electron Mobility Transistor) type transistor. Such a transistor is a high electron mobility field effect transistor, sometimes referred to as a heterostructure field effect transistor.

[0029] The transistor 10 comprises a stack 12 of layers 14, 16, 18, 20, 22. The stack 12 is for example located in or on a semiconductor substrate 13. The substrate 13 is for example made of silicon, sapphire or SiC. In the example of [Fig.l], the stack 12 is located on the upper surface of the substrate 13.

[0030] Layer 14 is a buffer layer. Layer 14 may correspond to several buffer layers. Buffer layer 14 is for example made of AIN, GaN or AlGaN.

[0031] Layer 16 is made of a piezoelectric material, for example GaN. Layer 16 is for example doped intrinsically or involuntarily. In other words, layer 16 is not doped or is doped with a doping concentration of less than 1014 cm 3. Layer 16 is located on, and for example in contact with, layer 14. Layer 16 is for example floating. In other words, layer 16 is for example not polarized. According to a variant, layer 16 is polarized by the reference voltage, for example ground.

[0032] Layer 18, which constitutes a rear barrier, is made of a piezoelectric material, for example AlGaN. The aluminum content is for example greater than 4%. Layer 18 is located on, and for example in contact with, layer 16. Layer 18 is for example floating.

[0033] Layer 20, which constitutes a channel, is made of a piezoelectric material, for example GaN. Layer 20 is located on, and for example in contact with, layer 18.

[0034] Layer 22, which constitutes a barrier, is made of a piezoelectric material, for example AlGaN. The aluminum content is for example greater than 4%. Layer 22 is located on, and for example in contact with, layer 20. Layer 22 does not does not, for example, entirely cover layer 20. In other words, a portion of layer 20, for example a portion of the upper surface of layer 20, is not covered by layer 22.

[0035] Transistor 10 includes a gate pattern 24. Gate pattern 24 is located in a cavity 26. The cavity extends from the top surface of layer 22, through layer 22 and a portion of layer 20. In other words, cavity 26 extends across the interface between layers 20 and 22. Cavity 26 extends through layers 18, 20, 22 and through a portion of layer 16. In other words, the bottom of cavity 26 of [Fig.l] is located in layer 16.

[0036] The layers crossed by the cavity, for example layers 18, 20, 22 of [Fig.l], are divided into two parts by the cavity 26. Layer 18 is divided into parts 18a and 18b, parts 18a and 18b not being in contact with each other. Layer 20 is divided into parts 20a and 20b, parts 20a and 20b not being in contact with each other. Layer 22 is divided into parts 22a and 22b, parts 22a and 22b not being in contact with each other. Parts 18a, 20a, 22a form a secondary stack 12a and parts 18b, 20b and 22b form a secondary stack 12b. The secondary stacks 12a and 12b are separated by the cavity 26.

[0037] The gate pattern 24 comprises a dielectric layer 28 and a conductive layer 30. The layer 28 conformally covers the cavity 28 and a portion of the upper surface of the layer 22 surrounding the cavity 26. In other words, the layer 28 covers the lateral surface of the layers 16, 18, 20, 22 forming the walls of the cavity, the surface of the layer 16 forming the bottom of the cavity 26 and a portion of the upper surface of the layer 22 surrounding the cavity 26. The layer 30 conformally covers the layer 28. Preferably, the layer 30 entirely and only covers the layer 28. The layer 30 is therefore separated from the stack 12 by the layer 28.

[0038] The transistor 10 comprises a drain electrode 32 and a source electrode 34. The drain electrode 32 is in contact with the two layers 20 and 22 on one side of the cavity 26 and the source electrode 34 is in contact with the two layers 20 and 22 on the other side of the cavity 26. More specifically, the drain electrode 32 is in contact with the parts 20a and 22a of the layers 20 and 22 and the source electrode 34 is in contact with the parts 20b and 22b of the layers 20 and 22. In the example of [Fig.l], the drain electrode 32 covers a part of the upper surface of the part 22a, a part of the upper surface of the part 20a which is not covered by the part 22a and the side surface of the part 22a. Similarly, the source electrode 34 covers a portion of the upper surface of the portion 22b, a portion of the upper surface of the portion 20b which is not covered by the portion 22b and the side surface of the portion 22b.

[0039] The architecture of a HEMT transistor such as transistor 10 comprises the superposition of two semiconductor layers having different band gaps which form a quantum well at their interface. This quantum well is induced by the spontaneous and piezoelectric polarization charges present. Electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG). In stack 12 of [Fig.l], a two-dimensional electron gas 36 is formed under layer 22, in layer 20. The two-dimensional electron gas 36 is generally confined at the interface between layers 20 and 22. Layers 20 and 22 form a heterojunction.

[0040] The grid pattern 24 crosses this interface between the layers 20 and 22, so as to interrupt the two-dimensional electron gas 36. Controlling the grid voltage Vgs allows the passage of electrons from the two-dimensional electron gas 36 to be authorized or blocked on either side of the grid pattern 24.

[0041] Generally, if the gate of the transistor is set to a voltage greater than a threshold voltage, there is an accumulation of electrons under the gate dielectric, thus connecting the two-dimensional electron gas on either side thereof, which makes it possible to connect the source and the drain so that the transistor switches to the on state. Consequently, when the gate pattern 24 is in a state suitable for allowing the passage of electrons, the two-dimensional electron gas 36 extends between the portions 20a and 22a, along the walls and the bottom of the cavity 26 and between the portions 20b and 22b.

[0042] If the gate of the transistor is set to a voltage lower than the threshold voltage, the source and drain are no longer connected and the transistor enters a blocked state.

[0043] A second two-dimensional electron gas 38 is formed beneath layer 18, in layer 16. The two-dimensional electron gas 38 is generally confined to the interface between layers 16 and 18. The two-dimensional electron gas 38 generates an unwanted constant leakage current flowing between the drain and source of transistor 10.

[0044] [Fig. 2] shows an embodiment of an electronic device comprising a semiconductor-based power transistor 11. More specifically, [Fig. 2] schematically shows a portion of a device comprising the power transistor 11. The transistor 11 is a high electron mobility transistor (HEMT) type transistor. Such a transistor is a high electron mobility field effect transistor, sometimes referred to as a heterostructure field effect transistor.

[0045] The device is for example intended for the automotive industry. The electrification of motor vehicles generates an increasingly high level of electronic content in the vehicles. The device comprises for example a high electron mobility transistor (HEMT) intended to be incorporated in these vehicles. The automation of automobile driving also generates an increasingly high level of electronic content in the vehicles.

[0046] The device can for example be used in the industrial field. More particu Specifically, the device is intended, for example, to be used for the development of green energy or for the electrification of infrastructure, for example for charging stations or for the incorporation of solar energy. The device can also be used in the field of the Internet of Things and smart homes. The device is, for example, intended to be implemented in the power and supply circuits of elements of equipment, comprising, for example, 650 V or 1200 V HEMTs, ultrafast and silicon carbide 1200 V diodes, transient voltage suppression diodes, and electromagnetic discharge protections. The device can also be used in the implementation of computing clouds, 5G networks, data centers and servers. The device comprises, for example, wide bandgap materials.

[0047] The device is for example intended to be used in personal electronics, for example for the purpose of increasing the content of radio frequencies, in 5G connections or more generally in connected devices. The device is for example a smartphone or a part of an Internet of Things network. The device is for example connected by 5G, WIFI or ultra-wideband. The device comprises for example high-speed interfaces, for example with advanced filtering and protection against electromagnetic discharges.

[0048] The device is for example intended to be used in communication equipment, or in computers and peripherals. For example, the device can be used in 5G infrastructures and dedicated data centers. The device comprises for example silicon carbide diodes, power Schottky transistors, electromagnetic discharge protections and transient voltage suppression diodes. The device can also be used in satellites, comprising for example integrated passive devices for radio frequency applications.

[0049] The described device comprises a HEMT type transistor. HEMT type transistors are generally used in high-frequency and high-power applications such as satellite communications, radar systems, battery chargers, computers, servers, automobiles, lighting systems and photovoltaic systems, microwave amplifiers and all equipment requiring power conversion, for example, direct-direct DC / DC or alternating-direct AC / DC or alternating-alternating AC / AC or direct-alternating DC / AC power conversion. HEMT type transistors can also be used in certain specialized personal electronic devices, such as high-end audio amplifiers or radio frequency (RF) transmitters. HEMT type transistors are increasingly used in the electrification of cars, particularly in electric and hybrid vehicles.

[0050] The transistor 11 comprises, like the device 10 of [Fig. 1], a stack 12 of layers 14, 16, 18, 20, 22. In the embodiment of [Fig. 2], the stack 12 further comprises a layer 15. Preferably, the layers 14, 15, 16, 18, 20, 22 of the stack 12 are arranged in this order from the substrate. The stack 12 is for example located in or on the semiconductor substrate 13. The substrate is for example made of silicon, sapphire or SiC.

[0051] Layer 14 is a buffer layer. Layer 14 may correspond to several buffer layers. Buffer layer 14 is for example made of AlGaN, AIN or GaN. Layer 14 is for example the lowest layer of stack 12. In other words, layer 14 is for example the layer closest to substrate 13.

[0052] Layer 15 is a semiconductor layer. Layer 15 is P-doped. For example, layer 15 is made of GaN. For example, layer 15 is doped with magnesium, carbon or iron. Layer 15 is, for example, the second lowest layer of the stack 12. Layer 15 is, for example, separated, preferably entirely, from the substrate by layer 14. The doping concentration is, for example, greater than 1017 cm 3, for example substantially equal to 1018 cm 3.

[0053] Preferably, layer 15 is floating. In other words, layer 15 is preferably not polarized. According to a variant, layer 15 is polarized by the reference voltage, for example ground.

[0054] Layer 16 is made of a piezoelectric material, preferably a piezoelectric semiconductor material. Layer 16 constitutes a buried channel or an intermediate layer. Layer 16 is preferably made of a material configured to be formed, for example to be grown by epitaxy, on layer 15. Layer 16 is for example made of GaN. Layer 16 is preferably doped intrinsically or involuntarily. In other words, layer 16 is not doped or is doped with a doping concentration of less than 1014 cm 3. For example, layer 16 is made of the same material as layer 15.

[0055] Layer 16 is for example the third lowest layer of stack 12. Layer 16 is for example located on, and preferably in contact with, layer 15. Layer 16 is for example separated, preferably entirely, from layer 14 by layer 15.

[0056] Preferably, layer 16 is floating. In other words, layer 16 is preferably not polarized. According to a variant, layer 16 is polarized by the reference voltage, for example ground.

[0057] Layer 18 is made of a piezoelectric material, preferably a piezoelectric semiconductor material. Layer 18 constitutes a back barrier. Layer 18 is preferably made of a material configured to be formed, for example to be grown epitaxially, on layer 16. Layer 18 is made of a material different from that of layer 16. Layer 18 is for example made of AlGaN, InGaN, AsGa or AIN. Preferably, layer 18 is made of AlGaN, the aluminum content being greater than 4%.

[0058] Layer 18 is for example the fourth lowest layer of stack 12. Layer 18 is for example located on, and preferably in contact with, layer 16. Layer 18 is for example separated, preferably entirely, from layer 15 by layer 16. Layer 18 is preferably not in contact with layer 15.

[0059] Preferably, layer 18 is floating. In other words, layer 18 is preferably not polarized. According to a variant, layer 18 is polarized by the reference voltage, for example ground.

[0060] Layer 20 is made of a piezoelectric material, preferably a piezoelectric semiconductor material. Layer 20 constitutes a channel. Layer 20 is preferably made of a material configured to be formed, for example to be grown by epitaxy, on layer 18. Layer 20 is made of a material different from that of layer 18. For example, the material of layer 20 is the same as that of layer 16. Layer 20 is for example made of GaN.

[0061] Layer 20 is for example the fifth lowest layer of stack 12. Layer 20 is for example located on, and preferably in contact with, layer 18. Layer 20 is for example separated, preferably entirely, from layer 16 by layer 18. Layer 18 is preferably not in contact with layers 15 and 16.

[0062] Layer 22 is made of a piezoelectric material, preferably a piezoelectric semiconductor material. Layer 22 constitutes a barrier. Layer 22 is preferably made of a material configured to be formed, for example to be grown by epitaxy, on layer 20. Layer 22 is made of a material different from that of layer 20. Layer 22 is for example made of the same material as layer 18. Layer 22 is for example made of AlGaN, InGaN, AsGa or AIN. Preferably, layer 22 is made of AlGaN, the aluminum content being greater than 4%.

[0063] Layer 22 is for example the uppermost layer of stack 12, in other words, the layer furthest from the substrate and furthest from the buffer layer not shown. Layer 22 is for example located on, and preferably in contact with, layer 20. Layer 22 is for example separated, preferably entirely, from layer 18 by layer 20. Layer 22 is preferably not in contact with layers 14, 15, 16, 18. Layer 22 does not, for example, entirely cover layer 20. In other words, a part of layer 20, for example a part of the upper surface of layer 20, is not covered by layer 22.

[0064] According to one embodiment, layers 16, 18, 20 and 22 are all in different piezoelectric materials. According to another embodiment, layers 16 and 20 are made of the same material and layers 18 and 22 are made of the same material.

[0065] Preferably, each of the layers 14, 15, 16, 18, 20, 22 is a homogeneous layer. Preferably, each of the layers 14, 15, 16, 18, 20, 22 is made of a single material.

[0066] Layer 16 has, for example, a doping concentration of less than 1014 cm 3. Layer 18 has a thickness of between 20 nm and 150 nm. Layer 20 has, for example, a doping concentration of less than 1014 cm 3. Layer 20 has a thickness of, for example, between 50 nm and 200 nm. Layer 22 has a thickness of between 20 nm and 100 nm.

[0067] The semiconductor materials of the transistor 10 are for example chosen so as to have a wide forbidden band, for reasons of power resistance (in particular, high voltage) and temperature.

[0068] Transistor 11 includes a gate pattern 24. Gate pattern 24 is located in a cavity 26. The cavity extends from the upper surface of layer 22. Cavity 26 extends at least through layer 22 and a portion of layer 20. In other words, cavity 26 extends through the interface between layers 20 and 22. In the embodiment of [Fig. 2], cavity 26 extends through layers 18, 20, 22 and through a portion of layer 16. In other words, the bottom of cavity 26 of [Fig. 2] is located in layer 16. Preferably, the bottom of cavity 26 is located between the interface of layers 20 and 22 and layer 16.

[0069] The layers crossed by the cavity, for example layers 18, 20, 22 of [Fig. 2], are divided into two parts by the cavity 26. Layer 18 is divided into parts 18a and 18b, parts 18a and 18b not being in contact with each other. Layer 20 is divided into parts 20a and 20b, parts 20a and 20b not being in contact with each other. Layer 22 is divided into parts 22a and 22b, parts 22a and 22b not being in contact with each other. Parts 18a, 20a, 22a form a secondary stack 12a and parts 18b, 20b and 22b form a secondary stack 12b. The secondary stacks 12a and 12b are separated by the cavity 26.

[0070] The gate pattern 24 comprises a dielectric layer 28 and a conductive layer 30. The layer 28 conformally covers the cavity 28 and a portion of the upper surface of the layer 22 surrounding the cavity 26. In other words, the layer 28 covers the lateral surface of the layers 16, 18, 20, 22 forming the walls of the cavity, the surface of the layer 16 forming the bottom of the cavity 26 and a portion of the upper surface of the layer 22 surrounding the cavity 26. The layer 30 conformally covers the layer 28. Preferably, the layer 30 entirely and only covers the layer 28. The layer 30 is therefore separated from the stack 12 by the layer 28.

[0071] The transistor 11 comprises a drain electrode 32 and a source electrode 34. The drain electrode 32 is in contact with the two layers 20 and 22 on one side of the cavity 26 and the source electrode 34 is in contact with the two layers 20 and 22 on the other side of the cavity 26. More specifically, the drain electrode 32 is in contact with the parts 20a and 22a of the layers 20 and 22 and the source electrode 34 is in contact with the parts 20b and 22b of the layers 20 and 22. In the example of [Fig. 2], the drain electrode 32 covers a part of the upper surface of the part 22a, a part of the upper surface of the part 20a which is not covered by the part 22a and the side surface of the part 22a. Similarly, the source electrode 34 covers a portion of the upper surface of the portion 22b, a portion of the upper surface of the portion 20b which is not covered by the portion 22b and the side surface of the portion 22b.

[0072] The architecture of a HEMT transistor such as transistor 11 comprises the superposition of two semiconductor layers having different band gaps which form a quantum well at their interface. This quantum well is induced by the spontaneous and piezoelectric polarization charges present. The electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG). In stack 12 of [Fig. 2], a two-dimensional electron gas 36 is formed under layer 22, in layer 20. The two-dimensional electron gas 36 is generally confined at the interface between layers 20 and 22. Layers 20 and 22 form a heterojunction.

[0073] The grid pattern 24 crosses this interface between the layers 20 and 22, so as to interrupt the two-dimensional electron gas 36. Controlling the grid voltage Vgs allows the passage of electrons from the two-dimensional electron gas 36 to be authorized or blocked on either side of the grid pattern 24.

[0074] Generally, if the gate of the transistor is set to a voltage greater than a threshold voltage, there is an accumulation of electrons under the gate dielectric, thus connecting the two-dimensional electron gas on either side thereof, which makes it possible to connect the source and the drain so that the transistor switches to the on state. Consequently, when the gate pattern 24 is in a state suitable for allowing the passage of electrons, the two-dimensional electron gas 36 extends between the portions 20a and 22a, along the walls and the bottom of the cavity 26 and between the portions 20b and 22b.

[0075] If the gate of the transistor is set to a voltage lower than the threshold voltage, the source and drain are no longer connected and the transistor goes into a blocked state.

[0076] It would be advantageous for the threshold voltage to be positive. Indeed, if the threshold voltage value is relatively low (<1V), the device may require a negative Vgs voltage to control the blocked state. Applying a Vgs voltage <0 implies the use of a more complex control circuit and the increase of the resistance of the transistor in the on state.

[0077] Layers 16 and 18 allow the threshold voltage to be increased to higher values.

[0078] However, a two-dimensional electron gas 38 is formed under layer 18, in layer 16. The two-dimensional electron gas 38 is generally confined to the interface between layers 16 and 18. The two-dimensional electron gas 38 generates a constant leakage current flowing between the drain and the source of transistor 10. This current is all the greater if the gate pattern does not cross the interface between layers 16 and 18.

[0079] The layer 15 is made of a P-doped semiconductor material. The layer 15 is therefore configured to deplete electrons in the neighboring regions. In the embodiment of [Fig. 2], the thickness of the layer 16, in other words the distance between the two-dimensional electron gas 38 and the layer 15, is configured to ensure that the two-dimensional electron gas 38 is at least partially suppressed by the influence of the P-type doping of the layer 15. In other words, the layer 15 stops the current generated by the two-dimensional electron gas 38. In other words, the layer 15 is configured to deplete the two-dimensional electron gas 38.

[0080] The choice of the thickness of the layer 16 depends on the leakage current generated by the two-dimensional electron gas 38 which must be suppressed. In the case of a layer 18 made of AlGaN, said leakage current depends on the aluminum content in the layer 18. Preferably, the thickness of the layer 16 allowing the compensation of the leakage current decreases when the aluminum content increases. The thickness of the layer 16 also depends on the thickness of the layer 18.

[0081] According to a preferred embodiment, layer 15 is made of magnesium-doped GaN. Preferably, the thickness of layer 15 is greater than 10 nm, preferably greater than 50 nm, for example substantially equal to 100 nm. In the preferred embodiment, layer 15 is floating and does not receive a bias voltage. According to the preferred embodiment, layer 16 is made of intrinsic GaN. Preferably, layer 16 is floating. Preferably, the thickness of layer 16 is less than 150 nm, preferably less than 100 nm. According to the preferred embodiment, layer 18 is made of AlGaN. Preferably, the aluminum content in layer 18 is greater than 4%, for example substantially equal to 4%. Preferably, layer 18 is floating. Preferably, the thickness of the layer 18 is greater than 20 nm, for example substantially equal to 75 nm. According to the preferred embodiment, the layer 20 is made of intrinsic GaN.Preferably, the thickness of the layer 20 is greater than 50 nm, for example substantially equal to 80 nm. According to the preferred embodiment, the layer 22 is made of AlGaN. Preferably, the aluminum content in the layer 22 is greater than 4%, for example substantially equal to 25%. Preferably, the thickness of the layer 22 is between 20 nm and 100 nm, for example. example substantially equal to 24 nm.

[0082] According to another embodiment, the device comprises a contact element configured to polarize the layer 15. For example, the device comprises an insulated conductive via, not shown, comprising a conductive core and an insulating sheath. The via passes through, for example, the layers 16, 18, 20 to reach the upper surface of the layer 15.

[0083] [Fig. 3] represents the behavior of the electronic device of [Fig. 2]. More precisely, [Fig. 3] represents, in view A, with curves C1, C2, C3, C4, C5, the energy of the conduction band in the different regions of the transistor 11 of [Fig. 2] for different values ​​of the thickness of the layer 16. Furthermore, [Fig. 3] represents, in view A and in view B with curves C6, C7, C8, C9 and CIO, the concentration of electrons, in the different regions of the transistor 11 of [Fig. 2] for different values ​​of the thickness of the layer 16. View B corresponds to an enlarged region 41 of view A.

[0084] In the different cases illustrated by way of example in [Fig.3], layer 15 has a thickness of 100 nm, layer 18 has a thickness of 75 nm, layer 20 has a thickness of 80 nm and layer 22 has a thickness of 24 nm.

[0085] Curves C1 and C6, C6 being identical to C7, correspond to a case in which layer 16 has a thickness of 50 nm. Curves C2 and C7 correspond to a case in which layer 16 has a thickness of 100 nm. Curves C3 and C8 correspond to a case in which layer 16 has a thickness of 150 nm. Curves C4 and C9 correspond to a case in which layer 16 has a thickness of 200 nm. Curves C5 and C10 correspond to a case in which layer 16 has a thickness of 250 nm.

[0086] The curves of [Fig.3] comprise different parts corresponding to the different regions of the transistor 11. The part Z22 corresponds to the layer 22, the part Z20 corresponds to the layer 20, the part ZI8 corresponds to the layer 18, the part ZI6 corresponds to the layer 16 and the part ZI5 corresponds to the layer 15.

[0087] The transistor is considered to be on. All curves C6 to CIO include a peak at the junction between parts Z22 and Z20, corresponding to the two-dimensional gas of electrons 36 between the electrodes of the transistor.

[0088] In view B, it can be seen that curves C8, C9 and CIO include a peak at the junction between portions Z16 and Z18, corresponding to the two-dimensional electron gas 38 between the electrodes of the transistor. The two-dimensional electron gas 38 is therefore not suppressed for the thickness corresponding to curves C8, C9 and CIO. It can also be observed that curves C6 and C7 do not include a peak at the junction between portions Z16 and Z18. Therefore, for the corresponding thickness of layer 16, the two-dimensional electron gas 38 is suppressed.

[0089] Thicknesses allowing the suppression of the two-dimensional electron gas 38 depend on the composition of the transistor, including the doping values ​​of the different regions and the thickness of the different regions. They can be determined empirically.

[0090] [Fig.4] represents another embodiment of an electronic device comprising a semiconductor power transistor 40.

[0091] The power transistor 40 comprises the elements of the transistor 10. These elements will not be described a second time in detail. In other words, the transistor 40 comprises: - buffer layer 14; - the P 15 doped layer, - the piezoelectric layer 16, - the piezoelectric layer 18, - the piezoelectric layer 20, - the piezoelectric layer 22, - cavity 26, - the grid pattern 24, comprising the dielectric layer 28 and the conductive layer 30, and - the drain electrode 32.

[0092] Transistor 40 differs from transistor 11 of [Fig.2] in that one of the electrodes, for example source electrode 34 of [Fig.2], is replaced by an electrode 42 which is in contact with layer 15. For example, part of the upper surface of layer 14 is not covered by layers 16, 18, 20, 22. One of the electrodes, for example electrode 42, covers: - a part of the upper surface of the layer 22, for example the part 22b, - the lateral surfaces of the layers 16, 18, 20, 22, for example the lateral surfaces of the parts 18b, 20b, 22b and of the layer 16, and - the part of the upper surface of layer 15 not covered by layers 16, 18, 20, 22.

[0093] In the embodiment of [Fig.4], layer 15 is biased with the same voltage as one of the electrodes, for example the source electrodes. For example, layer 15 is biased to ground. For example, layer 15 and source electrode 42 are both biased to ground.

[0094] According to one embodiment, the lateral surfaces of the layers 16, 18, 20, 22 are separated from the electrode 42 by a dielectric layer, not shown. The electrode is then in contact only with the upper surfaces of the layers 15 and 22.

[0095] An advantage of the described embodiments is that the threshold voltage of the transistor is higher, preferably positive. The transistor is therefore simpler to implement and more reliable.

[0096] Another advantage of the described embodiments is that the power consumption of the transistor is lower, since a leakage current has been neutralized.

[0097] Another advantage of the described embodiments is that, since the leakage current generated by the two-dimensional electron gas 38 is stopped by the layer 15, the bottom of the cavity 26 can be located above the layer 15 without increasing the leakage current.

[0098] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0099] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A device comprising a transistor (10, 40), the transistor comprising: - a first P-doped semiconductor layer (15); - a second piezoelectric semiconductor layer (16), covering the first layer (15); - a third piezoelectric semiconductor layer (18), covering the second layer (16); - a fourth piezoelectric semiconductor layer (20), covering the third layer (18); - a fifth piezoelectric semiconductor layer (22), covering the fourth layer (20), the transistor being configured to generate a first two-dimensional gas of electrons (36) between the fourth and fifth layers (20, 22); and - a gate pattern (24) passing through the fifth layer (22) and at least a portion of the fourth layer (20).

2. The device of claim 1, wherein the transistor (10, 40) is configured to generate a second two-dimensional electron gas (38) between the second (16) and third (18) layers, the first layer (15) being configured to suppress the second electron gas (38).

3. A device according to claim 1 or 2, wherein the grid pattern (24) passes through the third (18), fourth (20) and fifth (22) layers and at least a portion of the second layer (16).

4. A device according to any one of claims 1 to 3, wherein the second (16) and fourth (20) layers are made of the same material.

5. A device according to any one of claims 1 to 4, wherein the second (16) and fourth (20) layers are GaN.

6. A device according to any one of claims 1 to 5, wherein the third (18) and fifth (22) layers are made of the same material.

7. A device according to any one of claims 1 to 6, wherein the third (18) and fifth (22) layers are made of AlGaN, AsGa, AIN or InGaN.

8. A device according to any one of claims 1 to 7, wherein the first layer (15) is made of magnesium, carbon or iron doped GaN.

9. A device according to any one of claims 1 to 8, wherein the first layer (15) is configured to be non-polarized.

10. A device according to any one of claims 1 to 9, wherein the grid pattern (24) separates at least the fifth layer (22) into a first portion (22a) and a second portion (22b).

11. The device of claim 10, wherein the grid pattern (24) separates the third (18), fourth (20) and fifth (22) layers into a first portion (18a, 20a, 22a) and a second portion (18b, 20b, 22b).

12. A device according to any one of claims 1 to 10, wherein the device comprises a first electrode (32) in contact with the first portion (22a) of the fifth layer (22) and a second electrode (34, 42) in contact with the second portion (22b) of the fifth layer (22).

13. A device according to any one of claims 1 to 11, wherein the first layer (15) is configured to be biased with the same voltage as either of the first and second electrodes (32, 34, 42).

14. A method of using the device according to any one of claims 1 to 13 in on-board chargers for electric vehicles, in charging stations, in photovoltaic systems, in household appliances, in telecommunications systems, in data centers and servers, in light-emitting diode lighting systems or in equipment requiring energy conversion.

15. A system comprising an on-board charger in an electric vehicle, a charging station, a photovoltaic system, a household appliance, a telecommunications system, a data center, a server, a light-emitting diode lighting system, or equipment requiring energy conversion, the system comprising the device according to any one of claims 1 to 13.

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