Input / output processing system for serial digital architectures and associated process

Abstract

One aspect of the invention relates to a memory access method in a computer network included in an aircraft, the computer network comprising at least a first and a second device, the method comprising: Issuance of at least one sequential access request, by the first device, to a memory of the second device via a serial bus, the sequential access request comprising a plurality of contiguous memory addresses, Reception, by an address conversion module included in the network and connected to the first device by the serial bus, of the sequential access request, For each address of the plurality of contiguous memory addresses, conversion, by the address conversion module of the network, of the address into a converted address from predefined descriptors, Issuance, by the address conversion module of the network, of an access request to the memory of the second device, each access request comprising at least one converted memory address.Figure to be published with the abbreviation: Figure 3.

Description

Title of the invention: Input / output processing system for serial digital architectures and associated method. TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of computer systems architecture, and in particular in aeronautics.

[0002] The present invention relates to an input-output processing system for serial digital architectures and in particular such a system for use in aeronautics. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] Integrated components, whether in ASICs (Application-Specific Integrated Circuits) or FPGAs (Field-Programmable Gate Arrays), dedicated to processing low-performance input / output signals such as CANs (Controller Area Networks), UARTs (Universal Asynchronous Receiver-Transmitters), discrete signals, and A429 (ARINC 429, an avionics communication standard), have historically been characterized by register interfaces requiring frequent small read / write accesses to ensure their operation. This approach, functional in earlier architectures, now faces the challenges of modern architectures that favor the use of high-bandwidth serial buses, but with significant latency.

[0004] In the current context, the most relevant prior art solutions involve the widespread use of interrupt-driven software combined with DMAs (Direct Memory Access). This combination makes it possible to offload data transfers from the processor, thus allowing it to handle other tasks simultaneously.

[0005] However, a significant limitation of this approach emerges in the aeronautical field. The specific requirements of this industry make it more difficult to operate and certify interrupt-based software architectures. In the aeronautical field, software architectures are increasingly oriented towards the use of deterministic and uninterruptible operating systems. This orientation aims to strengthen the overall robustness of the architecture and simplify the certification process, which is essential in this critical sector.

[0006] There is therefore a need for a solution that improves the performance of the prior art while having an uninterrupted architecture. Summary of the invention

[0007] The invention offers a solution to the problems mentioned above, by allowing, in an uninterruptible computer architecture, to have high-performance memory accesses between two devices connected by a high-speed, high-latency serial bus.

[0008] One aspect of the invention relates to a memory access method in a computer network included in an aircraft, the computer network comprising at least a first and a second device, the method comprising: • The first device sends at least one sequential access request to a memory location on the second device via a serial bus; the sequential access request must include a plurality of contiguous memory addresses. • Reception, by an address conversion module included in the network and connected to the first device via the serial bus, of the sequential access request, • For each address in the plurality of contiguous memory addresses, the network address conversion module converts the address into a converted address using predefined descriptors. • Emission, by the network address conversion module, of a request to access the memory of the second device, each access request including at least one converted memory address.

[0009] Thanks to the invention, the first device, for example a processor, performs sequential memory accesses. These sequential memory accesses are then converted upon arrival, that is, downstream of the serial bus separating the two devices, and therefore as close as possible to the second device, for example an input / output manager, which the first device wishes to access. This makes it possible, in particular, to use the full capacity of the serial bus by performing sequential memory accesses while respecting the memory architecture of the input / output managers, which require non-sequential memory accesses. The address conversion module, using predefined descriptors, is thus able to convert the contiguous address sequences required by the first device into fragmented, non-contiguous addresses corresponding to the actual location of the data required by the first device in the memory of the second device.

[0010] In addition to the characteristics mentioned in the preceding paragraph, the memory access method according to one aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • Each predefined descriptor among the predefined descriptors includes a number of contiguous addresses to convert, a converted starting address, and offset information to add to the converted starting address for obtain a next converted address corresponding to the next contiguous address. • Memory access is a memory read or a memory write. • The sequential access request is a memory write request, in which the sequential access request further includes at least one data segment to be written into the memory of the second device and in which the access request issued by the address conversion module includes the data segment to be written into the memory of the second device.

[0011] Another aspect of the invention relates to a system comprising at least a first and a second device, the system being included in an aircraft, the system being characterized in that it includes an address conversion module and in that it is configured to implement the memory access method according to the invention.

[0012] In addition to the characteristics mentioned in the preceding paragraph, the system according to one aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • The first device is a processor and the second device is an input / output manager, with the conversion module included in the input / output manager. • The processor is a central computing unit or a microcontroller included in a first physical component, and the input / output manager is an FPGA included in a second physical component, with the conversion module being included in the second physical component. • The system is a multi-chiplet component and the first device is a chiplet dedicated to computation, the second device is an input / output management chiplet, and in which the address conversion module is allocated to the input / output management chiplet. • the first device includes a first direct memory access controller of the first device and the second device includes a second direct memory access controller of the second device, the first direct memory access controller performing the step of issuing the sequential access request to the second direct memory access controller. • the system further includes a plurality of data acquisition devices connected to the second device. • The serial bus is mapped into the memory of the first device. • The serial bus is not of a type mapped into the memory of the first device. • The first device is configured to issue the access request according to a predefined protocol, the predefined protocol defining a start time and a size of memory space to be accessed, and • The conversion module is configured to decode the access request into the predefined protocol.

[0013] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0014] The figures are presented for illustrative purposes only and are in no way limiting of the invention. • Figure 1 shows a schematic representation of a system according to the invention, • Figure [Fig. 2] shows a schematic representation of a first embodiment of a process according to the invention, • Figure 3 shows a schematic representation of an address conversion in a method according to the invention, • Figure 4 shows a schematic representation of an address conversion method included in a method according to the invention, • Figure 5 shows a schematic representation comparing memory access with and without the implementation of a system and method according to the invention. • Figure 6 shows a schematic representation of a second embodiment of a method according to the invention, • Figure 7 shows a schematic representation of a first embodiment of a system according to the invention, • Figure 8 shows a schematic representation of a second embodiment of a system according to the invention, • Figure [Fig. 9] shows a schematic representation of a third embodiment of a system according to the invention. DETAILED DESCRIPTION

[0015] Unless otherwise specified, the same element appearing on different figures presents a unique reference.

[0016] Fig. 1 shows a schematic representation of a system according to a first aspect of the invention.

[0017] The system 10 according to the invention comprises a first device 11 and a second device 12. The system 10 according to the invention further comprises an address conversion module 13.

[0018] The first device 11 and the second device 12 each comprise a memory 111 and 121 respectively and a processor 112 and 122 respectively. When an action is lent to a device, this action is in fact implemented by the processor of that device, by executing instructions stored in the memory of the device, the execution of the instructions by the processor leading the device to implement the action lent to the device.

[0019] System 10 is a computer network formed by devices 11 and 12, but is also preferably included in a larger computer network comprising other computer devices. In particular, the invention relates to an aircraft computer network, aircraft computer networks being characterized in that they rely on operating systems executed by deterministic and uninterruptible processors; the invention addresses the technical problem while taking this constraint into account.

[0020] The invention enables the first device 11 to perform access requests to the memory 121 of the second device 12, via a serial bus 14. A serial bus is a type of computer bus configured to transmit data element by element, requiring serialization of information for transmission and a reverse operation for reception. This type of bus transmits data sequentially and is very common in recent architectures, particularly in aircraft computer networks. This invention makes it possible to maintain existing serial buses in the aircraft computer network while making the most of them. In the invention, the serial bus 14 can be, for example, of the PCI Express or Ethernet type, and can be parallel or internal to the electronic components.

[0021] The invention allows in particular better read and write performance than the prior art, the first device making sequential access requests via the serial bus 14, memory addresses included in these sequential access requests being converted by the address conversion module 13 to access in a non-sequential manner the fragmented memory locations in the memory 121 of the second device 12.

[0022] To obtain these effects, the invention relates more particularly to a memory access method, the access being required by the first device 11, destined for the second device 12, for access to the memory 121 of the second device 12.

[0023] By "memory access" is meant an operation performed in memory, at a particular memory location, accessible via a particular memory address. Such an operation is, for example, a read operation from the memory location at the specified memory address, that is, acquiring the data stored at that memory location, or a write operation in the memory location, that is, storing data at the memory location at the memory address specified. In a memory read operation, a memory access request is sent. In a memory write operation, a memory access request is sent along with the data segment to be stored at the specified memory location.

[0024] Figure 2 shows a schematic representation of a first embodiment of the method according to the invention, wherein memory access is a writing of memory. Figure 2 therefore schematically represents a first method 20, according to a first embodiment of the method according to the invention.

[0025] The memory access method 20 comprises a first step 21 of sending at least one write request, by the first device 11, to the memory 121 of the second device 12. According to the invention, the write request is a sequential access request, sent via the serial bus 14. The access request therefore respects the sequential format for which the serial bus is most efficient, guaranteeing better data transfer performance than in the prior art.

[0026] A "sequential access" request is a request comprising a plurality of contiguous memory addresses, that is, starting at a given starting memory address, and comprising a plurality of these memory addresses, the subsequent addresses of which are separated by a fixed increment. For example, and as shown in the left column of [Fig. 3], all memory addresses are contiguous, the sequence of memory addresses starting at memory address 0x00100, and comprising a plurality of memory addresses incremented by 1 up to address 0x00100. Thus, a single sequential access request comprises a plurality of contiguous memory addresses, allowing a single "burst" access to be performed from the point of view of the first device 11.

[0027] This sequential access request is sent on the serial bus 14 by the first device 11 and received, at a step 22 of the process 20, by the address conversion module 13. The address conversion module 13 is preferably a physical module, but can also, without departing from the invention, be a software module. This will be described in more detail later.

[0028] Upon receiving the sequential access request, the address conversion module 13 performs, in a step 23, the conversion of each memory address in the plurality of contiguous memory addresses included in the sequential access request into a destination address in the memory of the second device. To perform this conversion 23, the conversion module 13 stores or accesses a descriptor table, the descriptors defining how and to which destination address each address in a sequence of contiguous addresses is to be converted. To use this table, the address conversion module 13 implements an address conversion process 40 and access. An example of an address conversion and memory access process is shown in [Fig.4].

[0029] This conversion process 40 comprises a plurality of steps 41 to 56.

[0030] In a first step 41, the starting address of the contiguous memory address sequence of the access request is received and read, and a descriptor table address is deduced from it, from a predefined offset applied to the received address.

[0031] At step 42, the type of descriptor stored at the descriptor address is read.

[0032] In step 43, depending on the type of descriptor, one of steps 44 to 47 is put into artwork.

[0033] If the descriptor is of type "DUMP", the "dump" mode is implemented in step 44 and memory writes are ignored. This descriptor allows the final memory address to be indicated. Procedure 40 must then be repeated with a new sequential access request.

[0034] If the descriptor is of type "TARGET_ADDRESS", that is, "target address", step 45 is implemented, which is a step during which the conversion address is defined as a predefined fixed address in the descriptor. The process 40 then proceeds to the next descriptor in the descriptor table by incrementing the descriptor address in step 50.

[0035] If the descriptor is of type "NEXT_DESCRIPTOR_LENGTH_LIMIT", that is, "length limit of the next descriptor", step 46 is implemented. Step 46 then defines the value of a length limit parameter for the data segment to be written, the parameter value being a value contained within the descriptor of that type. Process 40 then proceeds to the next descriptor in the descriptor table by incrementing the descriptor address in step 50. The next descriptor of type "DATA_SEGMENT" will then be limited in size for writing and / or reading in memory by the length limit parameter.

[0036] Finally, if the descriptor is of type "DATA_SEGMENT", that is, if the descriptor corresponds to a data segment to be read or written, step 47 is implemented. In step 47, the length of the data segment, the offset, and the conversion address are defined based on the descriptor. An example is shown in the central column of [Fig. 3], which displays a descriptor table. For example, the descriptor table associated with address 0x0100 indicates that the most significant bit (MSB) is 0x00000, and that the first memory address ("data len" corresponding to the number of converted addresses, "start" corresponding to the starting address for conversion) of the contiguous memory address sequence must be converted to address 0x0500. The address 0x00100 received in the sequential access request is therefore converted to 0x00500. This same descriptor table then indicates that the next two addresses must be associated with addresses whose starting address is 0x0520, that is, memory addresses 0x00520 and 0x00521 respectively. Then, the next three addresses (data len = 3) are converted to addresses whose starting address is 0x05A0, with a most significant bit of 0x00000 and a stride of 4. This stride information depends on the type of the descriptor, also indicated in the descriptor table but not shown. Thus, the conversion addresses for the three addresses 0x00103, 0x00104, and 0x00105 are 0x005A0, 0x005A4, and 0x005A8, all separated by an offset of 4 symbol sizes on bus 14. The descriptor table then indicates a change in the most significant bit (MSB). Therefore, the next two addresses (data len = 2) are converted to addresses whose starting address is 0x10000. The conversion addresses for the two addresses 0x00106 and 0x00107 are thus 0x10000 and 0x10001.The descriptor table then indicates another change to the most significant bit (MSB). Thus, the next hundred addresses (data len = 100) are converted to addresses whose starting address is 0x70000. The conversion addresses of the next hundred addresses of the sequential access request therefore start at 0x7A000 and are incremented by 1.

[0037] To perform these conversions and change the descriptor (i.e., to move to the next descriptor), once the descriptor has been read, and the starting conversion address, offset, and segment length have been determined from the descriptor in step 47, step 48 includes a check that the length of the segment remaining to be written and / or read is not zero. If the length of the data segment remaining to be written and / or read is zero, the data segment length limit parameter is disabled in step 49, and the descriptor address in the descriptor table is incremented in step 50 to read the next descriptor, since the data segment has been completely written and / or read.

[0038] Conversely, if the length of the remaining segment to be written and / or read is not zero, step 51 is performed. Step 51 is a step called "run", which consists of applying the decoded address to the internal memory of the address conversion module or the device implementing the address conversion module.

[0039] Step 52 includes a check whether the data segment length limit parameter has been activated. If it has been activated (for example, because the previous descriptor was of type "NEXT_DESCRIPTOR_LENGTH_LIMIT"), step 53 checks whether this limit is 0. If this limit is 0, the access size limit defined by the length limit parameter has been reached, and the process proceeds directly to step 56. Conversely, if this limit is not 0, the size limit has not been reached, and the parameter value is decremented by a predefined value in step 54, and then step 55 is performed.

[0040] Similarly, if the length limit parameter has not been enabled, access to the conversion address is allowed in a step 55 of the execution of the required memory access (read and / or write).

[0041] In step 56, the length of the segment read from the descriptor is decremented to write and / or read the rest of the segment. The process then resumes in step 48 with the segment length decremented until the segment length reaches 0, or the value of the length limit parameter reaches 0.

[0042] This address conversion and memory access method 40 enables the execution of step 23 of the address conversion method 20, as well as step 24 of the method 20. Step 24 of the method 20 is a step in which the address conversion module 13 sends a memory access request to the second device 12, each access request including at least one converted memory address. This corresponds in particular to step 55 of the method 40, which performs the memory accesses at the conversion address for the data segments.

[0043] The invention therefore makes it possible, from a sequential access request to the memory of the second device 12 issued by the first device 11 via a serial bus 14, to convert, downstream of the bus 14, i.e. as close as possible to the second device 12, the sequence of contiguous memory addresses into fragmented memory addresses, i.e. into real memory addresses of the second device 12, in order to achieve efficient memory access.

[0044] The performance of the method and system according to the invention is shown in [Fig. 5]. Diagram A of [Fig. 5] shows a schematic representation of the number of memory accesses achievable with current architectures, i.e., in the state of the art. In contrast, the solution of the present invention makes it possible to perform a much greater number of accesses than the state of the art in the same time window, as shown in diagrams B and C, which respectively represent the memory accesses seen from the first device 11, and the memory accesses performed by the conversion module 13, i.e., actually performed in the memory of the second device 12.Indeed, contrary to the state of the art, the serial bus 14 is not a limiting factor for data exchange since sequential accesses are performed via this bus 14, which allows many successive accesses to the memory of the second device 12, even if the data in the memory of the second device 12 is not sequentially accessible.

[0045] In a second embodiment of the memory access method according to the invention, shown in [Fig. 6], the memory access performed is a read operation. The method 60 therefore comprises steps 21 to 24 of the method 20, and an additional step 61 of transmitting the data to the first device 11, the data having been read from the memory addresses specified in the memory 121 of the second device 12.

[0046] The methods 20 and 60 can be implemented by the system 10 of [Fig. 1]. More specifically, several embodiments of the system according to the invention will now be described.

[0047] As shown in [Fig. 7], the system 70 is a first embodiment of the system 10 according to the invention, configured to implement the memory access method according to the invention. This system 70 comprises the first device 11 and a second device 72. In this embodiment, the first device 11 is a processor, for example a CPU (Central Processing Unit) or a microcontroller. For example, the first device 11 is a QorlQ® T1042 type CPU, comprising memories 111, a core 112, a bus controller 113, a DMA controller 114 (Direct Access Memory), and an interconnect 115.

[0048] In this embodiment, the address conversion module 13 is included in the second device 72. Thus, the second device 72 differs from the second device 12 only in that it includes the address conversion module 13. In this embodiment, the second device 72 is an aircraft input / output manager. In the context of aircraft, the input / output manager 72 is designed to temporarily store data from aircraft acquisition devices. In [Fig. 7], devices 151 and 152 are data acquisition devices, for example, sensors. For example, in an onboard data acquisition system, the input / output manager may be responsible for collecting and routing data from sensors or other acquisition devices to the CPU or other system components.This temporary storage may be necessary to ensure the consistency and reliability of data before it is processed or transmitted to other systems on board the aircraft. Furthermore, the input / output manager 72 includes, for example, a function for acquiring discrete signal inputs (DSI) and generating discrete signal outputs (DSO), data which the input / output manager 72 stores in memory. It is this type of data, for example, that the processor 11 seeks to access by executing a memory access request. For example, the input / output manager 72 is an FPGA (Field-Programmable Gate Array).

[0049] In the embodiment of [Fig. 7], the two devices 11 and 72 are contained within different physical components; that is, they are distinct physical devices. The address conversion module 13 is then, for example, a software module implemented by the FPGA 72. The two devices 11 and 72 are connected via the serial bus 14, for example, in PCI Express® format. The CPU 11 can then use its DMA controller 114 to perform large sequential access requests, for example, requests of a size greater than or equal to 64 bytes, thus providing high performance. The addresses of these access requests will then be converted into fragmented addresses for the memory of the input / output manager 12.

[0050] Figure 8 shows a schematic representation of a second embodiment of the system according to the invention. The system 80 of Figure 8 comprises a first device 81, and a second device 82 which differs from the first device 81 only in that it includes the address conversion module 13. In this embodiment, both devices are chiplets, that is, "fragmented chips," meaning electronic chips dedicated to a specific function. Thus, the chiplet 81 is dedicated to a computational function. In this respect, it is a computational chiplet. Chiplet 82 is dedicated to an input / output management function.In this respect, it is an aircraft input / output management chiplet. Chiplets 81 and 82 are linked in communication via a chiplet communication bus 14.

[0051] The chiplet 81 can then use its DMA controller 114 to perform large sequential access requests, for example preferably of size greater than or equal to 64 bytes, therefore efficient, access requests whose addresses will then be converted into fragmented addresses for the memory of the input / output chiplet 82.

[0052] Figure 9 shows a schematic representation of a third embodiment of the system according to the invention. The system 90 shown in Figure 9 comprises two devices 91 and 92. The first device 91 is a QorlQ® T1042 type CPU, comprising memories 111, a core 112, a bus controller 113, a DMA controller 114, and an interconnect 115. In this embodiment, the distinctive feature is that the second device 92 also includes a DMA controller 123. The second device 92 is, for example, an FPGA, an input / output manager for an aircraft, making it possible to avoid read accesses, which are more bandwidth-intensive. The two DMA controllers 114 and 123 perform write memory accesses to the other device: the DMA 114 of the CPU 91 writes to the DMA 123 of the FPGA 92 and the DMA 123 of the FPGA 92 writes to the DMA 114 of the CPU 91.This finds an interesting application, for example, in imaging, the second device 92 being a camera including the DMA controller 123, which improves read bandwidth. Indeed, the camera 92 then writes directly to the CPU 91, thus eliminating reads from the CPU 91 to the camera 92 and therefore reducing bandwidth.

[0053] In an embodiment of the system 10 compatible with the three embodiments of the system described previously in [Fig. 6] to 9, the bus is a memory-mapped bus, which makes it possible to avoid the need for a communication protocol In particular, memory addresses are converted on the fly upon receipt of sequential access requests by the address conversion module 13. A "memory mapped" bus is understood here as a bus enabling the memory addresses of the second device 12 to be made directly accessible by the master of the bus, i.e. by the first device 11.

[0054] In another embodiment of the system 10 compatible with the three system embodiments described previously in [Fig. 6] to [Fig. 9], the bus is a non-memory-mapped bus, for example Ethernet or RS422, which necessitates the implementation of a communication protocol between the first device 11 and the second device 12. Indeed, the memory addresses of the second device 12 are then not directly accessible by the first device 11. The first device, when it issues a sequential access request in step 21, must then issue its request in a protocol indicating a starting address and the size of the memory space to be accessed (read or write). Similarly, during read operations, the second device 12 sends its data segments in the predefined protocol, allowing identification of the data segments, their starting point, and their size.For example, in Ethernet, the second device 12 can be configured to automatically send frames according to a predefined protocol, identifying the data segments sent, thus avoiding read requests from the first device 11.

Claims

Demands

1. A method (2) for accessing memory in a computer network included in an aircraft, the computer network comprising at least a first (11) and a second (12) device, the method (2) comprising: - Sending (21) at least one sequential access request, by the first device (11), to a memory of the second device (12) via a serial bus (14), the sequential access request comprising a plurality of contiguous memory addresses, - Receiving (22), by an address conversion module (13) included in the network and connected to the first device (11) via the serial bus (14), the sequential access request, - For each address of the plurality of contiguous memory addresses, conversion (23), by the address conversion module (13) of the network, of the address into a converted address from predefined descriptors, - Sending (24), by the address conversion module (13) of the network,of a memory access request from the second device (12), each access request comprising at least one converted memory address.

2. A memory access method (2) according to the preceding claim, wherein each predefined descriptor among the predefined descriptors comprises a number of contiguous addresses to be converted, a converted starting address, and an offset information to be added to the converted starting address to obtain a next converted address corresponding to the next contiguous address.

3. Memory access method (2) according to any one of the preceding claims wherein the memory access is a memory read or a memory write.

4. Memory access method according to claim 3 wherein the sequential access request is a memory write request, wherein the sequential access request further includes at least one data segment to be written into the memory of the second device (12) and wherein the access request issued by the address conversion module includes the data segment to be written into the memory of the second device (12).

5. System (10) comprising at least a first (11) and a second (12) device, the system (10) being included in an aircraft, the system (10) being characterized in that it comprises an address conversion module (13) and in that it is configured to implement the memory access method (2) according to any one of the preceding claims.

6. System (10) according to the preceding claim in which the first device (11) is a processor and the second device (12) is an input / output manager, the address conversion module (13) being included in the input / output manager.

7. System (10) according to claim 6 wherein the processor is a central computing unit or a microcontroller included in a first physical component, and wherein the input / output manager is an FPGA included in a second physical component, the conversion module (13) being included in the second physical component.

8. System (10) according to claim 5 wherein the system is a multi-chiplet component and wherein the first device (11) is a chiplet dedicated to computing, the second device (12) is an input / output management chiplet, and wherein the address conversion module (13) is allocated to the input / output management chiplet.

9. System (10) according to any one of claims 5 to 8 wherein the first device (11) comprises a first direct memory access controller of the first device (11) and the second device comprises a second direct memory access controller of the second device (12), the first direct memory access controller performing the transmission step (24) of the sequential access request to the second direct memory access controller.

10. System (10) according to any one of claims 5 to 9 further comprising a plurality of data acquisition devices connected to the second device (12).

11. System (10) according to any one of claims 5 to 10 wherein the serial bus is mapped into the memory of the first device (11).

12. System (10) according to any one of claims 5 to 10 wherein: - the serial bus (14) is not of a type memory-mapped to the first device (11), the first device (11) is configured to issue (24) the access request according to a predefined protocol, the predefined protocol defining a start and size of memory space to be accessed, and The conversion module (13) is configured to decode the access request into the predefined protocol.

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