Manufacturing process for optoelectronic devices

Abstract

Method for manufacturing optoelectronic devices The present description relates to a method for manufacturing optoelectronic devices, comprising the following successive steps: a) forming, by epitaxial growth on a growth substrate, an active diode stack (101); b) transferring, on a first transfer substrate, the active diode stack; c) removing the growth substrate; d) forming, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes (131); and e) transferring, on a second transfer substrate (133), the elementary vignettes each comprising a part of the active diode stack. Figure for abstract: Fig. 1F

Description

Title of the invention: Method for manufacturing optoelectronic devices Technical field

[0001] The present description relates generally to the field of optoelectronic devices. It relates more particularly to a method for manufacturing optoelectronic devices each comprising a plurality of semiconductor diodes, for example based on gallium nitride (GaN) or indium-gallium nitride (InGaN), and an electronic circuit for controlling these diodes. Prior art

[0002] Emissive display devices comprising a matrix of gallium nitride-based light-emitting diodes (LEDs) and an electronic control circuit, enabling the LEDs to be individually controlled to display images, have already been proposed. The use of gallium nitride-based LEDs has in particular made it possible to manufacture micro-displays having high luminance values ​​and resolutions.

[0003] In order to produce such devices, it may be provided to manufacture the control circuit and the LED matrix separately, then to connect them to each other. The LED matrix of the device may in particular be manufactured by a method comprising steps of forming an active stack of LEDs on a substrate, delimiting emissive zones by photolithography then etching the active stack of LEDs, and producing anode and cathode contacts of each emissive zone and metal lines connected to pads making it possible to connect the anodes and cathodes of the emissive zones to the control circuit. Such methods are described in particular in international application No. WO2017 / 068029 and in French patent No. FR3079350 (DD18591 / B16845), respectively filed and previously obtained by the applicant.

[0004] Once the LED matrix has been produced, the latter is then connected to the control circuit by an operation known as wire bonding, by the use of solder balls or metal pillars, or by hybrid bonding of the control circuit to the LED matrix, i.e. by stacking and connecting these two elements to each other. Examples of hybrid bonding are described in international application No. WO2017 / 068029 and in French patent No. FR3079350 mentioned above.

[0005] However, a disadvantage of this method lies in the need to precisely align the control circuit and the LED matrix during the assembly step of these two elements, so that each LED is correctly positioned on a corresponding metal pad in the control circuit. This alignment is particularly difficult to achieve when the pixel pitch decreases, and constitutes a barrier to increasing the resolution and / or the integration density of the pixels.

[0006] In order to overcome this drawback, a method for manufacturing optoelectronic devices comprising the successive steps below has also been proposed, in particular in international application No. WO2017 / 194845 (DD 16946 / B15015) previously filed by the applicant: a) producing the control circuit in the form of an integrated circuit comprising, on one side, a plurality of metal pads intended to be connected to the LEDs to allow individual control of the current flowing in each LED; b) transferring, on the face of the control circuit comprising the metal pads, an active stack of LEDs extending continuously over the entire surface of the control circuit so as to connect a semiconductor layer of the active stack of LEDs to the metal pads of the control circuit; and c) structure the active LED stack to delimit and isolate the different LEDs of the device from each other.

[0007] An advantage of this method is that, during the step of transferring the active LED stack onto the control circuit, the positions of the different LEDs of the device in the active LED stack are not yet defined. The transfer step therefore does not present a strong constraint in terms of alignment accuracy. The delimitation of the different LEDs in the active stack can then be carried out by methods of structuring a substrate and depositing insulating and conductive layers on a substrate, which offer a significantly higher alignment accuracy than that which can be achieved when transferring from one substrate to another.

[0008] In existing processes, the active LED stack is generally formed, by epitaxial growth, on a sapphire wafer. Although this makes it possible to produce high-performance LEDs, the use of sapphire wafers has the disadvantage of generating high manufacturing costs. Furthermore, sapphire wafers have a diameter equal to approximately 100 or 150 mm, while the processes used for producing control circuits are more suited to silicon wafers having a larger diameter, for example equal to approximately 300 mm. In an attempt to solve these problems, active LED stacks based on gallium nitride have been produced on silicon substrates, for example on silicon wafers with a diameter substantially equal to that of the wafers used to produce the control circuits.However, the LEDs thus formed present, for certain emission wavelengths, particularly in green and red, lower performances than those obtained using . sapphire plates.

[0009] European patent application No. EP 4016594 describes an alternative approach consisting of reconstituting a large diameter wafer by transferring, onto a first silicon wafer typically having a diameter equal to approximately 200 or 300 mm, chips obtained by cutting a second sapphire wafer with a diameter strictly smaller than that of the first wafer and on which an active stack of LEDs has previously been formed. However, this approach has the disadvantage of comprising a step of cutting the second wafer which is particularly complex and expensive to produce, sapphire being a very hard material and the cutting of which causes the formation of chips at the edge of the chip. Furthermore, the method implements, after transferring the chips onto the first wafer, a step of removing the pieces of the second wafer resulting from the previous cutting step.This removal step, carried out by laser lift-off, is difficult to control because the first wafer contains electronic circuits, for example of the CMOS type (from the English "Complementary Metal-Oxide-Semiconductor"), which risk being irreversibly damaged by exposure to a laser beam.

[0010] The gallium nitride-based layers epitaxially grown on the second wafer are also highly stressed, due to the difference in thermal expansion coefficient between sapphire and gallium nitride. During epitaxial growth, carried out at high temperature, the gallium nitride-based layer(s) of the active LED stack are epitaxially grown on a thick gallium nitride buffer layer allowing a lattice parameter matching between the sapphire of the growth substrate and the gallium nitride of the active stack. The stresses are thus progressively released inside the buffer layer, so that the layers of the active LED stack are not, or are only slightly, stressed at the epitaxial growth temperature of these layers. When the second wafer is cooled, the stresses exerted in the buffer layer become highly compressive.After the pieces of the second, very rigid wafer have been removed, the stresses of the gallium nitride layer are transmitted to the first wafer. This causes very significant deformations of the first wafer, for example of the order of several hundred micrometers, therefore making the processing of the reconstituted substrate incompatible with standard microelectronics equipment.

[0011] European patent No. EP 3780123 (DD 19602 / B18565), previously obtained by the applicant, describes yet another approach consisting of performing two full wafer transfers before cutting, thus avoiding cutting the sapphire, followed by a chip-to-wafer transfer by non-aligned bonding of the type described in the application in- International No. WO2017 / 194845 mentioned above. Summary of the invention

[0012] There is a need to overcome all or part of the disadvantages of existing optoelectronic device manufacturing processes.

[0013] For this, one embodiment provides a method for manufacturing optoelectronic devices, comprising the following successive steps: a) forming, by epitaxial growth on a growth substrate, an active diode stack; b) transferring, onto a first transfer substrate, the active diode stack; c) remove the growth substrate; d) forming, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes; and e) transferring, onto a second transfer substrate, the elementary vignettes each comprising a part of the active diode stack.

[0014] According to one embodiment, the growth substrate or the transfer substrate is heated, preferably to a temperature greater than or equal to 40°C, more preferably greater than or equal to 70°C.

[0015] According to one embodiment, in step b), the growth substrate and the transfer substrate are heated, preferably to a temperature greater than or equal to 40°C.

[0016] According to one embodiment, in step b), the active diode stack is fixed on the first transfer substrate by direct bonding of a first bonding layer, previously deposited on the face of the active diode stack opposite the growth substrate, with a second bonding layer, previously deposited on the first transfer substrate.

[0017] According to one embodiment, in step b), the surfaces of the first and second bonding layers intended to be brought into contact are activated prior to fixing.

[0018] According to one embodiment, the first and second bonding layers are made of amorphous silicon.

[0019] According to one embodiment, the first and second bonding layers are metallic layers, preferably made of titanium.

[0020] According to one embodiment, in step e), the elementary vignettes are fixed on the second transfer substrate by direct bonding of a third bonding layer, previously deposited on the face of the active diode stack opposite the first transfer substrate, with a fourth bonding layer, previously deposited on the second transfer substrate.

[0021] According to one embodiment, the third and fourth bonding layers are in silicon oxide.

[0022] According to one embodiment, the method further comprises, after step e), the following step: f) transferring the assembly comprising the second transfer substrate and the parts of the active diode stack onto an active substrate comprising integrated control circuits.

[0023] According to one embodiment, in step f), the parts of the active diode stack and the second transfer substrate are fixed to the active substrate by bonding a first insulating layer, previously deposited on the face of the active diode stack opposite the second transfer substrate, and first contact recovery elements, located in the first insulating layer, with respectively a second insulating layer, previously deposited on the active substrate, and second contact recovery elements, located in the second insulating layer.

[0024] According to one embodiment, the method further comprises, after step e), a step g) of etching the elementary vignettes so as to compensate for a misalignment of the elementary vignettes relative to the second transfer substrate.

[0025] According to one embodiment, the method further comprises, after step g), a step h) of depositing an insulating layer filling spaces extending laterally between the elementary vignettes and then removing parts of the insulating layer located directly above the elementary vignettes.

[0026] According to one embodiment, the growth substrate is made of sapphire.

[0027] According to one embodiment, the active diode stack comprises nitride of gallium.

[0028] According to one embodiment, the active diode stack is a light-emitting diode stack comprising, in order from the growth substrate, first and second semiconductor layers of opposite conductivity types. Brief description of the drawings

[0029] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0030] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF], [Fig.lG], [Fig.lH], [Fig.II], [Fig.U], [Fig.lK], [Fig.IL] and [Fig.lM] are schematic and partial side and sectional views illustrating structures obtained at the end of steps of an example of an embodiment of a method for manufacturing optoelectronic devices;

[0031] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] are schematic and partial side and sectional views illustrating structures obtained at the end of steps of a alternative implementation of the method of figures IA to IM; and

[0032] [Fig.3A], [Fig.3B], [Fig.3C] and [Fig.3D] are respectively a top view and side and sectional views, schematic and partial, illustrating structures obtained at the end of steps of another variant of implementation of the method of figures 1A to 1M. Description of the embodiments

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the applications likely to benefit from the described optoelectronic devices have not been detailed, the described embodiments being compatible with all or most applications implementing at least one optoelectronic device, possibly subject to adaptations within the scope of the person skilled in the art upon reading this description. Furthermore, the production of an integrated circuit for controlling semiconductor diodes has not been detailed, the described embodiments being compatible with the usual structures and manufacturing methods of such control circuits.Furthermore, the composition and arrangement of the different layers of an active stack of semiconductor diodes have not been detailed, the embodiments described being compatible with the usual active stacks of semiconductor diodes, in particular based on gallium nitride.

[0035] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0037] Unless otherwise specified, the expressions “about”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably to within 5%.

[0038] In the following description, the qualifiers “insulator” and “conductor” mean respectively, unless otherwise specified, electrically insulating and electrically conductive.

[0039] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF], [Fig.lG], [Fig.lH], [Fig.II], [Fig.U], [Fig.lK], [Fig.IL] and [Fig.lM] are schematic and partial side and sectional views illustrating structures obtained at the end of steps of an example of an embodiment of a method for manufacturing optoelectronic devices.

[0040] Figures 1A to 1M illustrate more particularly the manufacture of an optoelectronic display device comprising an LED matrix and an electronic control circuit making it possible to individually control the LEDs to display images.

[0041] [Fig. 1A] illustrates a structure obtained at the end of steps of forming an active stack of LEDs 101 on the upper face, in the orientation of [Fig. 1A], of a growth substrate 103. The active stack of LEDs 101 is for example based on gallium nitride (GaN).

[0042] The active LED stack 101 is formed by epitaxial growth from the upper face of the growth substrate 103. The growth substrate 103 is for example a wafer or a piece of wafer. Preferably, the growth substrate 103 is made of sapphire. Sapphire has the advantage of allowing the growth of a very high-quality gallium nitride LED stack.

[0043] In the example shown, the active LED stack 101 comprises, in order from the upper face of the growth substrate 103, an N-type doped gallium nitride layer 105, an emissive layer 107, and a P-type doped gallium nitride layer 109. The emissive layer 107, or active layer, comprises for example a stack of several emissive layers forming quantum wells, for example layers based on gallium nitride, indium nitride (InN), indium-gallium nitride (InGaN), aluminum-gallium nitride (AlGaN), aluminum nitride (AIN), aluminum-indium-gallium nitride (AlInGaN), gallium phosphide (GaP), aluminum-gallium phosphide (AlGaP), phosphide aluminum-indium-gallium (AlInGaP), or any combination of one or more of these materials.

[0044] As a variant, the emissive layer 107 may be an intrinsic gallium nitride layer, i.e. not intentionally doped, for example having a concentration of residual donor species of between 1015 and 1018 at / cm3, for example of the order of 1017 at / cm3.

[0045] In the illustrated example, the lower face of the emissive layer 107 is in contact with the upper face of the layer 105, and the upper face of the emissive layer 107 is in contact with the lower face of the layer 109. In practice, a stack of one or more buffer layers (not shown), for example an undoped gallium nitride layer, may form an interface between the growth substrate 103 and the gallium nitride layer 105.

[0046] For example, the thickness of the layer 105 is between 0.2 and 2 μm, for example of the order of 1 μm. For example, the thickness of the layer 107 is between 30 and 300 nm, for example of the order of 100 nm. For example, the thickness of the layer 109 is between 5 and 300 nm, for example of the order of 100 nm. The active stack of LEDs 101 extends for example continuously and over a uniform thickness over the entire upper face of the growth substrate 103.

[0047] The structure of [Fig. 1A] further comprises, on the upper face of the active LED stack 101, a metal layer 111. In the example shown, the metal layer 111 is deposited on and in contact with the upper face of the gallium nitride layer 109. The metal layer 111 is for example deposited by implementing a vacuum deposition technique, for example by physical vapor deposition (PVD), by vacuum sputtering, by chemical vapor deposition (CVD), or by vacuum evaporation deposition. The metal layer 111 provides in particular a function of resuming electrical contact on the semiconductor layer 109 of the LED stack 101. The metal layer 111 can also provide a function of optical reflector, or mirror, and / or a function of barrier to the diffusion of metallic elements.

[0048] By way of example, the metal layer 111 is made up of a stack of several distinct metal layers (not detailed in the figures) comprising, in order from the upper face of the semiconductor layer 109: - a first metallic layer, for example made of a transparent and conductive oxide such as indium-tin oxide (ITO), in contact with the upper face of the semiconductor layer 109 and ensuring the resumption of an electrical contact on the semiconductor layer 109; - a second metal layer, for example titanium nitride (TiN), in contact with the upper face of the first metal layer, the second metal layer forming a barrier to the diffusion of metallic elements; and - a third metal layer, for example made of aluminum, in contact with the upper face of the second metal layer, the third metal layer having an optical reflector function.

[0049] The thickness of the first metal layer is for example adjusted so that the distance between the quantum well of the emissive layer 107 closest to the layer 109 and the upper face of the second metal layer makes it possible to obtain constructive interference of the light in the structure. This thus allows an ex- optimal light traction.

[0050] By way of example, the first metal layer has a thickness of between 20 and 100 nm, for example equal to approximately 60 nm. By way of example, the second metal layer has a thickness of between 1 and 10 nm, for example equal to approximately 5 nm. By way of example, the third metal layer has a thickness of between 100 and 200 nm, for example equal to approximately 100 nm.

[0051] As a variant, the metal layer 111 may consist of any stack of layers of a transparent and conductive oxide, for example ITO, and / or layers based on a metal, a metal alloy or a metal oxide, for example based on nickel, nickel oxide, nickel aluminide, aluminum, silver, platinum, etc.

[0052] [Fig.lB] illustrates a structure obtained at the end of a subsequent step of forming a bonding stack 113 on the upper face of the metal layer 111 of the structure of [Fig.lA].

[0053] The bonding stack 113 is for example chosen to allow hot bonding using a surface activated bonding (SAB) method or an atomic diffusion bonding (ADB) technique, and subsequent removal of the material used for bonding without damaging the semiconductor layer 109. For example, subsequent removal of the material used for bonding may be carried out by wet etching methods, for example by exposure to hydrofluoric acid and / or nitric acid, or by dry etching, for example by deep reactive ion etching (DRIE) using for example sulfur hexafluoride (SF6).

[0054] By way of example, the bonding stack 113 comprises, in order from the upper face of the metal layer 111, an insulating layer 115, an optional silicon nitride (SiN) layer 117, and a bonding layer 119. In the illustrated example, the lower face of the layer 117 is in contact with the upper face of the layer 115, and the upper face of the layer 117 is in contact with the lower face of the layer 119. The layer 115 comprises, for example, at least one layer made of an oxide, a nitride or an oxynitride. By way of example, the layer 115 is made of silicon oxide (SiO2), silicon nitride or silicon oxynitride (SiON). As a variant, the layer 115 may be an etching stop layer consisting for example of a titanium layer, having for example a thickness of the order of 10 nm, coated with a titanium nitride layer, having for example a thickness of the order of 50 nm.

[0055] The bonding layer 119 is for example made of amorphous silicon (a-Si).

[0056] For example, the layer 115 has a thickness of between 300 and 600 nm. For example, layer 117 has a thickness of the order of 200 nm. For example, layer 119 has a thickness of the order of 20 nm.

[0057] [Fig.1C] illustrates a structure obtained following subsequent steps of transferring and fixing the active stack of LEDs 101 to the upper face of a temporary transfer substrate 121, or handle, then removing the growth substrate 103.

[0058] Beforehand, a bonding layer 123 is for example formed on the upper face, in the orientation of [Fig.1C], of the temporary transfer substrate 121. The substrate 121 is for example a wafer or a piece of wafer made of a semiconductor material, for example silicon. The substrate 121 has for example lateral dimensions substantially equal to those of the growth substrate 103.

[0059] The bonding layer 123 is for example made of the same material as the bonding layer 119, for example amorphous silicon. The bonding layer 123 has for example a thickness substantially identical to that of the bonding layer 119, for example of the order of 20 nm. The bonding layer 123 extends for example continuously over the entire upper face of the substrate 121. Depending on a desired surface state, the bonding layer 123 can be subjected to a planarization operation prior to the transfer step.

[0060] During the transfer step, the assembly comprising the growth substrate 103, the active LED stack 101, the metal layer 111 and the bonding stack 113 can be turned over and attached to the temporary transfer substrate 121 so as to bring the upper face (in the orientation of [Fig. 1B]) of the bonding layer 119 into contact with the upper face of the bonding layer 123. In this example, the fixing of the active LED stack 101 on the temporary transfer substrate 121 is obtained by direct bonding of the lower face (in the orientation of [Fig. 1C]) of the bonding layer 119 onto the upper face of the bonding layer 123. The expression “direct bonding” here means that the bonding is a spontaneous bonding without the presence of a fluid layer, for example a layer of glue, on the surface. Although this is a spontaneous bond, pressure may be applied at the time of bonding.

[0061] By way of example, the bonding is more precisely a covalent bonding under ultra-high vacuum with temperature control of the substrates 103 and 121. The surfaces intended to be brought into contact are for example previously activated, for example by bombardment of argon atoms having an energy of the order of 200 eV until reaching a dose of the order of 1015 at / cm2. This activation is for example carried out by implementing the SAB technique previously mentioned. As a variant, the bonding by surface activation (SAB) can be replaced by bonding by atomic diffusion ("Atomic Diffusion Bonding" - ADB, in English) with a deposition under ultra-high vacuum of amorphous silicon of low thickness, for example between 1 and 10 nm. This layer can advantageously replace the previously deposited on surfaces.

[0062] Prior to bringing the two bonding surfaces into contact, at least one of the substrates—among the growth substrate 103 and the temporary transfer substrate 121—is for example heated. For example, one of the substrates 103, 121 is heated to a temperature approximately 20°C or approximately 50°C higher than ambient temperature, for example a temperature greater than or equal to 40°C or greater than or equal to 70°C. In a case where the growth substrate 103 has a coefficient of thermal expansion strictly greater than that of the layer 105 and where the layer 105 has a coefficient of thermal expansion strictly greater than that of the temporary transfer substrate 121, the substrates 103 and 121 are advantageously heated to different temperatures, the heating temperature of the substrate 103 being for example strictly greater than that of the substrate 121.Heating the growth substrate 103 makes it possible to relax the stresses in the layer 105 because this makes it possible to approach the growth temperature. Once the bonding has been carried out and the structure has cooled to room temperature, the difference in the coefficient of thermal expansion between the materials of the substrate 121 and the substrate 103 causes an increase in the stress in the substrates 103 and 121. At the end of the step of removing the growth substrate 103, the layer 105 will be less stressed, therefore will cause less deformation of the transfer substrate 121 due to the difference in coefficients of thermal expansion between the layer 105 and the temporary transfer substrate 121. The choice of the temperatures to which the substrates 103 and 121 are brought before bonding is for example conditioned by the search for a compromise between two objectives: . - maintain the integrity of the structure when returning to room temperature, because if excessive stresses are imposed between the substrate 121 and the substrate 103 it is possible to reach the breaking limit of the materials; and - obtain a low warpage (“bow”, in English) of the transfer substrate 121 after removal of the growth substrate 103, for example less than 100 or 120 pm so as to allow the processing of the structure by standard microelectronic equipment, in particular dry etching equipment of the RIE (“Reactive Ion Etching” - reactive ion etching, in English) or ICP (“Inductively Coupled Plasma” - inductively coupled plasma, in English) type.

[0063] By way of example, in the case where the substrate 103 has a coefficient of thermal expansion strictly greater than that of the layer 105 and where the layer 105 has a coefficient of thermal expansion strictly greater than that of the substrate 121, the growth substrate 103 is heated to a temperature of between 95 and 150°C, and the transfer substrate 121 is heated to a temperature of the order of 40°C. As a variant, the transfer substrate 121 may not be heated and may, for example, be kept at room temperature, for example at about 20°C. Depending on the materials from which the substrates 103 and 121 are made, the transfer substrate 121 may, as a variant, be heated to a temperature higher than that of the growth substrate 103, the growth substrate in this case being able to be heated or not. This corresponds, for example, to a case in which the substrate 103 has a coefficient of thermal expansion strictly lower than that of the substrate 121.

[0064] Alternatively, the growth substrate 103 and the temporary transfer substrate 121 are heated, for example to a temperature approximately 20 or 25°C higher than ambient temperature. For example, the substrates 103 and 121 are each heated to a temperature greater than or equal to 40 or 45°C.

[0065] The removal of the growth substrate 103 is for example carried out by implementing a laser lift-off (LLO) technique during which a laser beam is projected through the substrate 103 from its face opposite the active stack of LEDs 101. In the case where the temporary transfer substrate 121 has warping following the transfer and fixing of the active stack of LEDs 101, the laser beam is for example controlled so as to perform a spiral scan rather than a line-by-line scan. The laser lift-off step is for example followed by a step of removing gallium balls formed on the upper face of the layer 105 under the action of the laser, for example by wet treatment with hydrochloric acid or hot water.

[0066] In the example shown, the layer 105 has been thinned, for example by RIE or ICP on the side of its upper face, in the orientation of [Fig.1C].

[0067] [Fig. 1D] illustrates a structure obtained at the end of subsequent steps of forming another bonding stack 125 on the upper face of the semiconductor layer 105 of the structure of [Fig. 1C].

[0068] By way of example, the bonding stack 125 comprises, in order from the upper face of the semiconductor layer 105, an etch stop layer 127, for example made of silicon nitride, and a bonding layer 129, for example made of silicon oxide. In the example shown, the lower face of the layer 127 is in contact with the upper face of the layer 105, and the upper face of the layer 127 is in contact with the lower face of the layer 129. By way of example, the etch stop layer 127 has a thickness equal to approximately 150 nm. By way of example, the bonding layer 129 has a thickness of the order of 600 nm.

[0069] Furthermore, during this step, the upper face of the bonding layer 129 is for example planarized, for example by CMP (from the English “Chemical and Me-chanical Polishing”).

[0070] [Fig.lE] illustrates a structure obtained at the end of a subsequent step of cutting the structure of [Fig.lD] into a plurality of elementary vignettes 131. More precisely Specifically, the assembly comprising the temporary transfer substrate 121, the bonding layer 123, the bonding stack 113, the metal layer 111, the active LED stack 101 and the bonding stack 125 is cut into a plurality of elementary vignettes 131.

[0071] In the example shown, each sticker 131 comprises parts of the temporary transfer substrate 121, the bonding layer 123, the bonding stack 113, the metal layer 111, the active LED stack 101 and the bonding stack 125. For example, the cutting of the stickers 131 is carried out by sawing. The stickers 131 have, for example, identical dimensions.

[0072] Advantageously, a prior step of inspecting the structure of [Fig. 1D] can be provided so as to detect epitaxial defects. The cutting can then be implemented so as to concentrate the defects in order to subsequently select the vignettes 131 which have low defect rates.

[0073] [Fig. 1F] illustrates a structure obtained at the end of subsequent steps of transferring and fixing the stickers 131 on the upper face of a temporary transfer substrate 133, or handle, then removing the temporary transfer substrate 121 and the bonding layers 119 and 123.

[0074] Beforehand, a bonding layer 135 is for example formed on the upper face, in the orientation of [Fig. 1F], of the temporary transfer substrate 133. The substrate 133 is for example a wafer or a piece of wafer made of a semiconductor material, for example silicon. The substrate 133 has for example lateral dimensions strictly greater than those of the growth substrate 103.

[0075] The bonding layer 135 is for example made of the same material as the bonding layer 129, for example silicon oxide. The bonding layer 135 has for example a thickness substantially identical to or less than that of the bonding layer 129, for example of the order of 200 nm. The bonding layer 135 extends for example continuously over the entire upper face of the substrate 133.

[0076] During the transfer step, the stickers 131 can be turned over and placed on the temporary substrate 133 so as to bring the lower face (in the orientation of [Fig. 1F]) of the bonding layer 129 into contact with the upper face of the bonding layer 135. In this example, the fixing of the active LED stack 101 on the temporary transfer substrate 133 is obtained by direct bonding of the lower face (in the orientation of [Fig. 1F]) of the bonding layer 129 on the upper face of the bonding layer 135. The direct bonding of the stickers 131 on the temporary transfer substrate 133 is for example a molecular bonding, a thermocompression bonding, or even a eutectic bonding.

[0077] The parts of the transfer substrate 121 and of the bonding layers 119 and 123 included in each vignette 131 are for example then removed by grinding.

[0078] [Fig. 1G] illustrates a structure obtained following subsequent steps of depositing an encapsulation layer 137, depositing an insulating passivation layer 139, and planarizing the structure.

[0079] In the example shown, the encapsulation layer 137 is deposited on the side of the upper face of the structure of [Fig. 1F]. In this example, the layer 137 covers the lateral faces and the upper faces of the vignettes 131. The layer 137 is then, after deposition, for example more precisely located on and in contact with the upper faces of the parts of the layer 117 (or of the layer 115, in the case where the layer 117 is omitted) and on and in contact with the lateral faces of the bonding stack 125, of the active LED stack 101, of the metal layer 111, of the layer 115 and of the layer 117. The encapsulation layer 137 is for example intended to protect the lateral faces of the vignettes 131 against infiltration of liquids used during subsequent wet etching steps.

[0080] For example, the encapsulation layer is made of silicon nitride.

[0081] In the example illustrated, the insulating passivation layer 139 is then deposited over the entire upper face of the structure. The layer 139 is for example deposited over a thickness greater than the cumulative thickness of the bonding stack 125, the active LED stack 101, the metal layer 111, the layer 115 and the layer 117. The layer 139 is for example made of an oxide, for example silicon oxide. By way of example, the layer 139 has a thickness of the order of a few micrometers, for example equal to approximately 3 or 4 μm. The layer 139 is for example then planarized, for example by CMP, so as to obtain an assembly having a substantially flat upper face. The planarization is for example carried out with a stop on the layer 117. The layer 117 is for example then removed by etching.For example, at the end of the planarization step, the upper face of the insulating layer 115 is flush with the upper face of the insulating passivation layer 139.

[0082] [Fig. 1H] illustrates a structure obtained at the end of a subsequent step of delimitation and individualization of a plurality of elementary LEDs in each vignette 131.

[0083] In the example shown, trenches 141 are formed in the LED stack 101. In this example, each trench extends vertically, from the upper face of the insulating layer 115, through the conductive layer 111, through the semiconductor layers 109 and 107, and is interrupted in the thickness of the layer 105. By way of example, the trenches 141 are produced by etching using the material of the layer 115 as a hard mask.

[0084] [Fig.II] illustrates a structure obtained following subsequent steps of depositing another insulating passivation layer 143 and forming trenches 145 and vias 147.

[0085] In the example shown, the insulating passivation layer 143 is deposited over the entire upper face of the structure. The layer 143 is for example deposited conformally in the trenches 141, for example by a method of the ALD (Atomic Layer Deposition) or PECVD (Plasma-Enhanced Chemical Vapor Deposition) type. The layer 143 is for example made of an oxide, for example aluminum oxide, of a nitride, for example silicon nitride or aluminum nitride, or of a stack of layers made of these materials. The layer 143 is for example then etched anisotropically so as to uncover the bottom of the trench 141, for example by dry etching of the RIE or ICP type.

[0086] In the illustrated example, the trenches 145 are formed in the extension of the trenches 141 previously produced. The trenches 145 have lateral dimensions strictly smaller than those of the trenches 141, the lateral walls of each trench 145 being constituted by parts of the insulating passivation layer 143. In the illustrated example, each trench 145 extends vertically, from the upper face of the insulating layer 115, through the conductive layer 111, through the semiconductor layers 109, 107 and 105, and is interrupted in the thickness of the layer 127 of the bonding stack 125. The trenches 145 make it possible, among other things, to isolate the part of the semiconductor layer 105 of each elementary LED relative to the parts of the layer 105 of the other LEDs.

[0087] In the example shown, the vias 147 have a depth less than that of the trenches 145. The vias 147 extend vertically, from the upper face of the layer 115, through the entire thickness of the layer 115. In the example illustrated, the bottom of each via 147 is constituted by a part of the upper face of the conductive layer 111.

[0088] [Fig.U] illustrates a structure obtained at the end of a subsequent step of forming conductive regions 149 inside the trenches 145 and the vias 147. In the example shown, the regions 149 fill the trenches 145 and the vias 147.

[0089] As an example, the regions 149 are produced by successive deposits, on the side of the upper face of the assembly: - at least one mirror layer extending over and in contact with the side faces and the bottom of the trenches 145 and the vias 147; - at least one seed layer extending over and in contact with the mirror layer; and - at least one layer of filling.

[0090] For example, the mirror layer is an aluminum layer or a titanium layer coated with an aluminum layer. For example, the seed layer consists of a stack of several layers comprising, in order from the mirror layer, a titanium layer, a titanium nitride layer and a copper layer. For example, the filling layer is made of a metal, for example copper, or a metal alloy.

[0091] The regions 149 are for example produced by a damascene-type process. The mirror layer is for example formed by ion beam deposition (IBD) or by physical vapor deposition. The filling layer is for example formed by electrochemical deposition.

[0092] The filling layer is for example deposited over the entire upper face of the assembly, to a sufficient thickness to fill the trenches 145 and the vias 147. A step of planarization of the upper face of the assembly, for example by chemical-mechanical polishing, is for example then implemented so that the regions 149 are flush with the upper faces of the parts of the layer 115.

[0093] [Fig. 1K] illustrates a structure obtained at the end of subsequent steps of forming a stack 151 of insulating layers 153 and 155 on the upper face of the structure of [Fig. U], of producing through-conducting vias 157 in the stack 151, of forming a stack 159 of insulating layers 161 and 163 on the stack 151, and of forming contact recovery elements 165 in the stack 159.

[0094] By way of example, the insulating layers 153 and 155 are respectively made of silicon nitride and silicon oxide. The conductive vias 157 are for example made of a metal, for example copper, or a metal alloy. The conductive vias 157 are for example made by implementing a damascene-type process. The conductive vias 157 make it possible, for example, to adjust the proportion of conductive material on the upper face of the assembly. In the example shown, each conductive via 157 extends vertically across the entire stack 151, and is located on and in contact with the upper face of one of the regions 149.

[0095] By way of example, the insulating layers 161 and 163 are respectively made of silicon nitride and silicon oxide. The contact recovery elements 165 are for example produced by implementing a damascene-type process, for example of the type described in French patent No. FR3079350 (DD18591 / B16845), previously obtained by the applicant. The contact recovery elements 165 are for example made of a metal, for example copper, or a metal alloy. In the example shown, each contact recovery element 165 extends vertically across the entire stack 159, and is located on and in contact with the upper face of one of the conductive vias 157.

[0096] [Fig. IL] illustrates a structure obtained at the end of steps of forming, on one face of a substrate 167 comprising an active region 169, a stack 171 of insulating layers 173 and 175, of producing through-conductor vias 177 in the stack 171, of forming a stack 179 of insulating layers 181 and 183 on the stack 171, and of forming contact recovery elements 185 in the stack 179.

[0097] The substrate 167 is for example a wafer or a piece of wafer made of a semiconductor material, for example silicon. The active region 169 of the substrate 167 comprises for example a plurality of integrated control circuits. The control circuits, not detailed in [Fig. IL] for the sake of readability, are for example produced in CMOS (Complementary Metal-Oxide-Semiconductor) technology. The control circuits formed in the active region 169 are for example of the ASIC (Application-Specific Integrated Circuit) type. For example, the substrate 167 has lateral dimensions strictly greater than those of the growth substrate 103.

[0098] The stacks 171 and 179 are, for example, analogous or identical to the stacks 151 and 159, respectively. Furthermore, the conductive vias 177 and the contact recovery elements 185 are, for example, analogous or identical to the conductive vias 157 and the contact recovery elements 165, respectively.

[0099] [Fig.lM] illustrates a structure obtained following subsequent steps of transferring and fixing the assembly of [Fig.lK] to the assembly of [Fig.l11]. In this step, the assembly comprising the temporary transfer substrate 133, the layer 135, the stack 125, the stack 101, the layer 111, the layer 115, and the stacks 151 and 159 can be turned over with respect to the orientation of [Fig. 1K] so as to fix the face of the LED stack 101 opposite the substrate 133 to the upper face of the substrate 167. The lower face of the insulating layer 163 and the lower faces of the contact recovery elements 165, in the orientation of [Fig. 1M], can be fixed respectively to the upper face of the insulating layer 183 and to the upper faces of the contact recovery elements 185.In this example, the fixing of the active LED stack 101 on the substrate 167 is obtained by direct bonding of the surfaces brought into contact, for example more precisely by hybrid metal / oxide bonding. By way of example, an annealing operation, for example at a temperature equal to approximately 400°C and for a duration of the order of 2 h, is then implemented so as to consolidate the bonding.

[0100] At the end of the transfer step, the individual LEDs previously delimited in the active stack of LEDs 101 are connected to the electronic control circuits formed in the active region 169 of the substrate 167.

[0101] Once the active LED stack 101 is fixed on the upper face of the substrate 167, the temporary transfer substrate 133 is removed, for example by grinding then etching. wet with selective stopping on the material of layer 135.

[0102] A chemical-mechanical polishing step is for example then implemented on the side of the upper face of the assembly so as to remove the layers 135 and 129. By way of example, the chemical-mechanical polishing is carried out with a stop on the layer 127.

[0103] A passivation layer (not shown), for example made of silicon nitride, is for example then deposited on the side of the upper face of the assembly, and microlenses 187 are produced directly above each elementary LED of the optoelectronic display device. By way of example, the microlenses 187 are made of an insulating material, for example silicon nitride or gallium nitride.

[0104] An advantage of the method described in relation to Figures 1A to 1M is that it does not include a step of cutting the growth substrate 103 into individual tiles or chips. This is particularly advantageous in the case where the growth substrate 103 is made of sapphire, which is a material that is very difficult to cut.

[0105] Another advantage of the method described in relation to figures 1A to 1M lies in the fact that the step of removing the growth substrate 103 is carried out before the transfer of the active stack of LEDs 101 onto the semiconductor substrate 167 in and onto which the control circuits are integrated. This makes it possible, in the case where this removal is implemented by projecting a laser beam through the substrate 103, for example during a laser detachment step, to avoid the risk of damaging the control circuits.

[0106] Yet another advantage of the method described in relation to figures 1A to 1M is that it makes it possible to obtain an optimal optical configuration in terms of light extraction, in particular due to the presence of resonant cavity LEDs, slopes in the gallium nitride favorable to the extraction of light towards the external environment, and the possibility of producing the microlenses in gallium nitride.

[0107] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] are schematic and partial side and sectional views illustrating structures obtained at the end of steps of an alternative implementation of the method of Figures 1A to 1M. The alternative of Figures 2A to 2D corresponds, for example, generally to a case in which the first bonding is a metal / metal type bonding.

[0108] [Fig.2A] illustrates a structure obtained at the end of a step of forming a bonding stack 201 on the upper face of the metal layer 111 of the structure of [Fig.1A].

[0109] In the example shown, the bonding stack 201 comprises, in order from the upper face of the metal layer 111, a layer 203 of metal nitride, for example titanium nitride (TiN), and a bonding layer 205 of metal, for example titanium. In the example shown, the lower face of the layer 203 is in contact with the upper face of the metal layer 111, and the upper face of the layer 203 is in contact with the lower face of the layer 205.

[0110] For example, layer 203 has a thickness of the order of 40 nm. For example, layer 205 has a thickness of the order of 600 nm.

[0111] Although this has not been illustrated in [Fig.2A] in order not to overload the drawing, another layer can be interposed between layers 203 and 205 in order to constitute a stop layer during a subsequent step of removing layer 205.

[0112] In subsequent steps, for example analogous to the steps previously described above in relation to figures IC to 1E: - the structure of [Fig.2A] is for example turned over then transferred onto the temporary transfer substrate 121, the bonding layer 123 coating the substrate 121 being in this case made of metal, for example titanium; - the growth substrate 103 is removed and the bonding stack 125 is formed on the active LED stack 101; and - the assembly is cut out so as to obtain the elementary vignettes 131.

[0113] [Fig.2B] illustrates a structure obtained at the end of subsequent steps of transferring and fixing the stickers 131 on the upper face of the temporary transfer substrate 133, of removing a part of the thickness of the temporary transfer substrate 121 and of depositing the encapsulation layer 137.

[0114] The transfer of the vignettes 131 onto the upper face of the temporary transfer substrate 133 is for example carried out in a manner similar or identical to that described above in relation to [Fig. 1F]. By way of example, the partial removal of the temporary transfer substrate 121 is carried out by grinding. The encapsulation layer 137 is for example deposited over the entire upper face of the structure, for example as explained previously in relation to [Fig. 1G].

[0115] [Fig.2C] illustrates a structure obtained following subsequent steps of removing the entire temporary transfer substrate 133 and removing the bonding layers 123 and 207.

[0116] The temporary transfer substrate 133 is for example removed by grinding. For example, the bonding layers 123 and 207 are removed by etching, for example by wet etching, with a stop on the metal nitride layer 203.

[0117] [Fig.2D] illustrates a structure obtained following subsequent steps of depositing the passivation layer 139.

[0118] The production of the passivation layer 139 is for example analogous or identical to what was previously described in relation to [Fig.1G], and will not be detailed again below.

[0119] Subsequent steps similar or identical to those previously described in relation to FIGS. 1H to 1M are for example then implemented from the assembly of [Fig.2D].

[0120] The variant of Figures 2A to 2D has, for example, advantages similar or identical to those of the method of Figures 1A to 1M.

[0121] [Fig.3A], [Fig.3B], [Fig.3C] and [Fig.3D] are respectively a top view and side and sectional views, schematic and partial, illustrating structures obtained at the end of steps of another variant of implementation of the method of FIGS. 1A to 1M. The variant of FIGS. 3A to 3D corresponds for example in a general manner to a case in which the transfer of the vignettes 131 onto the temporary transfer substrate 133 is carried out by means of a film of water.

[0122] [Fig.3A] illustrates a structure obtained at the end of a step of transferring and fixing the stickers 131 onto the bonding layer 135 coating the temporary transfer substrate 133. By way of example, the stickers 131 are obtained according to the steps of the method described above in relation to FIGS. 1A to 1E.

[0123] The transfer of the vignettes 131 is for example carried out by the implementation of a water film bonding technique, for example as explained in European patent application No. EP 3593376 previously filed by the applicant.

[0124] In the illustrated example, the vignettes 131 have, in top view, a substantially square general shape. This example is however not limiting, the vignettes 131 being able, as a variant, to have any general shape, for example rectangular, oval, circular, etc.

[0125] At the end of the transfer and fixing step, the vignettes 131 are for example misaligned laterally and / or angularly with respect to the desired positions of the vignettes 131. In order to overcome this problem, the vignettes 131 are for example etched so as to obtain vignettes 301 aligned with respect to the desired positions. To be able to implement this misalignment correction, it is for example provided that the vignettes 131 have lateral dimensions strictly greater than those of the desired vignettes 301 after transfer onto the temporary transfer substrate 133.

[0126] [Fig.3B] illustrates a structure obtained at the end of subsequent steps of depositing the encapsulation layer 137 and depositing the insulating passivation layer 139, for example as explained previously in relation to [Fig.1G].

[0127] [Fig.3C] illustrates a structure obtained at the end of a subsequent step of structuring the insulating passivation layer 139, for example by photolithography then etching directly above each vignette 131.

[0128] In the example shown, the layer 139 is removed directly above each vignette 131 so as to expose the upper face (in the orientation of [Fig.3C]) of the layer 137 located on each vignette 131.

[0129] [Fig.3D] illustrates a structure obtained following a subsequent plana- rization of the structure of [Fig.3C] on the side of the upper face (in the orientation of [Fig.3D]) of the temporary transfer substrate 133.

[0130] In the example shown, at the end of this step, the upper face of the insulating passivation layer 139 is flush with the upper faces of the vignettes 131, more precisely the upper faces of the parts of the layer 137 covering each vignette. By way of example, the planarization step is carried out by chemical-mechanical polishing, for example with a stop on the layer 137.

[0131] The variant of figures 3A to 3D has, for example, similar advantages or identical to those of the process of figures IA to IM.

[0132] Another advantage of the variant described above in relation to FIGS. 3A to 3D is that it makes it possible to greatly improve the flatness of the assembly, which constitutes a key element for the subsequent production of the hybrid bonding on the substrate 167.

[0133] Subsequent steps similar or identical to those previously described in relation to FIGS. 1H to 1M are for example then implemented from the assembly of [Fig. 1G].

[0134] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the variation of Figures 2A-2D and the variation of Figures 3A-3D may be combined.

[0135] Furthermore, the conductivity types of the semiconductor layers 105 (N-type, in the described examples) and 109 (P-type, in the described examples) may be reversed.

[0136] Furthermore, although exemplary embodiments of display devices comprising gallium nitride-based LEDs have been detailed, the described embodiments may be adapted by those skilled in the art to the manufacture of a device comprising a plurality of individually addressable gallium nitride-based photodiodes for acquiring images.

[0137] More generally, the embodiments described can be adapted to the manufacture of any display device or photosensitive sensor based on semiconductor diodes, including those based on semiconductor materials other than gallium nitride, for example diodes based on other III-V semiconductor materials.

[0138] The described embodiments may further be adapted to the manufacture of any electronic device comprising a plurality of semiconductor components based on gallium nitride or based on other semiconductor materials, for example III-V materials, and an integrated circuit adapted to individually control these components. For example, the semiconductor components may be power components, e.g. transistors, diodes, etc.

[0139] Finally, the practical implementation of the described embodiments and variants is within the reach of those skilled in the art from the functional indications given above. In particular, the described embodiments are not limited to the particular examples of materials and dimensions mentioned in the present description.

Claims

Claims

1. Method for manufacturing optoelectronic devices, comprising the following successive steps: a) forming, by epitaxial growth on a growth substrate (103), an active diode stack (101); b) transferring, on a first transfer substrate (121), the active diode stack; c) removing the growth substrate; d) forming, by cutting the first transfer substrate and the active diode stack, a plurality of elementary vignettes (131); and e) transferring, on a second transfer substrate (133), the elementary vignettes each comprising a part of the active diode stack.

2. Method according to claim 1, wherein, in step b), the growth substrate (103) or the transfer substrate (121), is heated, preferably to a temperature greater than or equal to 40°C, more preferably greater than or equal to 70°C.

3. The method of claim 1, wherein in step b), the growth substrate (103) and the transfer substrate (121) are heated, preferably to a temperature greater than or equal to 40°C.

4. Method according to claim 1, 2 or 3, wherein, in step b), the active diode stack (101) is fixed on the first transfer substrate (121) by direct bonding of a first bonding layer (119), previously deposited on the face of the active diode stack opposite the growth substrate, with a second bonding layer (123), previously deposited on the first transfer substrate.

5. A method according to claim 4, wherein, in step b), the surfaces of the first (119) and second (123) bonding layers intended to be brought into contact are activated prior to fixing.

6. The method of claim 4 or 5, wherein the first (119) and second (123) bonding layers are made of amorphous silicon.

7. A method according to claim 4 or 5, wherein the first (119) and second (123) bonding layers are metal layers, preferably titanium.

8. Method according to any one of claims 1 to 7, in which, in step e), the elementary vignettes (131) are fixed on the second transfer substrate (133) by direct bonding of a third layer of bonding (129), previously deposited on the face of the active diode stack (101) opposite the first transfer substrate (121), with a fourth bonding layer (135), previously deposited on the second transfer substrate.

9. The method of claim 8, wherein the third (129) and fourth (135) bonding layers are silicon oxide.

10. Method according to any one of claims 1 to 9, further comprising, after step e), the following step: f) transferring the assembly comprising the second transfer substrate (133) and the parts of the active diode stack (101) onto an active substrate (167) comprising integrated control circuits.

11. Method according to claim 10, wherein, in step f), the parts of the active diode stack (101) and the second transfer substrate (133) are fixed to the active substrate (167) by bonding a first insulating layer (163), previously deposited on the face of the active diode stack opposite the second transfer substrate, and first contact recovery elements (165), located in the first insulating layer, with respectively a second insulating layer (183), previously deposited on the active substrate, and second contact recovery elements (185), located in the second insulating layer.

12. Method according to any one of claims 1 to 11, further comprising, after step e), a step g) of etching the elementary vignettes (131) so as to compensate for a misalignment of the elementary vignettes relative to the second transfer substrate (133).

13. Method according to claim 12, further comprising, after step g), a step h) of depositing an insulating layer (139) filling spaces extending laterally between the elementary vignettes (131) then removing parts of the insulating layer located directly above the elementary vignettes (131).

14. A method according to any one of claims 1 to 13, wherein the growth substrate (103) is sapphire.

15. A method according to any one of claims 1 to 14, wherein the active diode stack (101) comprises gallium nitride.

16. A method according to any one of claims 1 to 15, wherein the active diode stack (101) is a light-emitting diode stack comprising, in order from the growth substrate (103), first (105) and second (109) semiconductor layers of opposite conductivity types.

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