Electronic chip

Abstract

Electronic chip The present description relates to an electronic chip (200) delimited by an edge and comprising: - a semiconductor layer (101) extending along a main plane (XY); - an interconnection structure (202) positioned above the semiconductor layer; - a sealing ring (207) arranged in the interconnection structure between the edge of the electronic chip and an electronic circuit region (105) of the electronic chip, the sealing ring including: - a plurality of cavities (231, 231') connected together so as to form at least one continuous annular cavity around the electronic circuit region; and / or - a plurality of conductive regions connected together so as to form at least one annular conductive wall around the electronic circuit region. Figure for abstract: Fig. 2B

Description

Title of the invention: Electronic chip Technical field

[0001] The present description relates generally to electronic chips, or integrated circuits, and in particular to electronic chips comprising sealing rings, known as "seal-rings" in English. Prior art

[0002] In industry, most electronic devices are mass-produced. Generally, several copies of an electronic device are manufactured simultaneously in and on the same semiconductor substrate, for example the same plate or semiconductor wafer. In particular, several electronic chips are generally manufactured in and on the same semiconductor substrate, for example the same plate or semiconductor wafer. The electronic chips can then be separated, or individualized, so that they can be used, for example alone or in a more complete electronic device. This individualization is generally carried out by cutting.

[0003] During this individualization, for example during cutting of the semiconductor wafer, a crack may occur on an edge of an electronic chip. Such a crack may lead to a failure of the electronic circuits of the electronic chip.

[0004] Furthermore, even if cracks do not appear during manufacturing, some cracks may appear during the lifetime of the chip, particularly on an edge of the chip, for example due to temperature changes of the electronic chip.

[0005] To protect an electronic chip, particularly during manufacturing, individualization, or even during its lifetime, the electronic chip may include a sealing ring at its periphery. One purpose of the sealing ring is to prevent cracks from propagating from the edge to an electronic circuit region, or circuit region, of the electronic chip. However, the sealing ring does not always prevent cracks from forming and propagating in the electronic chip.

[0006] It would be desirable to be able to improve, at least in part, electronic chips, and in particular the protection of electronic chips. Summary of the invention

[0007] There is a need for an electronic chip that is better protected, particularly better protected from cracks.

[0008] It would be advantageous if the method of manufacturing such an electronic chip could be carried out using standard electronic chip manufacturing processes.

[0009] One embodiment overcomes all or part of the drawbacks of known electronic chips.

[0010] One embodiment provides an electronic chip delimited by an edge, the electronic chip comprising: - a semiconductor layer extending along a principal plane; - an interconnection structure positioned above the semiconductor layer; - a sealing ring disposed in the interconnect structure between the edge of the electronic chip and an electronic circuit region of the electronic chip, the sealing ring including: a plurality of cavities connected together so as to form at least one continuous annular cavity around the electronic circuit region; and / or a plurality of conductive regions connected together so as to form at least one annular conductive wall around the electronic circuit region.

[0011] The electronic circuit region comprises electronic circuits formed in and on the semiconductor layer.

[0012] According to one embodiment, the interconnection structure comprises: - a plurality of metallization levels each comprising a conductive layer, the conductive layers of two successive metallization levels being connected to each other by conductive vias and / or conductive strips of the interconnection structure; and - insulating layers in which the conductive layers, conductive vias and / or conductive strips are embedded; the interconnection structure being for example connected to the semiconductor layer by means of another conductive via and / or an electrical contact.

[0013] According to one embodiment, each metallization level of the interconnection structure comprises conductive elements of a conductive layer insulated from each other by insulating elements of an insulating layer.

[0014] According to one embodiment, the cavities and / or the conductive regions extend at least up to a first metallization level of the interconnection structure.

[0015] According to one embodiment, the cavities and / or the conductive regions extend at least up to an interface level between conductive vias and conductive layers of two successive metallization levels of the interconnection structure, for example up to an interface level between conductive vias and first and second level conductive layers of metallization of the interconnect structure.

[0016] According to one embodiment, the cavities and / or the conductive regions extend to the semiconductor layer.

[0017] According to one embodiment, the cavities and / or the conductive regions stop at a non-zero distance from the semiconductor layer.

[0018] According to one embodiment, the conductive regions are metallic regions, for example comprising tungsten, or are mainly made of tungsten.

[0019] According to one embodiment, the sealing ring includes a sealing element comprising an annular conductive plate in each metallization level of the interconnection structure, two annular conductive plates of two successive metallization levels being connected to each other in a direction perpendicular to the main plane by an annular conductive strip.

[0020] According to one embodiment, the at least one annular continuous cavity comprises a first annular continuous cavity between the electronic circuit region and the sealing element and / or a second annular continuous cavity between the sealing element and the edge of the electronic chip.

[0021] According to one embodiment, the at least one annular conductive wall comprises a first annular conductive wall between the electronic circuit region and the sealing element and / or a second annular conductive wall between the sealing element and the edge of the electronic chip.

[0022] According to one embodiment, the electronic chip further comprises, in the electronic circuit region, cavities connected to each other, and / or conductive regions connected to each other, between two adjacent conductive elements of the interconnection structure.

[0023] One embodiment provides a method of manufacturing an electronic chip, the method comprising: - providing a structure comprising a semiconductor layer and a first metallization level of a future interconnect structure above the semiconductor layer, the structure comprising an electronic circuit region which comprises electronic circuits formed in and on the semiconductor layer, and a sealing ring region around the electronic circuit region, and the first metallization level comprising conductive elements of a conductive layer insulated from each other by insulating elements of a first insulating layer; - forming first holes in the sealing ring region through the first insulating layer between two adjacent conductive elements among the conductive elements; - widening the first orifices by etching, so as to form in the sealing ring region open cavities connected to each other around the electronic circuit region; - forming a second insulating layer above the open cavities and the first insulating layer, so as to close the open cavities, forming interconnected cavities around the electronic circuit region, the interconnected cavities forming at least one continuous annular cavity around the electronic circuit region.

[0024] According to one embodiment, the method comprises, before the formation of the first orifices, the deposition of a protective layer above the first insulating layer and the conductive elements, then the formation of openings by etching in the protective layer, the first orifices being formed at the right angle of the openings.

[0025] According to one embodiment, the method further comprises: - forming at least two second holes by etching into the second insulating layer up to at least two of the cavities in the sealing ring region; and - filling the second orifices with a conductive material, for example a metallic material, the filling of the second orifices being carried out so as to fill the cavities, forming conductive regions connected to each other, and thus an annular conductive wall around the electronic circuit region.

[0026] According to one embodiment, the filling of the second orifices also forms first conductive vias connected to the annular conductive wall.

[0027] According to one embodiment, the method further comprises: - forming third orifices by etching in the second insulating layer, each third orifice extending to one of the conductive elements; and - filling the third orifices with a conductive material, for example a metallic material, forming second conductive vias connected to the conductive elements.

[0028] According to one embodiment, the formation of the third orifices is carried out at the same time as the formation of the second orifices, and / or the filling of the third orifices is carried out at the same time as the filling of the second orifices.

[0029] According to one embodiment, the method further comprises forming, in the electronic circuit region, interconnected cavities, and / or interconnected conductive regions, between two adjacent conductive elements of the interconnection structure. Brief description of the drawings

[0030] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0031] [Fig.1A] is a schematic and partial top view illustrating an example of an electronic chip;

[0032] [Fig.lB] is a schematic and partial sectional view representing an exemplary embodiment of the electronic chip of [Fig.lA];

[0033] [Fig.lC] is another schematic and partial sectional view of the electronic chip of [Fig.lB];

[0034] [Fig.2A] is a schematic and partial top view illustrating an electronic chip according to one embodiment;

[0035] [Fig.2B] is a schematic and partial sectional view representing an exemplary embodiment of the electronic chip of [Fig.2A];

[0036] [Fig.2C] is another schematic and partial sectional view of the electronic chip of [Fig.2B];

[0037] [Fig.3A] is a schematic and partial top view illustrating an electronic chip according to another embodiment;

[0038] [Fig.3B] is a schematic and partial sectional view representing an exemplary embodiment of the electronic chip of [Fig.3A];

[0039] [Fig.3C] is another schematic and partial sectional view of the electronic chip of [Fig.3B];

[0040] [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F], [Fig.4G] and [Fig.4H] ​​are sectional views schematically and partially representing structures obtained at the end of steps of an example of a method for manufacturing an electronic chip according to an embodiment; and

[0041] [Fig.5A] and [Fig.5B] are sectional views schematically and partially representing structures obtained at the end of steps of a variant of the manufacturing method of FIGS. 4A to 4H. Description of the embodiments

[0042] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0043] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, not all the manufacturing steps and details of the electronic chips are described, being achievable with the usual methods of manufacturing electronic chips. In particular, the electronic circuits of the electronic chips are not shown, the embodiments being compatible with different electronic circuits in an electronic chip. Furthermore, all the manufacturing steps and details of the interconnection structures are not described, being achievable with the usual methods of manufacturing interconnection structures.

[0044] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0045] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0046] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0047] In the following description, the terms "insulator" and "conductor" mean respectively, unless otherwise specified, electrically insulating and electrically conductive.

[0048] In the following description, unless otherwise specified, when a chip is referred to, it is an electronic chip, when a via is referred to, it is a conductive via, and when a substrate is referred to, it is a semiconductor substrate.

[0049] In Figures 1A to 3C described below, an electronic chip is shown which is already individualized. However, in practice, the entire following description of the chip also applies when the chip is not yet individualized and is still part of a semiconductor wafer comprising, for example, a plurality of chips. In particular, in the case where the chip is still part of a semiconductor wafer, the edge of the chip corresponds to the location of the edge of the chip after the individualization step. By edge, we mean all of the edges, or peripheral ends, of the chip.

[0050] [Fig.lA] is a schematic and partial top view illustrating an example of an electronic chip 100. [Fig.lB] is a schematic and partial sectional view representing an example of an embodiment of the electronic chip 100 of [Fig.lA]. [Fig.lC] is another schematic and partial sectional view of the electronic chip of [Fig.lB]. The sectional view of [Fig.lB] is produced along the section plane A- A marked in [Fig.lA]. The sectional view in [Fig.lC] is made according to the sectional plane BB marked in [Fig.lB].

[0051] The chip 100 comprises a semiconductor layer 101, for example corresponding to a semiconductor substrate, for example made of silicon, or to the semiconductor layer of a substrate of the silicon on insulator type, or "SOI", from the English "Silicon On Insulator". The electronic circuits of the chip 100 are arranged in and / or on the semiconductor layer 101. The electronic circuits of the chip 100 are not shown in FIGS. 1 A, 1 B and 1 C, but are all arranged in an electronic circuit region 105, or circuit region, of the chip 100 delimited by the circumference 105L. In other words, the circuit region 105 comprises all the electronic circuits of the chip 100. The circuit region 105 of the chip 100 is, for example, a central region of the chip 100, as shown in the view of [Fig.lA],

[0052] The chip 100 further comprises an interconnection structure 102 above the semiconductor layer 101, for example in contact with the semiconductor layer 101. This interconnection structure 102 is also designated by the expression "end of line interconnection structure", for short "BEOL" interconnection structure, from the English "back end of line". The interconnection structure 102 comprises a plurality of metallization levels. Six metallization levels M1, M2, M3, M4, M5, M6 are shown in the example of [Fig.lB], although this is not limiting, the number of metallization levels being able to vary.

[0053] Each metallization level comprises at least one portion 103C of a conductive layer 103, for example a metal layer, each portion 103C forming a conductive element in the form of a conductive track, or conductive line. The conductive tracks 103C of the different levels of the interconnection structure 102 are electrically connected to each other, and / or to connection pads 104, and / or to the electronic circuits of the chip 100 by conductive vias 106, for example metal vias. The conductive tracks 103C of the different levels of the interconnection structure 102 are preferably positioned in the circuit region 105. Thus, the interconnection structure 102 makes it possible to connect the electronic circuits of the chip 100 to each other and / or to the connection pads 104. It is considered that the connection pads 104, which can be referred to as "pads" for short, are part of the interconnection structure 102.The pads 104 are arranged at the upper metallization level of the interconnection structure 102 in the example of [Fig. 1B], which corresponds to the metallization level M6. In other words, the pads 104 are arranged at an upper face 102A (first face) of the interconnection structure 102, a lower face 102B (second face) of the . interconnection structure, opposite the upper face 102A, being in contact with the semiconductor layer 101.

[0054] The pads 104 are distributed in a substantially annular manner, here a square-shaped ring, in the circuit region 105 of the chip 100 and, more precisely, in a region of the interconnection structure 102 included in the circuit region 105 of the chip 100.

[0055] The pads 104 are configured to be in contact with conductive elements located outside the chip 100, so that the chip 100 can, for example, exchange electrical signals with the outside. For example, each pad 104 is in direct contact with a conductive track 103C of the upper metallization level M6, that is to say the metallization level which is the furthest from the semiconductor layer 101. The interconnection structure 102 further comprises insulating layers, which are all designated by the same and unique reference 111 in FIGS. 1B and 1C, which each separate two successive metallization levels and which can also be between portions of each conductive layer 103 at the same metallization level, the conductive layers 103 and the vias 106 being embedded in the insulating layers 111. All of the insulating layers can be designated as being an insulating layer.The insulating layer may be made of an oxide, for example silicon oxide, or of a high-K dielectric material, i.e. a material having a high dielectric constant K compared to that of silicon dioxide.

[0056] The chip 100 comprises a sealing region 107, or sealing ring, at the periphery of the chip 100, that is to say between the circuit region 105 and the edge 110 of the chip 100. Thus, the sealing ring 107 surrounds the circuit region 105 of the chip 100. The sealing ring 107 has an annular shape when viewed from above. The sealing ring 107 is arranged in the interconnection structure 102, at the periphery of the chip 100. The sealing ring 107 is thus part of the interconnection structure 102 although it is not used to connect the electronic circuits of the chip 100 together and / or with the pads 104. Preferably, the chip 100 does not include any electronic circuits in the sealing ring 107. In other words, the circuit region 105 of the chip 100 is delimited laterally, in the interconnection structure 102, by the sealing ring 107.

[0057] An intended function of the sealing ring 107 is to prevent crack propagation from the edge 110 of the chip 100 to the circuit region 105 of the chip 100.

[0058] Another intended function of the sealing ring 107 may be to block the propagation of moisture from the outside of the chip 100, therefore from the edge 110 of chip 100, to the electronic circuits of circuit region 105 of chip 100.

[0059] To perform one or more of these functions, the sealing ring 107 may include one or more sealing elements 108, each sealing element having an annular shape in plan view. One sealing element is shown in Figures 1A, 1B and 1C, although there may be more than one, as discussed later. Where there are more than one sealing element, they may be substantially concentric. One sealing element may be adapted to stop crack propagation, another sealing element may be adapted to block moisture ingress, and / or one sealing element may be adapted to perform both of these functions of stopping crack propagation and blocking moisture ingress.Each sealing element extends in height from the semiconductor layer 101 through all or part of the metallization levels M1-M6 of the interconnection structure 102, for example through one or more lower metallization levels of the interconnection structure 102. For protection against humidity, it is however preferable that the sealing element 108 extends up to the upper metallization level M6.

[0060] The shown sealing element 108 forms a closed loop around the circuit region 105 of the chip 100, or, in other words, the sealing element 108 completely surrounds the circuit region 105 of the chip 100.

[0061] In the exemplary embodiment shown in [Fig.lB], the sealing element 108 forms an annular wall comprising other portions 103A of the conductive layers 103 of the interconnection structure 102. More precisely, the sealing element 108 comprises a portion 103A of the conductive layer 103 of each metallization level M1-M6 of the interconnection structure 102. Each portion 103A of the conductive layer 103 forms an annular conductive plate at each metallization level. For example, each annular conductive plate 103A extends in a plane substantially parallel to the semiconductor layer 101. The successive annular conductive plates 103A of the sealing element 108 are connected to each other by one or more annular conductive strips 112 which extend continuously between two successive annular conductive plates 103A.In other words, the annular conductive strips 112 join two successive annular conductive plates 103A in the Z direction perpendicular to the XY plane of the semiconductor layer 101.

[0062] As shown in [Fig.lB], the successive annular conductive plates 103A of the sealing element 108 can furthermore be connected to each other by conductive vias 106 of the interconnection structure 102, making it possible for example to increase the mechanical resistance of the sealing element 108 with respect to a crack propagation. The vias 106 may be cylindrical in shape as shown in [Fig.lC]. Alternatively, the vias may be elongated in the form of bars, or even form the annular conductive strips 112. The vias 106 and the annular conductive strips 112 may be formed during the same manufacturing step.

[0063] The sealing element 108 may form a protective wall against the propagation of moisture towards the circuit region 105 of the chip 100.

[0064] As shown in [Fig.lB], the sealing ring 108 may comprise a dummy pad 104A, which is for example formed at the same time as the pads 104. The dummy pad 104A rests on the annular conductive plate 103A at the upper metallization level M6 of the interconnection structure 102. The dummy pad 104A may be arranged in a substantially annular manner, here it forms a square-shaped ring. It may be a question of several dummy pads. The annular arrangement and the presence of one or more dummy pads is not obligatory.

[0065] In order to detect cracks in the chip 100, the sealing ring 107 may include a crack sensor 116, or crack detector. The crack sensor 116 is disposed in the interconnect structure 102. In other words, the interconnect structure 102 includes the crack sensor 116. As shown in FIGS. 1A, 1B and 1C, the crack sensor 116 may be disposed in a region between the edge 110 of the chip 100 and the sealing element 108, this region of the interconnect structure 102 being devoid of any other sealing element. Thus, if a crack appears at the edge 110 of the die 100 and propagates toward the circuit region 105, the crack may be detected by the crack sensor 116 before the sealing element 108. Other configurations may be considered, as described further below.

[0066] The crack sensor 116 corresponds to a conductive structure that forms a conductive path, preferably an open loop. By testing the electrical conductivity between a first terminal, or node, 118 of the sensor 116, for example a first end of the sensor 116, and a second terminal, or node, 119 of the sensor 116, for example a second end of the sensor 116, cracks can be detected by the sensor 116.

[0067] In the exemplary embodiment shown in Figures 1B and 1C, the crack sensor 116 comprises several metal stacks each comprising other portions 103B of the conductive layers 103 connected by conductive vias 106 of the interconnection structure 102. More precisely, each metal stack extends in height in the Z direction perpendicular to the XY plane of the semiconductor layer 101 through all or part of the metallization levels M1-M6 of the interconnection structure 102, in the example shown up to the upper metallization level M6. Two metal stacks SI and S2 of crack sensor 116, although there may be more than two.

[0068] Preferably, although not illustrated in Figures 1B and 1C, in each metallization level, the portions 103B of the crack sensor 116 are discontinuous to form an electrical path extending upwardly and downwardly in the crack sensor 116 by means of the vias 106 of the crack sensor 116 which form a chain of vias. Preferably, the crack sensor 116 includes a plurality of portions 103B in each metallization level of the interconnect structure 102.

[0069] Although not shown in Figures 1A, 1B and 1C, the sealing ring 107 may include several sealing elements similar to the sealing element 108 described above, for example an inner sealing element disposed in the interconnection structure 102 around the circuit region 105 and an outer sealing element disposed in the interconnection structure 102 around the inner sealing element. The sealing ring 107 may then include an intermediate crack sensor, for example similar to the crack sensor 108 described above, disposed in the interconnection structure 102 between the inner sealing element and the outer sealing element.The presence of internal and external sealing elements and an intermediate crack sensor between these internal and external sealing elements makes it possible to detect that cracks have propagated from the edge of the electronic chip through the external sealing element.

[0070] Although not shown in Figures 1A, 1B, and 1C, the sealing ring 107 may include an internal crack sensor disposed in the interconnect structure 102 around, or at the edges of, the circuit region 105 and surrounded by the sealing element 108, or the internal sealing element. The internal crack sensor is capable of detecting that cracks have propagated from the edge 110 of the die 100 through the sealing element(s) and may reach the circuit region 105.

[0071] More generally, any sealing ring structure may be considered in the interconnect structure, aimed at limiting the propagation of cracks towards the circuit region of the electronic chip, or even at blocking moisture. For example, the sealing ring may comprise one or more sealing elements that do not necessarily extend to the upper metallization level, or even several sealing elements that extend to different metallization levels. For protection against moisture, a sealing element preferably extends to the upper metallization level. In addition, the sealing ring may comprise one or more crack sensors that do not extend necessarily up to the upper metallization level, or even several crack sensors that extend to different metallization levels.

[0072] In some cases, it has been found by crack sensors, in particular by an internal crack sensor, that cracks could propagate in the sealing ring, or even pass through the sealing ring. Thus, the sealing ring is not always sufficient to stop cracks, which can propagate in the circuit region of the electronic chip.

[0073] The inventors propose an electronic chip making it possible to meet the improvement needs described above, and to overcome all or part of the drawbacks of the electronic chips described above. In particular, the inventors propose an electronic chip with reinforced protection, in particular against cracks, in particular an electronic chip comprising a sealing ring with reinforced protection.

[0074] It would be advantageous if the method of manufacturing such an electronic chip could be carried out using standard electronic chip manufacturing processes.

[0075] Embodiments of electronic chips will be described below. The embodiments described are non-limiting and various variants will appear to those skilled in the art from the indications of the present description.

[0076] [Fig.2A] is a schematic and partial top view illustrating an electronic chip 200 according to one embodiment. [Fig.2B] is a schematic and partial sectional view representing an exemplary embodiment of the electronic chip of [Fig.2A]. [Fig.2C] is another schematic and partial sectional view of the electronic chip of [Fig.2B]. The sectional view of [Fig.2B] is produced along the section plane AA identified in [Fig.2A]. The sectional view of [Fig.2C] is produced along the section plane BB identified in [Fig.2B].

[0077] The electronic chip 200 of FIGS. 2A, 2B and 2C has many elements in common with the electronic chip 100 of FIGS. 1A, 1B and 1C and only the differences between the two electronic chips 100 and 200 are detailed in the description which follows.

[0078] The electronic chip 200 of FIGS. 2A, 2B and 2C is distinguished from the electronic chip 100 of FIGS. 1A, 1B and 1C mainly in that the sealing ring 207 further comprises a plurality of cavities 231, 231' in the interconnection structure 202.

[0079] The cavities 231 are connected together, forming an annular continuous cavity 230 which is located around the circuit region 105, preferably all around the circuit region 105, for example between the circuit region 105 and the sealing element 108. For example, the annular continuous cavity 230 can be positioned in the insulating layer 111 between the portions 103A, 103C of the conductive tracks 103 of one or more metallization levels.

[0080] The insulating layer 111 may be made of an oxide, for example a silicon oxide, or of a dielectric material of the high-K type, that is to say a material having a high dielectric constant K compared to that of silicon dioxide.

[0081] The cavities 231' are connected to each other, forming a continuous annular cavity 230' which is located around the circuit region 105, preferably all around the circuit region 105, for example between the edge 110 of the chip 200 and the sealing element 108.

[0082] Cavities can be referred to by the English term "air-gap". A cavity is a volume filled with a gas. Thus, cavities are filled with gas, for example air.

[0083] Such an annular continuous cavity allows a crack absorption region to be formed, thereby preventing crack propagation in the sealing ring 207 to the circuit region 105.

[0084] Advantageously, the cavities extend at least up to the interface level between the vias 106 and the conductive layers 103 of two successive metallization levels, for example of the first metallization level M1 and of the second metallization level M2, so as to block the progression of cracks which would form or propagate at this interface.

[0085] Cavities 231 are shown by way of example which extend up to the first metallization level M1, thus forming a continuous annular cavity 230 in the sealing ring 207 at the first metallization level ML. When indicated up to a metallization level, it should be understood that this metallization level is included. Since cracks often occur at the first metallization level, such a configuration may be sufficient to prevent cracks from propagating up to the circuit region 105 of the electronic chip 200. In addition, this makes it possible not to burden the manufacturing process of the electronic chip, knowing that it is possible to rely on an air-gap formation process, which may already be provided in another region of the interconnection structure, for example in the circuit region 105, for example at the first metallization level ML.

[0086] But this example is not limiting, and cavities 231' can be formed which extend up to the second metallization level M2 as illustrated, or even up to a higher metallization level, or even up to the upper metallization level (M6 in the example shown), thus forming a continuous annular cavity 230' in the sealing ring 207 which extends beyond the first metallization level ML.

[0087] Furthermore, cavities 231, 231' are shown which reach the semiconductor layer 101, which is not always necessary. Alternatively, the cavities may be at a non-zero distance from the semiconductor layer 101, for example stopping in the insulating layer 111, which may form a more robust structure than with cavities 231, 231' which stop at the semiconductor layer 101.

[0088] The other characteristics described in relation to figures 1A, 1B and 1C can be applied to the electronic chip 200 of figures 2A, 2B and 2C.

[0089] In particular, in Figures 2A, 2B and 2C, a single sealing element 108 is shown, knowing that the sealing ring 207 may comprise several sealing elements in the interconnection structure 202. For example, the sealing ring 207 may comprise one or more sealing elements which do not extend to the upper metallization level, or even several sealing elements which extend to different metallization levels. For protection against humidity, a sealing element preferably extends to the upper metallization level. Furthermore, in Figures 2A, 2B and 2C, no crack sensor is shown, but the sealing ring 207 of the electronic chip 200 could include one or more crack sensors, similarly to what has been described in connection with Figures 1A, 1B and 1C.Further, the sealing ring 207 could include one or more crack sensors that do not necessarily extend to the upper metallization level, or even multiple crack sensors that extend to different metallization levels.

[0090] [Fig. 3A] is a schematic and partial top view illustrating an electronic chip 300 according to another embodiment. [Fig. 3B] is a schematic and partial sectional view representing an exemplary embodiment of the electronic chip of [Fig. 3A]. [Fig. 3C] is another schematic and partial sectional view of the electronic chip of [Fig. 3B]. The sectional view of [Fig. 3B] is produced along the section plane AA illustrated in [Fig. 3A]. The sectional view of [Fig. 3C] is produced along the section plane BB identified in [Fig. 3B].

[0091] The electronic chip 300 of FIGS. 3A, 3B and 3C has many elements in common with the electronic chip 200 of FIGS. 2A, 2B and 2C and only the differences between the two electronic chips 200 and 300 are detailed in the description which follows.

[0092] The electronic chip 300 of Figures 3A, 3B and 3C is distinguished from the electronic chip 200 of Figures 2A, 2B and 2C primarily in that the interconnected cavities are filled with a conductive material, preferably a metallic material, such as tungsten or copper, forming conductive regions 331, 331' in the sealing ring 307. Like the cavities 231, 231', the conductive regions 331, 331' are interconnected, forming an annular conductive wall 330, 330' in the sealing ring 307 around the circuit region 105. Each conductive region 331, 331' is preferably a single piece. The annular conductive wall is preferably a single piece. It can also be referred to as a continuous annular wall. When referring to a "single piece" element, it refers to an element that is held in one piece, without division, without break in shape and material.

[0093] Such an annular conductive wall makes it possible to oppose the propagation of cracks. Indeed, in a sealing element which comprises portions of conductive layers connected together by vias, the interface between a via and a conductive layer is potentially fragile and can be a source of cracking and / or crack propagation. On the other hand, each conductive region is made of a single conductive material and in one piece, and therefore does not comprise an interface, and thus no fragility, and the annular conductive wall formed by the conductive regions connected together thus forms a continuous wall all around the circuit region and which is capable of opposing the propagation of cracks.

[0094] Advantageously, the conductive regions 331, 331' extend at least up to the interface level between the vias 106 and the conductive layers 103 of two successive metallization levels, for example of the first metallization level M1 and of the second metallization level M2, so as to block the progression of cracks which would form or propagate at this interface.

[0095] By way of example, conductive regions 331 are shown which are formed at the first metallization level M1, thus forming an annular conductive wall 330 in the sealing ring 307 at the first metallization level ML. Since cracks often occur at the first metallization level, such a configuration may be sufficient to prevent cracks from propagating to the circuit region 105 of the electronic chip 300. In addition, this makes it possible not to burden the manufacturing process, knowing that it is possible to rely on a process for forming a metal-filled air gap, which may already be provided in another region of the interconnection structure, for example in the circuit region 105, for example at the first metallization level ML.

[0096] But this example is not limiting, and it is possible to form conductive regions 331' which extend up to the second metallization level M2 as illustrated, or even up to a higher metallization level, or even up to the upper metallization level (M6 in the example shown), thus forming an annular conductive wall 330' in the sealing ring 307 which extends beyond the first metallization level ML.

[0097] Furthermore, conductive regions 331, 331' have been shown which reach the semiconductor layer 101, which is not always necessary. Alternatively, the conductive regions may be at a non-zero distance from the semiconductor layer 101, for example stop in the insulating layer 111, which can form a more robust structure than with conductive regions 331, 331' which stop at the semiconductor layer 101.

[0098] The other characteristics described in relation to figures 1A, 1B and 1C can be applied to the electronic chip 300 of figures 3A, 3B and 3C.

[0099] In particular, in Figures 3A, 3B and 3C, a single sealing element 108 is shown, knowing that the sealing ring 307 may comprise several sealing elements in the interconnection structure 302. For example, the sealing ring 307 may comprise one or more sealing elements that do not extend to the upper metallization level, or even several sealing elements that extend to different metallization levels. For protection against humidity, a sealing element preferably extends to the upper metallization level. Furthermore, in Figures 3A, 3B and 3C, no crack sensor is shown, but the sealing ring 307 of the electronic chip 300 could include one or more crack sensors, similarly to what has been described in connection with Figures 1A, 1B and 1C.Further, the sealing ring 307 could include one or more crack sensors that do not necessarily extend to the upper metallization level, or even multiple crack sensors that extend to different metallization levels.

[0100] The embodiments of Figures 2A to 2C and 3A to 3C may be combined. For example, the sealing ring may comprise an annular continuous cavity and an annular conductive wall, the annular continuous cavity and the annular conductive wall being, for example, substantially concentric.

[0101] Further, in combination with one or more of the disclosed embodiments, and similarly to what is disclosed in the sealing ring, the interconnect structure may include, in the circuit region, interconnected cavities between adjacent conductive tracks of the interconnect structure, forming a continuous cavity between the adjacent conductive tracks, at least at the first metallization level of the interconnect structure. The interconnect structure may also include, in the circuit region, interconnected cavities between adjacent conductive tracks of the interconnect structure, these interconnected cavities being filled with a metallic material, such as tungsten or copper, forming a continuous conductive region between the adjacent conductive tracks, at least at the first metallization level of the interconnect structure.

[0102] [Fig.4A], [Fig.4B], [Fig.4C], [Fig.4D], [Fig.4E], [Fig.4F], [Fig.4G] and [Fig.4H] ​​are sectional views schematically and partially representing structures obtained at the end of steps of an example of a manufacturing process of an electronic chip according to one embodiment. The electronic chip obtained is for example similar to the electronic chip 200 of FIGS. 2A, 2B and 2C, [Fig.4H] ​​representing for example a portion of the electronic chip 200.

[0103] The structure of [Fig.4A] comprises a first metallization level 410 of a future interconnection structure of a future electronic chip. More particularly, [Fig.4A] illustrates a portion of interconnection structure comprising a sealing ring region 407, intended to comprise a sealing ring, around a circuit region 405. In the circuit region 405, electronic circuits are formed in and on a semiconductor layer 401. The first metallization level 410 is disposed above the semiconductor layer 401. In certain embodiments, the semiconductor layer 401 corresponds to a semiconductor substrate, for example made of silicon, or to the semiconductor layer of a substrate of the silicon on insulator, or "SOI", type.

[0104] The semiconductor layer 401 extends along a main plane XY.

[0105] An insulating layer 402, for example a pre-metal dielectric layer, or PMD layer, is formed on the semiconductor layer 401. In some embodiments, the PMD layer 402 comprises a silicon oxide, such as silicon dioxide (SiO2). In other embodiments, the PMD layer 402 comprises a silicon phosphide glass known by the English abbreviation "PSG" (Phospho-Silicon Glass), or a silicon borophosphide glass, known by the English abbreviation "BPSG" (Borophospho-Silicon Glass). However, the PMD layer 402 can comprise a combination of several of these materials, or any other suitable material.

[0106] Conductive vias 403 are formed through the PMD layer 402 to the semiconductor layer 401. The conductive vias 403 may form vias of the type of cylindrical vias 106 described in relation to FIGS. 1A to 1C, or form elongated vias in the form of bars or lines, or even form the annular conductive strips 112 described in relation to FIGS. 1A to 1C.

[0107] The first metallization level 410 comprises conductive elements 411, such as metal tracks or lines (elongated in the Y direction), insulated from each other by dielectric elements, or insulating elements 412. All of these insulating elements 412 form an insulating layer 413 (first insulating layer). The insulating layer 413 can be called an intermetallic dielectric layer, or IMD layer, from the English Inter-Metal Dielectric. The conductive elements 411 are connected to the vias 403, preferably being positioned substantially in line with the vias 403.

[0108] The first metallization level 410 may be formed by a subtractive process, for example for aluminum conductive elements, or by a Damascene-type process, for example for copper conductive elements.

[0109] An example of a subtractive process is described in the following. A conductive layer, for example made of aluminum, is deposited on the PMD layer 402 and the vias 403. Then, the conductive layer is etched through an etching mask, for example obtained by photolithography, the etching forming openings passing through the conductive layer to the PMD layer 402. The etching mask is sized so that the remaining parts of the conductive layer, forming the conductive elements 411, are positioned substantially in line with the vias 403. Then the etching mask is removed. A protective layer 414 can then be deposited so as to cover at least the side walls of the conductive elements 411, the protective layer possibly being made of a nitride, such as silicon nitride, or any other suitable material.Next, an IMD layer 413 is formed at least to fill the openings between the conductive elements 411, forming the insulating elements 412. The IMD layer 413 comprises, for example, a silicon oxide, such as silicon dioxide (SiO2), or any other dielectric material. Excess portions of the IMD layer 413 above the conductive layer may then be removed by means of planarization such as CMP.

[0110] An example of a Damascene process is described in the following. An IMD layer 413 is deposited on the PMD layer 402 and the vias 403. The IMD layer may be similar to the IMD layer described above. Then, the IMD layer 413 is etched through an etch mask, obtained for example by photolithography, forming openings passing through the IMD layer 413. The remaining portions of the IMD layer 413 form the insulating elements 412. The etch mask is sized so that the openings in the IMD layer 413 are positioned substantially in line with the vias 403. Then the etch mask is removed. A protective layer 414 may then be deposited in the openings of the IMD layer 413, so as to cover at least the side walls of the openings. The protective layer may be similar to the protective layer described above.A barrier layer may be formed in the openings, so as to cover the sidewalls and bottoms of the openings. The barrier layer comprises a suitable conductive material such as tantalum, tantalum nitride, titanium, titanium nitride, or a combination of several of these materials. Then, a layer of a conductive material, for example copper, is formed at least to fill the openings between the insulating elements 412, forming the conductive elements 411 with the barrier layer when provided. Excess portions of the conductive layer above the insulating elements 412 may be removed by means of planarization such as CMP.

[0111] In both techniques, the protective layer 414 is found on the sides of the conductive elements 411, which can protect the conductive elements 411 during of subsequent manufacturing steps, such as etching to form cavities as described later.

[0112] As seen in [Fig.4A], a protective layer 421 is formed on the first metallization level 410, i.e., on the conductive elements 411 and the IMD layer 413. The protective layer 421 may be similar to the protective layer 414 described above.

[0113] [Fig.4B] shows a structure obtained after forming an etching mask 422 on the protective layer 421. The etching mask 422 can be obtained by a photolithography technique, and it comprises an opening 422A which passes through it. Only one opening 422A is shown in [Fig.4B], but there are generally several openings at least in the Y direction.

[0114] [Fig.4C] shows a structure obtained after etching a portion of the protective layer 421 through the opening 422A of the etching mask 422, the etched portion forming an opening 421A in the protective layer 421. This etching is for example a dry etching, of the plasma etching type.

[0115] [Fig.4D] shows a structure obtained after etching an orifice 423 (first orifice) passing through the IMD layer 413 into the PMD layer 402, between the conductive elements 411, in the sealing ring region 407. The etching is carried out through the opening 422A of the etching mask 422 and the opening 421A of the protective layer 421. The orifice 423 may be formed by means of a suitable anisotropic etching, such as a dry etching, for example, of the plasma etching type. The diameter of the orifice 423 may correspond substantially to the diameter of the opening 421A in the protective layer 421.

[0116] The etching steps described in connection with Figures 4C and 4D can be performed in a single step.

[0117] The orifice 423 does not extend to the semiconductor layer 401, that is to say it stops in the PMD layer 402.

[0118] The etching mask 422 is then removed.

[0119] [Fig.4E] shows a structure obtained after widening the orifice 423 by etching, so as to form an open cavity 424 in the IMD layer 413 and the PMD layer 402 between two conductive elements 411, and possibly between two vias 403. The opening of the open cavity 424 corresponds to the opening 421A of the protective layer 421. The open cavity 424 can be formed by means of an appropriate isotropic etching, advantageously selective of the material of the IMD layer 413 and the PMD layer 402 with respect to the material of the protective layer 421, to avoid etching the protective layer 421. In certain embodiments, the isotropic etching is a wet etching, for example carried out with hydrofluoric acid (HF), for example HF in vapor form, of hydrochloric acid (HCl), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), sodium hydroxide (NaOH), nitric acid (HNO3), buffered oxide etch (BOE), or a mixture of several of these products.

[0120] The diameter of the orifice 423 can be used to define the dimensions of the open cavity 424. For example, the larger the diameter of the orifices 423, the larger the average diameter of the open cavities 424 can be. The diameter of the orifice 423 is however generally limited by the following step which consists of closing the opening 421A, and thus the open cavity 424, without sealing it.

[0121] The protective layer 414 which is located on the side walls, or flanks, of the conductive elements 411 can advantageously protect the conductive elements 411 during anisotropic etching and / or isotropic etching.

[0122] [Fig.4F] shows a structure obtained after forming an insulating layer 425 (second insulating layer), which may be called an intermetallic dielectric layer, or IMD layer, on the protective layer 421 and on the opening of the open cavity 424, so as to close this open cavity, forming a closed cavity which is designated cavity 431. The IMD layer 425 may be formed using materials and methods similar to those of the IMD layer 413 as described further. Passing through the opening 421A of the protective layer 421, the dielectric material of the IMD layer 425 may come to cover the internal surfaces of the cavity 431 before closing the open cavity 424, forming an internal coating 426 in the cavity 431.

[0123] The sections of Figures 4C, 4D, 4E, 4F respectively show a single opening 421A, a single orifice 423, a single open cavity 424 and a single cavity 431, but there are several openings 421A, several orifices 423, and thus several cavities 431 connected to each other in the Y direction. Thus, the cavities 431 between the conductive elements 411 are connected to each other, forming a continuous extended cavity. This may form an annular continuous cavity such as the annular continuous cavity 230 described in connection with FIGS. 2A, 2B and 2C, insofar as the cavities 431 are connected to each other along the entire periphery of the electronic chip around the circuit region 405. The widening of the orifices 423 is thus advantageously carried out so that the open cavities 424 can be connected to each other, then forming the cavities 431 connected to each other between the conductive elements 411.

[0124] The sections of Figures 4C, 4D, 4E, 4F respectively show a single opening 421A, a single orifice 423, a single open cavity 424, and a single cavity 431 between the two conductive elements 411 in the X direction. This section corresponds to an example, and one could have several openings 421A, several orifices 423, then several adjacent cavities 431 connected to each other, between the two conductive elements 411 in the X direction.

[0125] Figures 4G and 4H show an example of formation of vias 428 connecting the conductive elements 411 of the first metallization level 410 (M1) to other conductive elements of a second metallization level (not shown).

[0126] [Fig.4G] shows a structure obtained after forming an etching mask 426 on the IMD layer 425, then etching the IMD layer 425 and the protective layer 421 to form orifices 427 passing through these layers 425, 421 in line with the conductive elements 411.

[0127] The etching mask 426 may be obtained by a photolithography technique, and openings 426A in the etching mask 426 may be formed in line with the conductive elements 411 so that the orifices 427 are connected to the conductive elements 411, the etching being carried out through the openings 426A of the etching mask 426.

[0128] [Fig.4H] ​​shows a structure obtained after filling the orifices 427 with a conductive material, preferably a metallic material, which comprises for example tungsten with prior formation of a barrier layer of the Ti / TiN type, or copper with prior formation of a barrier layer of the TaN / Ta type, forming the conductive vias 428.

[0129] [Fig.4H] ​​may correspond to a partial section along the section plane CC marked in [Fig.2A] of the interconnection structure 202 of the electronic chip 200. Thus, the cavity 431 may correspond to one of the cavities 231 of [Fig.2B] which are in the sealing ring 207, and in the interconnection structure 202, between the circuit region 105 and the sealing element 108. The conductive elements 411 and the vias 403, 428 to the left of [Fig.4H] ​​may correspond to a part of the interconnection structure which is in the circuit region 405, the via 403 to the left then being able to be a contact connected to an electronic component on the semiconductor layer 401. The conductive elements 411 and the vias 403, 428 to the right of [Fig.4H] ​​may correspond to a portion of the interconnect structure that is in the sealing ring region 407, and may correspond to a portion of a sealing element formed in the interconnect structure.

[0130] Then, a second metallization level can be formed, by a technique similar to that used to form the first metallization level 410, for example by a subtractive process or by a Damascene-type process, as described in connection with [Fig.4A]. Then, other metallization levels can be formed in a similar manner.

[0131] If it is desired to obtain cavities which extend at least up to the second metallization level, or even up to a higher metallization level, the steps described in connection with FIGS. 4A to 4H can be reproduced at least once.

[0132] The method described in connection with FIGS. 4A to 4H may be adapted to also form, in the circuit region 405 of the chip, cavities connected to each other between adjacent conductive tracks of the interconnection structure, so as to form a continuous cavity between the adjacent conductive tracks, at least at the first metallization level of the interconnection structure.

[0133] [Fig.5A] and [Fig.5B] are sectional views schematically and partially representing structures obtained at the end of steps of a variant of the manufacturing method of FIGS. 4A to 4H. The electronic chip obtained is for example similar to the electronic chip 300 of FIGS. 3A, 3B and 3C, [Fig.5B] representing for example a portion of the electronic chip 300.

[0134] In particular, Figures 5A and 5B represent a variant of Figures 4G and 4H, in which the etching mask 526 comprises a first opening 526A in line with the cavity 431, and second openings 526B in line with the conductive elements 411. Thus, the etching of the IMD layer 425 and the protective layer 421 through the etching mask 526 forms an orifice 527A (second orifice) which passes through these layers to the cavity 431, and are thus connected to the cavity 431, and orifices 527B (third orifices) which pass through these layers to the conductive elements 411 and are thus connected to the conductive elements 411.

[0135] A single first opening 526A has been shown in line with the cavity 431, but, as indicated previously, there are several cavities 431 in the Y direction, and there are generally at least two first openings 526A in line with two different cavities 431.

[0136] The orifices 527A allow the cavities 431 to be reopened, to fill them with conductive material, and thus fill the continuous extended cavity, or annular continuous cavity, as described later. Preferably, each orifice 527A is centered with one of the openings 421A of the protective layer 421.

[0137] As shown in [Fig.5B], when filling with conductive material, preferably a metallic material, which for example comprises tungsten, the filling of the orifice 527A makes it possible to fill the cavity 431 with the conductive material, forming a conductive region 531, and the orifice 527A forms a first via 528A once filled. A single conductive region 531 has been shown, but, as indicated previously, there are several cavities 431 connected to each other in the Y direction, and thus, there are several conductive regions 531 connected to each other in the Y direction. There are also generally at least two first vias 528A in the Y direction.

[0138] The filling of the orifices 527B forms second vias 528B which are connected to the conductive elements 411 and which participate in the interconnection of the conductive elements 411 of the first metallization level 410 with conductive elements of a second metallization level (not shown).

[0139] The filling is carried out using a suitable deposition technique such as an ALD technique, or by a PVD or CVD technique, or by electrodeposition.

[0140] As the cavities 431 are connected together in one or more directions of the XY plane, the conductive regions 531 are also connected together, forming a continuous conductive wall. This may form an annular conductive wall such as the annular conductive wall 330 described in connection with FIGS. 3A, 3B and 3C, as the conductive regions 531 are connected together along the entire periphery of the electronic chip, around the circuit region 505.

[0141] [Fig.5B] may correspond to a partial section along the section plane C- C identified in [Fig.3A] of the first level of the interconnection structure 302 of the electronic chip 300. Thus, the conductive regions 531 may correspond to the conductive regions 331 of [Fig.3B], which are in the sealing ring 307, and in the interconnection structure 302, between the circuit region 105 and the sealing element 108. The conductive elements 411 and the vias 403, 528B on the left of [Fig.5B] may correspond to a part of the interconnection structure which is in the circuit region 505, the via 403 on the left then being able to be a contact connected to an electronic component on the semiconductor layer 401. The conductive elements 411 and the vias 403, 528A, 528B on the right of [Fig.5B] may correspond to a part of the structure interconnection which is in the sealing ring region 507, and may correspond to a portion of a sealing element formed in the interconnection structure.

[0142] Not all of the cavities 431 of the same continuous extended cavity are necessarily connected to a first orifice 527A. Indeed, to the extent that the cavities 531 of the same continuous extended cavity are connected to each other, it may be sufficient to have only two orifices 527A to fill the cavities 431 with conductive material, for example a first inlet orifice for the conductive material and a first outlet orifice for the conductive material. However, for example depending on the length of the continuous extended cavity, more than two orifices 527A may be provided so that it can be correctly filled.

[0143] Then, a second metallization level can be formed, by a technique similar to that used to form the first metallization level 410, for example by a subtractive process or by a Damascene-type process, as described in connection with [Fig.4A]. Then, other metallization levels can be formed in a similar manner.

[0144] If it is desired to obtain conductive regions which extend at least up to the second metallization level, or even up to a higher metallization level, the steps described in connection with FIGS. 4A to 4F, 5A, 5B can be reproduced at least once.

[0145] The method described in connection with FIGS. 5A and 5B may be adapted to also form, in the circuit region 505 of the chip, cavities connected to each other between adjacent conductive tracks of the interconnection structure, then fill these cavities connected to each other with a metallic material so as to form a continuous conductive region between the adjacent conductive tracks, at least at the first metallization level of the interconnection structure.

[0146] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0147] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An electronic chip (200; 300) delimited by an edge (110), the electronic chip comprising: - a semiconductor layer (101) extending along a main plane (XY); - an interconnection structure (202; 302) positioned above the semiconductor layer; - a sealing ring (207; 307) arranged in the interconnection structure between the edge (110) of the electronic chip and an electronic circuit region (105) of the electronic chip, the sealing ring including: - a plurality of cavities (231, 231') connected together so as to form at least one continuous annular cavity (230, 230') around the electronic circuit region; and / or - a plurality of conductive regions (331, 331') connected together so as to form at least one annular conductive wall (330, 330') around the electronic circuit region.

2. Electronic chip (200; 300) according to claim 1, wherein the interconnection structure (202; 302) comprises: - a plurality of metallization levels each comprising a conductive layer (103), the conductive layers of two successive metallization levels being connected to each other by conductive vias (106) and / or conductive strips (112) of the interconnection structure; and - insulating layers (111) in which the conductive layers (103), the conductive vias (106) and / or the conductive strips (112) are embedded; the interconnection structure (202; 302) being for example connected to the semiconductor layer (101) by means of another conductive via (106) and / or an electrical contact.

3. Electronic chip (200; 300) according to claim 1 or 2, wherein the cavities (231, 231') and / or the conductive regions (331, 331') extend at least up to a first metallization level (Ml) of the interconnection structure (202; 302).

4. Electronic chip (200; 300) according to any one of claims 1 to 3, in which the cavities (231, 231') and / or the conductive regions (331, 331') extend at least up to a interface level between conductive vias (108) and conductive layers (103) of two successive metallization levels of the interconnection structure (202; 302), for example up to an interface level between conductive vias and conductive layers of first and second metallization levels of the interconnection structure.

5. Electronic chip (200; 300) according to any one of claims 1 to 4, wherein the cavities (231, 231') and / or the conductive regions (331, 331') extend to the semiconductor layer (101).

6. Electronic chip according to any one of claims 1 to 4, in which the cavities and / or the conductive regions stop at a non-zero distance from the semiconductor layer.

7. An electronic chip according to any one of claims 1 to 6, wherein the conductive regions are metallic regions, for example comprise tungsten, or are mainly made of tungsten.

8. An electronic chip according to any one of claims 1 to 7, wherein the sealing ring (207; 307) includes a sealing element (108) comprising an annular conductive plate (103A) in each metallization level of the interconnection structure (202; 302), two annular conductive plates of two successive metallization levels being connected to each other in a direction (Z) perpendicular to the main plane (XY) by an annular conductive strip (112).

9. An electronic chip (200; 300) according to claim 8, wherein the at least one annular continuous cavity comprises a first annular continuous cavity (230) between the electronic circuit region (105) and the sealing element (108) and / or a second annular continuous cavity (230') between the sealing element (108) and the edge (110) of the electronic chip.

10. An electronic chip according to claim 8 or 9, wherein the at least one annular conductive wall comprises a first annular conductive wall (330) between the electronic circuit region (105) and the sealing element (108) and / or a second annular conductive wall (330') between the sealing element (108) and the edge (110) of the electronic chip.

11. An electronic chip according to any one of claims 1 to 10, further comprising, in the electronic circuit region, interconnected cavities, and / or interconnected conductive regions, between two adjacent conductive elements of the interconnection structure.

12. A method of manufacturing an electronic chip, the method comprising: - providing a structure comprising a semiconductor layer (401) and a first metallization level (410) of a future interconnection structure above the semiconductor layer, the structure comprising an electronic circuit region (405; 505) which comprises electronic circuits formed in and on the semiconductor layer, and a sealing ring region (407; 507) around the electronic circuit region, and the first metallization level comprising conductive elements (411) of a conductive layer insulated from each other by insulating elements (412) of a first insulating layer (413); - forming first holes (423) in the sealing ring region (407; 507) through the first insulating layer (413) between two adjacent conductive elements among the conductive elements;- widening the first orifices (423) by etching, so as to form in the sealing ring region (407; 507) open cavities (424) connected to each other around the electronic circuit region; - forming a second insulating layer (425) above the open cavities (424) and the first insulating layer (413), so as to close the open cavities, forming cavities (431) connected to each other around the electronic circuit region (405; 505), the connected cavities forming at least one continuous annular cavity around the electronic circuit region.;

13. The method of claim 12, further comprising, before forming the first orifices (423), depositing a protective layer (421) above the first insulating layer (413) and the conductive elements (411), then forming openings (421 A) by etching in the protective layer, the first orifices being formed at right angles to the openings.

14. The method of claim 12 or 13, further comprising: - forming at least two second orifices (527A) by etching into the second insulating layer (425) up to at least two of the cavities (431) in the sealing ring region (507); and - filling the second orifices with a conductive material, for example a metallic material, the filling of the second orifices being carried out so as to fill the cavities (431), forming conductive regions (531) connected to each other, and thus an annular conductive wall around the electronic circuit region (505).

15. The method of claim 14, wherein filling the second orifices (527A) also forms first conductive vias (528A) connected to the annular conductive wall.

16. A method according to any one of claims 12 to 15, further comprising: - forming third orifices (527B) by etching in the second insulating layer (425), each third orifice extending to one of the conductive elements (411); and - filling the third orifices with a conductive material, for example a metallic material, forming second conductive vias (528B) connected to the conductive elements.

17. A method according to claim 16 in its dependency with claim 14 or 15, wherein the formation of the third orifices is carried out at the same time as the formation of the second orifices, and / or the filling of the third orifices is carried out at the same time as the filling of the second orifices.

18. A method according to any one of claims 12 to 17, further comprising forming, in the electronic circuit region, interconnected cavities, and / or interconnected conductive regions, between two adjacent conductive elements of the interconnect structure.

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