Floating-point processor

Abstract

The invention relates to a processor comprising: an integer processing unit (ALU), a floating-point processing unit (FPU), a register bank (RGBK), an external data bus (DTB), a data path connecting the register bank to the floating-point processing unit, the integer processing unit, and the external data bus, and a processing chain configured to process at least partially simultaneous integer and floating-point instructions, the processing chain comprising common stages for processing an integer and a floating-point instruction, and at least one additional execution stage for executing a floating-point operation. Figure 1

Description

Title of the invention: Floating-point processor technical field

[0001] The present invention relates to the field of processors and in particular microprocessors, especially microprocessors for embedded systems adapted to space applications. State of the art

[0002] There are three types of processor architectures for embedded space systems: microcontrollers, signal processing processors, and general-purpose processors. Microcontrollers are small processors that control command and control operations using actuators and sensors, such as managing the solar panels of a satellite. Microcontrollers do not incorporate floating-point operators and operate only at several tens of megahertz.

[0003] Digital signal processors (DSPs) are specialized for high-performance computing. DSPs can perform fixed-point or floating-point operations. To ensure high speed (low latency) and fast results, arithmetic operations are executed in a single clock cycle. The operating frequency of this type of processor is several hundred MHz. These processors can be used, for example, in star trackers. Such sensors are mounted on a satellite to determine its position based on the location of stars. This positioning function must be performed in real time and requires significant computing power to process and interpret images.

[0004] Finally, general-purpose processors, particularly those used in personal computers and mobile phones, are capable of providing high computing power by using spatial and temporal parallelism. The operating frequency of these processors can reach several gigahertz.

[0005] Regardless of their architecture, processors can use two types of instruction sets: RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). RISC instructions consist exclusively of instructions for simple operations of fixed size. These instructions are therefore easy to decode and quick to execute, but result in a large memory footprint. In CISC instructions, the instructions are of variable size, from 1 to 5 bytes, and are executed in one or more Clock cycles are determined by their complexity. This optimizes them in terms of memory footprint.

[0006] Processors capable of performing floating-point operations generally comprise a processor for integer operations and a coprocessor for floating-point operations. The combination of a processor and a coprocessor allows for the simultaneous performance of integer and floating-point operations. This type of architecture has two register banks and two separate data paths.

[0007] However, applications such as space applications require processors hardened to critical radiative environments. Indeed, the behavior of a circuit can be altered when it is traversed by energetic particles. The energy of these particles is notably capable of modifying the value contained in registers. To overcome this problem, architectures have been proposed implementing three sets of redundant registers and proceeding by majority vote, which results in a significant increase in the number of registers. However, in embedded applications, it is also desirable to limit the number of registers in order to avoid increasing the static and dynamic power consumption of the processor. Indeed, the power consumption of embedded systems, particularly in the space domain, is critical because they mostly operate on batteries recharged by solar panels.

[0008] These various constraints necessitate minimizing the number of registers and memory cells. However, embedded software in space applications requires significant floating-point processing power, particularly double-precision 64-bit. Indeed, the single-precision (32-bit) format is often avoided for fear of overflow during program execution. Conversely, a 32-bit size for integers is preferred for all integer calculations, such as data addressing calculations.

[0009] It is therefore desirable to propose a high-performance processor architecture for performing double-precision floating-point operations, which is both energy-efficient, compact in terms of silicon area occupied, and has an instruction set that allows the design of programs with a reduced memory footprint. Summary

[0010] Embodiments relate to a processor comprising: an integer processing unit, a floating-point processing unit, a register bank, an external data bus, a data path connecting the register bank to the floating-point processing unit, to the integer operation processing unit, and to the external data bus, and a processing chain configured to process at least partially simultaneously integer operation instructions and floating-point operation instructions, the processing chain including common stages for processing an integer operation instruction and a floating-point operation instruction, and at least one additional execution stage for executing a floating-point operation.

[0011] According to one embodiment, the processor includes a program memory access bus separate from the external data bus.

[0012] According to one embodiment, the processor includes a set of CISC-type instructions and is configured to transform CISC instructions into RISC instructions before executing them.

[0013] According to one embodiment, the register bank comprises only 32 32-bit registers that can be used as 16 64-bit registers.

[0014] According to one embodiment, the integer operation processing unit is configured to process 32-bit operands.

[0015] According to one embodiment, the floating-point operation processing unit is configured to process 64-bit operands.

[0016] According to one embodiment, the processor is configured to manage data dependencies in the data path using internal registers.

[0017] According to one embodiment, the processing chain comprises: an instruction acquisition stage, an instruction decoding stage, an instruction operand selection stage, a first execution stage of an instruction operation, including writing the result of the operation into a register of the register bank, and two additional execution stages dedicated to executing a floating-point operation, between the selection stage and the first execution stage.

[0018] According to one embodiment, the decoding, selection and execution stages are separated by internal registers. Brief description of the figures

[0019] The present invention will be better understood with the aid of the following description of exemplary embodiments with reference to the accompanying figures, in which identical reference signs correspond to structurally and / or functionally identical or similar elements.

[0020] [Fig-1] Figure 1 schematically represents the architecture of a processor, according to a method of implementation,

[0021] [Fig.2] Figure 2 represents a simple instruction processing chain, put implemented in the processor, according to one embodiment,

[0022] [Fig.3] Figure 3 represents a comma instruction processing chain floating-point number, implemented in the processor, according to one embodiment,

[0023] [Fig. 4] Figure 4 illustrates a case of processor processing of a sequence of a floating-point instruction followed by two integer instructions, according to one embodiment,

[0024] [Fig. 5] Figures 5A, 5B, 5C illustrate various examples of treatment by the three-instruction serial processor. Detailed description

[0025] Figure 1 shows the architecture of a PRC processor and, in particular, the architecture of the processor's data path, according to one embodiment. The PRC processor's data path includes, among other things, an RGBK register bank, an ALU (arithmetic logic unit), an FPU (floating-point processing unit), an IDEC (instruction decoder), an IR (instruction register), and a PC (instruction pointer register). The RGBK register bank comprises 32-bit registers that can be paired to form 16 64-bit registers. The ALU is configured to perform arithmetic and logic operations with one or two input operands and one output operand.The ALU unit receives as input one or two 32-bit operands each from the RGBK register bank, and provides a 32-bit output data which is transmitted via an internal DBI1 data bus to an input of the RGBK register bank or to an external DTB data bus giving access to a data memory space connected to the PRC processor and addressed by the external ADB bus with address.

[0026] The FPU is configured to perform floating-point operations. For this purpose, the FPU is connected to the RGBK register bank via two 64-bit data buses (4 x 32 bits), and to the DTB data bus and the RGBK register bank via two data buses: the DBI1 bus and an internal 32-bit data bus, DBI2. The IDEC decoder determines, from the instruction in the IR register, the commands to be executed by the ALU or FPU, and the register numbers to be selected in the RGBK register bank to execute the instruction. The DTB data bus can be connected to the internal buses DBI1 and DBI2, for example, via multiplexers / demultiplexers, to select which of the DBI1 and DBI2 buses to connect to the DTB bus. The PC register is connected to an external 24-bit program address APB bus providing access to a program memory space connected to the PRC processor.The instruction register (IR) is connected to an external 32-bit instruction bus (PGB) to receive an instruction to be executed, located at the address stored in the PC register. The FPU, for example, conforms to the IEEE 754 standard for floating-point arithmetic.

[0027] Thus, the processor has a Harvard-type architecture, having a program memory space access bus (PGB / APB) separate from the data memory space access bus (DTB / ADB).

[0028] The PRC processor includes a single data path connecting the RGBK register bank, the ALU and FPU units, and the external DTB data bus. In one embodiment, the number of registers in the RGBK register bank is limited to 32 32-bit registers. This register bank size is compatible with all C language compilers, such as the CompCert certified compiler, which is used particularly for coding critical embedded applications, such as those in the space sector. This compiler performs few performance optimizations and therefore uses very few registers. Consequently, a larger number of registers may be unnecessary from the compiler's perspective.

[0029] According to one embodiment, the PRC processor is of a hybrid type in that it includes a CISC instruction set, with the IDEC decoder configured to decode and transform the CISC instructions into RISC instructions. As a result, the PRC processor can quickly execute instructions on the single data path while being able to access all of the processor's resources in parallel. Thus, the memory footprint of programs is minimized while maintaining good performance.

[0030] In one embodiment, the data path is configured to manage the interactions of the PRC processor with external memory. The PRC processor's data path is further configured to distribute the processing of each instruction across several successive stages of a processing pipeline. Thus, the execution of a new instruction can be activated as soon as the first stage is available, without waiting for the execution of the previous instruction to be fully completed.

[0031] Thanks to the fact that the PRC processor integrates a single data path, the processing chain can implement a number of stages to process either an integer instruction involving the ALU unit or a double-precision floating-point instruction involving the FPU unit, with some stages of the processing chain being used only to process a floating-point instruction. In one embodiment, the processing chain comprises three operation execution stages, only one of these three execution stages being used to process an integer instruction.

[0032] According to one embodiment, the processing chain comprises four stages corresponding to four processing steps of one clock cycle each, and two additional operation execution stages corresponding to two steps of successive processing of one clock cycle each, specifically configured to perform a floating-point operation.

[0033] It is therefore possible to maintain a certain parallelism between the processing of integer and floating-point instructions, while reducing the number of registers. Furthermore, data dependencies are completely managed by the data path, which avoids the need for the compiler to set "nop" (or "no operation") instructions. The size of the executable code is thus reduced.

[0034] Figures 2 and 3 represent steps in an example processing chain. Figure 2 shows the steps executed respectively by the stages of the processing chain during the execution of an entire instruction involving the ALU. These steps include ACQ loading the instruction located in the IR register and updating the program pointer PC, DEC decoding the instruction, SEL selection and reading the operands from the registers in the RGBK register bank, and finally EXC execution of the entire operation corresponding to the instruction, including writing the result of the operation to a register in the RGBK register bank. The ACQ, DEC, SEL, and EXC steps are executed successively during cycles C1 to C4, respectively.

[0035] Figure 3 illustrates the steps executed by the processing chain stages during the execution of a floating-point instruction, thus involving the FPU. These steps include the ACQ, DEC, and SEL steps executed to process an integer instruction and three EXC1, EXC2, and EXC3 steps for executing the floating-point operation corresponding to the instruction. The third and final EXC3 step includes writing the result of the operation to a register in the RGBK register bank. The ACQ, DEC, SEL, EXC1, EXC2, and EXC3 steps are executed successively during cycles C1 to C6, respectively.

[0036] The processing chains shown in Figures 2 and 3 include internal registers PR1, PR2, PR3, and PR4 (Figure 1) for implementing the steps ACQ, DEC, SEL, EXC / EXC1, EXC2, and EXC3, respectively, during cycles C1 to C6. The instruction loading cycle C1 (ACQ) is performed at the input of the instruction register IR. The instruction decoding cycle C2 (DEC) is performed by the instruction decoder IDEC. The result of the DEC decoding (operation to be executed and the register numbers containing the operands) is stored in the internal registers PRL. The operand selection and reading cycle C3 (SEL) is performed in the register bank RGBK. The result of the SEL selection (operation to be executed and the operand values) is stored in the internal registers PR2. The EXC / EXC1 execution cycle C4 is executed by the AU unit or a first stage of the FPU unit. The EXC2 and EXC3 execution cycles C5, C6 are performed successively in the FPU unit.Intermediate results from the EXC1 and EXC2 execution steps of a . Instructions from the FPU unit are stored successively in the internal registers PR3 and PR4 in the FPU unit.

[0037] It should be noted that simple floating-point operations such as addition and multiplication can be executed in six clock cycles. However, some more complex instructions such as division or square root are broken down into several simple floating-point operations, and therefore require more than six clock cycles to be processed.

[0038] Figure 4 illustrates an optimal case of a sequence of three instructions comprising a floating-point arithmetic instruction followed by two integer arithmetic instructions. Thanks to the division of the processing of each instruction into several steps, the processing of the first integer arithmetic instruction can start as soon as the ACQ step of the floating-point arithmetic instruction is completed. Similarly, the processing of the second integer arithmetic instruction can start as soon as the ACQ step of the first integer arithmetic instruction is completed.Because the processing of the floating-point instruction involves three execution steps (EXC1, EXC2, EXC3), the processing of the first integer instruction completes (at the end of the EXC step) simultaneously with the second execution step (EXC2) of the floating-point instruction processing, and the processing of the second integer instruction completes simultaneously with the third execution step (EXC3) of the floating-point instruction processing. Therefore, the three instructions in the sequence are processed in parallel by the PRC processor in six cycles (C1-C6).

[0039] Figure 5A illustrates an example of processing by the PRC processor of a sequence of a floating-point multiplication instruction followed by two integer addition instructions, corresponding to the optimal case illustrated in Figure 4. This sequence can be written in assembly language as follows:

[0040] fmul rO, rl, r2; rO = rl * r2

[0041] add r3, r4, r5; r3 = r4 + r5

[0042] add r4, r3, r6; r4 = r3 + r6

[0043] The first instruction is a floating-point multiplication "fmul" of the contents of register rl (32 bits) by the contents of register r2 (32 bits), with register r0 (64 bits) receiving the result of the multiplication. The second instruction is an integer addition "add" of the contents of register r4 (32 bits) with the contents of register r5 (32 bits), with register r3 (32 bits) receiving the result of the addition. The third instruction is an integer addition "add" of the contents of register r3 (32 bits) with the contents of register r6 (32 bits), with register r4 (32 bits) receiving the result of the addition. In this example, there is no register access conflict, particularly with register r3, since register SEL can be performed in The EXC, EXC3 instruction sequence of the previous operation using the same register is executed simultaneously. Therefore, this instruction sequence can be processed by the PRC processor in six C1-C8 cycles instead of 14 cycles if no parallelism were implemented.

[0044] Figure 5B illustrates an example of the PRC processor processing a sequence of a floating-point multiplication instruction "fmul", followed by two integer addition instructions "add". This example does not correspond to the optimal case illustrated in Figure 4, because the instruction following the floating-point instruction uses a register (rO) also used by the latter. This sequence can be written in assembly language as follows:

[0045] fmul rO, rl, r2; rO = rl * r2

[0046] add r3, rO, r4; r3 = rO + r4

[0047] add r5, r3, r6; r5 = r3 + r6

[0048] The first instruction is a floating-point multiplication "fmul" of the contents of register rl (32 bits) by the contents of register r2 (32 bits), with register rO (64 bits) receiving the result of the multiplication. The second instruction is an integer addition "add" of the contents of register rO (32 bits) with the contents of register r4 (32 bits), with register r3 (32 bits) receiving the result of the addition. The third instruction is an integer addition "add" of the contents of register r3 (32 bits) with the contents of register r6 (32 bits), with register r5 (32 bits) receiving the result of the addition.Since access to register rO is locked by the execution of the first "fmul" instruction until the beginning of EXC3 (cycle C6), the SEQ sequencer waits for two cycles to elapse before beginning processing the second instruction in cycle C4. The SEL step for selecting register rO can only be performed starting from EXC3 of the "fmul" instruction (cycle C6). In contrast, using register r3 in the two addition instructions does not pose a problem because it can be selected (SEL step) during an EXC execution step in which it is used. Thus, this instruction sequence can be processed by the PRC processor in eight cycles C1-C8 instead of 14 cycles if no parallelism were implemented.

[0049] Figure 5C illustrates an example of the PRC processor processing a sequence of three floating-point instructions, comprising a multiplication "fmul" followed by two additions "fadd". This sequence can be written in assembly language as follows:

[0050] fmul rO, rl, r2; rO = rl * r2

[0051] fadd r3, rO, r4; r3 = rO + r4

[0052] fadd r5, r3, r6; r5 = r3 + r6

[0053] The first instruction is the floating-point multiplication "fmul" of the content of the rl register (32 bits) by the contents of the r2 register (32 bits), the rO register (on 64 bits) receiving the result of the multiplication. The second instruction is a floating-point "fadd" addition of the contents of register rO (on 32 bits) with the contents of register r4 (on 32 bits), register r3 (on 64 bits) receiving the result of the addition. The third instruction is a floating-point "fadd" addition of the contents of register r3 (on 32 bits) with the contents of register r6 (on 32 bits), register r5 (on 64 bits) receiving the result of the addition. Here again, access to register rO is locked by the execution of the first instruction until the beginning of the EXC3 step (cycle C6) of the execution of the "fmul" instruction. The SEQ sequencer therefore waits for two cycles to elapse before starting the processing of the second "fadd" instruction at cycle C4, the SEL step of selecting the rO register can only be carried out from the EXC3 step (cycle C6) of the execution of the second "fadd" instruction.Similarly, access to register r3 is locked by the execution of the second "fadd" instruction until the beginning of the EXC3 step (cycle C9) of the "fadd" instruction's execution. As a result, the SEQ sequencer waits for two cycles to elapse before beginning the processing of the third "fadd" instruction in cycle C7, since the SEL step for selecting register r3 can only be performed from the EXC3 step (cycle C9) of the preceding "fadd" instruction. Thus, this sequence of instructions can be executed in 12 cycles Cl-Cl2, instead of 18 if no parallelism were implemented.

[0054] It will be evident to those skilled in the art that the present invention is susceptible to various embodiments and applications. In particular, the invention is not limited to a processor with a Harvard-type architecture. Indeed, it is not necessary for the data access bus to be separate from the program instruction access bus to benefit from the advantages offered by the described processor architecture. In particular, the processing chain described above and the implementation of a single data path can be implemented in a processor having a single data and program instruction access bus.

[0055] Nor is it necessary for the processor's instruction set to be of the CISC or RISC type. Indeed, the processor's IDEC instruction decoder can be adapted to either of these two types of instruction set, given that the choice of instruction set type influences the memory footprint of the programs that can be executed by the processor.

[0056] Furthermore, the internal and external bus sizes shown in Figure 1 are provided by way of example. The processor architecture described above can be easily adapted to any other data, program, and address bus sizes.

[0057] Furthermore, it may be provided that the processing chain comprises stages of a different nature and number than those previously described. Thus the processing chain For example, it may include five stages common to the processing of integer and floating-point operations, and two additional stages dedicated to the execution of floating-point operations. The common stages may include a stage for loading the instruction to be executed, a stage for decoding the instruction, a stage for executing the instruction, a stage for transferring between a register and memory, and a stage for storing the result of the execution in a register. In other embodiments, some of the stages listed above are grouped into a single stage.

Claims

Demands

1. 1. A processor comprising: an integer operations processing unit (ALU), a floating-point operations processing unit (FPU), a register bank (RGBK), an external data bus (DTB), a data path connecting the register bank to the floating-point operations processing unit, the integer operations processing unit, and the external data bus, and a processing chain configured to process at least partially concurrently integer operation instructions and floating-point operation instructions, the processing chain comprising common stages for processing an integer operation instruction and a floating-point operation instruction, and at least one additional execution stage for executing a floating-point operation.

2. 2. Processor according to claim 1, comprising a program memory access bus (APB, PGB) separate from the external data bus (DTB).

3. 3. Processor according to claim 1 or 2, wherein the processor (PRC) comprises a CISC-type instruction set and is configured to transform CISC instructions into RISC instructions before executing them.

4. 4. Processor according to any one of claims 1 to 3, wherein the register bank (RGBK) comprises only 32 32-bit registers that can be operated as 16 64-bit registers.

5. 5. Processor according to any one of claims 1 to 4, wherein the integer operations processing unit (ALU) is configured to process 32-bit operands.

6. 6. Processor according to any one of claims 1 to 5, wherein the floating-point processing unit (FPU) is configured to process 64-bit operands.

7. 7. Processor according to any one of claims 1 to 6, configured to handle data dependencies in the data path using internal registers (PR1-PR4).

8. 8. A processor according to any one of claims 1 to 7, wherein the processing chain comprises:

9. an acquisition stage (ACQ) of an instruction to be executed, a decoding stage (DEC) of the instruction, an operand selection stage (SEL) of the instruction, a first execution stage (EXC, EXC3) of an instruction operation, including writing the result of the operation to a register in the register bank (RGBK), and two additional execution stages (EXC1, EXC2) dedicated to executing a floating-point operation, between the selection stage and the first execution stage. Processor according to claim 8, wherein the decoding (DEC), selection (SEL) and execution (EXC, EXC1, ECX2, EXC3) stages are separated by internal registers (PR1-PR4).

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