Auxiliary circuit for a gate transistor control device and associated control device

Abstract

An auxiliary circuit (200b) for a power transistor (T2) control device, the auxiliary circuit (200b) being configured to connect to the gate and drain of the gate transistor (T2), the auxiliary circuit (200b) being configured to receive from a main circuit (200a) at least one switching command (OUT_H, OUT_B) and output a gate control (GRDV), the auxiliary circuit (200b) being configured to output a nominal desaturation voltage (DESAT), the auxiliary circuit (200b) comprising at least one auxiliary comparator circuit (224) configured to compare a voltage representative of a drain voltage (VDS) to an advanced desaturation threshold (Vth) so as to achieve early desaturation detection, the auxiliary circuit (200b) being configured to modify the gate control (GDRV) upon early detection. Abstract Figure: Figure 5

Description

Title of the invention: Auxiliary circuit for a gate transistor control device and associated control device technical field

[0001] The present invention relates to the field of electronics and, more particularly, to a control device for a gate transistor.

[0002] Climate change is a major concern for many legislative and regulatory bodies worldwide. Indeed, various restrictions on carbon emissions have been, are being, or will be adopted by various states. In particular, an ambitious standard applies to both new types of aircraft and those already in service, requiring the implementation of technological solutions to bring them into compliance with current regulations. Civil aviation has been actively working for several years now to contribute to the fight against climate change.

[0003] Technological research efforts have already led to very significant improvements in the environmental performance of aircraft. The Applicant takes into account the factors impacting all phases of design and development in order to obtain aeronautical components and products that are less energy-intensive, more environmentally friendly, and whose integration and use in civil aviation have moderate environmental consequences, with the aim of improving the energy efficiency of aircraft.

[0004] Consequently, the Applicant is constantly working to reduce its negative climate impact by using methods and operating virtuous development and manufacturing processes that minimize greenhouse gas emissions to the minimum possible in order to reduce the environmental footprint of its activity.

[0005] This sustained research and development work focuses on new generations of aircraft engines, the weight reduction of aircraft, in particular through the materials used and lighter on-board equipment, the development of the use of electrical technologies to provide propulsion, and, as essential complements to technological progress, aviation biofuels.

[0006] It has been known that an aircraft can be equipped with a plurality of electric propulsion motors. In practice, when the aircraft includes a direct current voltage source to power the electric propulsion motor, for example an electric battery, it is known to use one or more inverters to convert the direct current voltage into an alternating current voltage for the electric propulsion motor.

[0007] By way of example, with reference to [Fig. 1], an electric machine M is shown, powered by an electric battery BAT via an inverter OND. As is known, the inverter OND comprises several bridge arms, each having at least one gate transistor T1-T6, generally of the IGBT or SiC MOSFET type to improve the performance of the inverter OND, which is controlled to open or close. In practice, the opening and closing of a gate transistor T1-T6 is driven by a gate driver 100 of the gate of the gate transistor T1-T6. Such a driver 100 is known by its English abbreviation "driver".

[0008] Such a control device 100 allows the opening and closing of a gate transistor T1-T6 to be controlled according to a control signal, generally of the PWM type, emitted by a control circuit (not shown).

[0009] With reference to [Fig. 1], the OND inverter generally comprises three bridge arms B1, B2, B3, each bridge arm B1, B2, B3 having two branches, each containing a gate transistor T1-T6. A critical failure can occur when two gate transistors T1-T6 of the same bridge arm B1, B2, B3 are closed simultaneously. Therefore, if the first bridge arm B1 has a first gate transistor T1 short-circuited, it is important that the second gate transistor T2 can open without being damaged.

[0010] The most critical case occurs when a short circuit is established upon the closing of the second gate transistor T2 while the first gate transistor T1 is already short-circuited. Indeed, in this case, the second gate transistor T2 must, as soon as it closes, withstand the voltage of the electric battery BAT and must conduct a short-circuit current for a short-circuit duration.

[0011] In practice, to detect a short circuit, the control device monitors a desaturation voltage DESAT of the second gate transistor T2 which makes it possible to determine the occurrence of a short circuit.

[0012] During a short circuit, the second gate transistor T2 heats up, and it is necessary that it be able to open very quickly to prevent its destruction. For example, an IGBT gate transistor must open in less than 10 μs, while a SiC MOSFET gate transistor must open in less than 0.6 μs. Furthermore, it is important that the second gate transistor T2 opens in a controlled manner without being too rapid. Indeed, if the second gate transistor T2 opens too quickly (too rapid a change in the control voltage), an overvoltage is generated and can exceed the avalanche voltage of the second gate transistor T2, which will be destroyed by this overvoltage.

[0013] It is therefore necessary to have a control device 100 that can perform a controlled opening upon detection of desaturation caused by a short circuit. It is customary to say that a transistor is desaturated when it is prevented to close due to the action of the short circuit. This is a misuse of language because desaturation is the consequence of the short circuit.

[0014] In the prior art and with reference to [Fig. 2], a control device 100 compatible with an IGBT or SiC MOSFET gate transistor is known, comprising a main circuit 100a, in particular an integrated circuit, and an auxiliary circuit 100b, formed of discrete electronic components. The auxiliary circuit 100b is configured to measure a drain voltage Vds, which corresponds to the potential difference between the Drain and the Source of said power transistor T2, in order to provide a desaturation voltage DESAT to the main circuit 100a.

[0015] The main circuit 100a of the control device 100 according to the prior art includes an input for receiving a PWM control signal to determine a high output OUT_H and a low output OUT_L, which are processed by the auxiliary circuit 100b to determine a gate voltage GDRV to control the power transistor T2. The main circuit 100a includes a fault output FLT that allows for the detection of a short circuit by processing the desaturation voltage DESAT.

[0016] The auxiliary circuit 100b includes two resistors Rg(ON) and Rg(OFF), connected respectively to the high output OUT_H and the low output OUT, which are connected to the gate of the power transistor T2 in order to determine the gate voltage GDRV.

[0017] In particular, the main circuit 100a includes a comparator circuit 101 configured to trigger a short-circuit opening when the desaturation voltage DESAT exceeds a desaturation threshold VDS* during a phase in which said power transistor T2 is switched ON, i.e., closed. Preferably, the main circuit 100a includes a current source circuit 102 activated when the power transistor T2 is switched ON to perform a desaturation detection inhibition function for the duration of a normal switching operation. As is known, this helps to limit errors during the comparison.

[0018] The main circuit 100a includes a control circuit 103 for the opening of the power transistor T2. When the desaturation voltage DESAT exceeds the desaturation threshold Vds* after an inhibition time, this circuit slowly opens the power transistor T2 without generating excessive overvoltage. Such a function is known to those skilled in the art by its English acronym STO for "Soft Tum Off".

[0019] In a known manner, the main circuit 100a includes a fault management circuit 105 configured to output a fault signal FLT in the event of a desaturation detected by the comparator circuit 101. Preferably, the fault management circuit 105 is configured to store the occurrence of a fault. The circuit of Fault management 105 is configured to be reset following a fault. Such a reset is also called "resetting" the control device 100.

[0020] Such a control device 100 has several disadvantages.

[0021] First of all, the control device 100 has a delay which does not allow for the detection of desaturation in a sufficiently reactive manner, which is problematic for a power transistor of the SiC MOSFET type which can be damaged rapidly.

[0022] In practice, the delay consists of: • a first delay Tleb determined between the ON switching command of the power transistor T2 and the start of the inhibition of the power transistor T2, • a second configurable delay, Tblank, called "inhibition delay" or "blanking delay," which occurs when a short circuit is detected after an ON closing command. • a third delay Tdesat_out between the moment when the desaturation voltage DESAT exceeds the desaturation threshold VDS * and the start of the opening command OFF of the power transistor T2 with the STO function.

[0023] With reference to [Fig.2], the auxiliary circuit 100b includes an inhibition circuit 104, also called "Blanking", which allows the second delay to be adjusted by the selection of discrete electronic components, in particular, the capacitance Cblnk.

[0024] In practice, the combined effect of the first and third delays alone exceeds the maximum acceptable short-circuit duration for a SiC MOSFET power transistor (<600ns). Therefore, an immediate solution would be to replace the main 100a circuit with a circuit specifically designed for controlling the SiC MOSFET to enable more responsive detection, but this significantly increases costs.

[0025] In addition to the drawbacks related to the delay, the technique of controlled short-circuit opening by increasing the gate resistance of the power transistor T2 necessitates a compromise between the overvoltage at short-circuit opening and the losses at normal opening, because the time constant for the establishment of the gate voltage GDRV at short-circuit opening also depends on a gate capacitance of the transistor, comprising an intrinsic gate capacitance (inherent to the transistor) and, in some cases, an external capacitance added to slow down the opening of a short circuit. Furthermore, this gate capacitance slows down normal switching, which increases switching losses. Also, this capacitance is charged and discharged with each switching cycle, which increases the gate drive power consumption and therefore the size of its power supply.This is particularly problematic with a SiC MOSFET power transistor used at high switching frequencies.

[0026] The invention thus aims to eliminate at least some of these drawbacks. PRESENTATION OF THE INVENTION

[0027] The invention relates to an auxiliary circuit for a control device of a power transistor, the auxiliary circuit being configured to connect to the gate and drain of the gate transistor, the auxiliary circuit being configured to receive from a main circuit of the control device at least one switching command and to output a gate command of the gate transistor, the auxiliary circuit being configured to output a nominal desaturation voltage, representative of a short circuit, to the main circuit so as to achieve nominal desaturation detection.

[0028] The auxiliary circuit is notable in that it includes at least one auxiliary comparator circuit configured to compare a voltage representative of a drain voltage, at an advanced desaturation threshold so as to achieve early detection of desaturation, the auxiliary circuit being configured to modify the gate control in the event of early detection.

[0029] Thanks to the auxiliary comparator circuit, a short circuit is detected earlier than a short circuit would be detected by a main circuit, which is advantageous for driving a SiC MOSFET gate transistor. This allows the gate control provided by the main circuit to be modified to drive an early turn-off and prevent the conduction of a short circuit for an excessively long time, which could damage the gate transistor. A rapid comparison with a low, advanced desaturation threshold enables reactive detection. Advantageously, this allows the use of a main circuit adapted for an IGBT power transistor, which has a lower turn-off reactivity, while retaining its technical (isolation, STO, reset, etc.) and economic advantages.

[0030] According to one aspect, the auxiliary circuit includes a two-stage switching circuit configured to define an intermediate voltage step during a switching command in the event of early detection. The use of an intermediate step allows for partial switching, which protects the gate transistor. Any risk of overvoltage during switching can thus be reduced.

[0031] According to one aspect, the auxiliary circuit includes a matching circuit configured to boost the output control of the auxiliary comparator circuit up to the nominal desaturation voltage. A rapid comparison with a low-value advanced desaturation threshold enables reactive detection. The matching circuit allows this value to be increased so that it falls within a typical range for the nominal desaturation voltage. In other words, this allows a nominal desaturation voltage to be simulated for the main circuit. while a lower desaturation voltage was detected. Thus, the main circuit receives a nominal desaturation voltage within a typical range. This allows the main circuit to perform its functions optimally.

[0032] According to one aspect, the auxiliary circuit includes a delay circuit configured to delay the output command of the auxiliary comparator circuit before the nominal desaturation voltage is applied. A rapid comparison enables reactive detection. The delay circuit temporarily inhibits detection by the main circuit. In other words, it delays the main circuit's response. Thus, the comparator circuit acts before the main circuit, which receives a nominal desaturation voltage at an optimal time. This allows the main circuit to perform its functions optimally.

[0033] According to one aspect, the auxiliary circuit includes an inhibition circuit configured to generate a stabilization delay of the voltage representative of the drain voltage for the comparator circuit during the switching time.

[0034] According to one aspect, the two-level switching circuit includes an additional capacitor. This limits the decay rate of the gate control current at the end of the intermediate voltage plateau and thus limits the overvoltage at the switching of transistor T2.

[0035] According to one aspect, the two-stage opening circuit is controlled by the output of the adaptation circuit. Thus, the two-stage opening command occurs before the conventional opening command of the main circuit.

[0036] Also presented is a gate transistor control device comprising a main circuit and an auxiliary circuit as previously presented, the auxiliary circuit being configured to receive from the main circuit of the control device at least one switching command, the auxiliary circuit being configured to output a nominal desaturation voltage representative of a short circuit to the main circuit so as to achieve nominal desaturation detection.

[0037] In one aspect, the main circuit is in the form of an integrated circuit, and the auxiliary circuit is in the form of discrete components. This allows the use of a main circuit with proven functions and reduced cost, while optimizing performance, transparently to the main circuit, with the auxiliary circuit being a SiC MOSFET-type gated transistor.

[0038] According to one aspect, the main circuit includes a comparator circuit configured to compare the nominal desaturation voltage to a nominal desaturation threshold so as to achieve nominal desaturation detection, the main circuit being configured to modify the switching control in the event of Nominal detection. This allows the main circuit to perform a STO function after the auxiliary circuit, i.e., when the short-circuit current has already been canceled by the action of the auxiliary circuit. Preferably, the nominal desaturation threshold is higher than the advanced desaturation threshold.

[0039] Also presented is an electrical converter comprising a plurality of gate transistors, at least one gate transistor being associated with a control device as previously described, in particular, an inverter. Preferably, the inverter powers at least one propulsion or non-propulsion machine of an aircraft.

[0040] A method for controlling a power transistor by an auxiliary circuit as previously described is also presented, the method comprising steps consisting of: • Compare a voltage representative of a drain voltage to an advanced desaturation threshold in order to achieve early detection of desaturation, and • Modify the grid command in case of early detection. PRESENTATION OF THE FIGURES

[0041] The invention will be better understood upon reading the following description, given by way of example, and referring to the following figures, given by way of non-limiting examples, in which identical references are given to similar objects.

[0042] Fig. 1 is a schematic representation of a power supply system for an electric machine using an electric battery via an inverter comprising control devices.

[0043] Fig. 2 is a schematic representation of a control device according to the prior art.

[0044] Fig. 3 is a schematic representation of a power supply system for an electric machine by means of an electric battery via an inverter comprising control devices according to the invention.

[0045] Fig. 4 is a schematic representation of a control device according to the invention.

[0046] Fig. 5 is a schematic representation of a first embodiment of an auxiliary circuit of the control device.

[0047] Fig. 6 is a schematic representation of an example of use of the auxiliary circuit of Fig. 5.

[0048] Fig. 7 is a schematic representation of an example of use of the auxiliary circuit of Fig. 5.

[0049] Fig. 8 is a schematic representation of another embodiment of an auxiliary circuit of the control device.

[0050] Fig. 9 is a schematic representation of another embodiment of an auxiliary circuit of the control device.

[0051] The [Fig. 10] is a schematic representation of another embodiment of an auxiliary circuit of the control device.

[0052] The [Fig. 11] is a schematic representation of another embodiment of an auxiliary circuit of the control device.

[0053] The [Fig. 12] is a schematic representation of another embodiment of an auxiliary circuit of the control device.

[0054] It should be noted that the figures set out the invention in detail to implement the invention, said figures being of course able to serve to better define the invention where appropriate. DETAILED DESCRIPTION OF THE INVENTION

[0055] The invention will be presented in the aeronautical context for an aircraft propulsion electric machine. In such a context, operational safety is paramount. It goes without saying that the invention also applies to a non-propulsive aircraft propulsion electric machine. It is nevertheless self-evident that the invention applies to other technical fields in transportation or industry for any type of electric machine.

[0056] With reference to [Fig. 3], an electric machine M is shown, powered by an electric battery BAT via an inverter OND. As is known, the inverter OND comprises several bridge arms, each having at least one gate transistor T1-T6, generally of the IGBT or MOSFET type, which is controlled to turn on or off. In this example, the gate transistor is a MOSFET-type power gate transistor, in particular, of silicon SiC technology. As explained previously, such a power transistor must be reactively turned on without generating an overvoltage exceeding its breakdown voltage.

[0057] With reference to [Fig. 3], each gate transistor T1-T6 is associated with a gate driver 200 configured to control the opening and closing of each gate transistor T1-T6. Such a driver 200 is known by its English abbreviation "driver".

[0058] The control device 200 allows the opening (corresponding to a non-conducting or OFF state) and the closing (corresponding to a conducting or ON state) of a gate transistor T1-T6 to be controlled according to a control signal, generally of the PWM type, emitted by a control circuit (not shown).

[0059] With reference to [Fig. 3], the OND inverter comprises three bridge arms Bl, B2, B3, each bridge arm B1, B2, B3 having two branches, each containing a gate transistor T1-T6. A critical short-circuit failure can occur when one of the two gate transistors T1-T6 is switched ON while the other transistor in the same bridge arm Bl, B2, B3 is already faulty. Therefore, if the first bridge arm Bl has a first gate transistor T1 that is short-circuited, it is important that the second gate transistor T2 can switch on without being damaged.

[0060] As presented in the preamble, the most critical case occurs when a short circuit is established upon the closing of the second gate transistor T2 while the first gate transistor T1 is already short-circuited. Indeed, in this case, the second gate transistor T2 operates in saturated mode from the moment the short circuit is established upon the closing of the second gate transistor T2. The second gate transistor T2 must simultaneously withstand the mains voltage generated by the battery BAT or any other power source and conduct a short-circuit current for the duration of the short circuit. In this case, a large amount of power is dissipated as heat in the second gate transistor T2, which very quickly leads to excessive heating and its destruction.

[0061] A control device 200 for controlling the second gate transistor T2 will be presented. Preferably, all control devices 200 are analogous or identical.

[0062] Control device 200

[0063] With reference to [Fig.4], a control device 200 is shown comprising a main circuit 200a and an auxiliary circuit 200b.

[0064] The control device 200 further includes a first voltage source connected between a first positive potential Vddl and a reference potential GND. The reference potential GND is connected to the source of the power transistor T2. The control device 200 includes a second voltage source connected between the reference potential GND and a supply potential Vss that is negative with respect to the reference potential GND. The control device 200 includes a third voltage source connected between a second positive potential Vdd2 and the supply potential Vss, the second positive potential Vdd2 being positive with respect to the supply potential Vss.

[0065] Main circuit 200a

[0066] Preferably, the main circuit 200a corresponds to a prior art main circuit, in particular, in the form of an integrated circuit adapted to detect desaturation of an IGBT-type power transistor. Such a main circuit The 200a boasts a low cost and numerous integrated functions. Its performance is proven and compatible with the aerospace sector.

[0067] The main circuit 200a includes an input for receiving a PWM control signal to determine a high output OUT_H and a low output OUT_L. These outputs are processed by the auxiliary circuit 200b to determine a gate drive (GDRV), specifically a gate voltage, to control the power transistor T2. The high output OUT_H and the low output OUT_L are switching controls. Such a main circuit 200a is said to be "split" because the two switching outputs OUT_H and OUT_L are separate, but it is understood that they could be combined into a single switching output. The main circuit 200a can thus include a common push-pull switching output, connected to the transistor gate by two resistors Rg(ON) and Rg(Off) and diodes (not shown) to differentiate between the on-state and off-state controls.

[0068] The main circuit 200a includes a fault output FLT which allows the detection of a short circuit to be reported by processing a nominal desaturation voltage DESAT supplied by the auxiliary circuit 200b.

[0069] In particular, the main circuit 200a includes a nominal comparator circuit 214 configured to compare the nominal desaturation voltage DESAT to a nominal desaturation threshold VDSth so as to perform nominal desaturation detection. The main circuit 200a includes an opening control circuit 213 for the power transistor T2. In other words, the opening control circuit 213 is configured to modify the switching commands OUT_H, OUT_L in the event of nominal detection, that is, when the nominal desaturation voltage DESAT exceeds the nominal desaturation threshold VDsth during a phase in which said power transistor T2 is turned off in order to trigger a short-circuit opening.

[0070] The main circuit 200a includes a current source circuit 212 activated when the power transistor T2 is switched ON to perform a desaturation detection inhibition function for the duration of a normal switching cycle. This, as is known, helps to limit errors during comparison.

[0071] The opening control circuit 213 is configured to slowly open the power transistor T2 without generating excessive overvoltage. This function is known to those skilled in the art by its English acronym STO for "Soft Tum Off". The main circuit 200a further includes an isolation barrier 204 to ensure the safety and proper electrical operation of an inverter arm. The main circuit 200a also allows for fault memory across the isolation barrier, reset, etc.

[0072] The main circuit 200a is formed by an integrated circuit for an IGBT power transistor whose functions are isolated and referenced to the reference potential GND and powered by the voltages Vddl, Vss. Such a main circuit 200a is known to those skilled in the art and will not be described in further detail.

[0073] Auxiliary circuit 200b

[0074] With reference to [Fig. 4], the auxiliary circuit 200b is configured to measure a drain voltage VDS, which corresponds to the potential difference between the Drain and the Source of said power transistor T2, in order to provide a nominal desaturation voltage DESAT to the main circuit 200a. In this example, the auxiliary circuit 200b has two resistors Rg(ON) and Rg(OFF), connected respectively to the high output OUT_H and the low output OUT_L, which are connected to the gate of the power transistor T2 in order to determine the gate drive GDRV.

[0075] The auxiliary circuit 200b preferably comprises discrete electronic components, which allows precise and customized adjustment of the behavior of the control device 200 to control a gate transistor of the MOSFET type.

[0076] With reference to [Fig. 5], the auxiliary circuit 200b is shown in close-up. The auxiliary circuit 200b comprises: • an auxiliary comparator circuit 224 configured to perform early detection of desaturation, • an inhibition circuit 221 configured to stabilize the input of the auxiliary comparison circuit 224, • a 222 protection circuit, • a 223 pinch circuit • a two-level short-circuit opening circuit 227 configured to modify the GDRV grid control in case of early detection, • an adaptation circuit 225 configured to increase the output control of the auxiliary comparator circuit 224 up to the nominal desaturation voltage DESAT, • a delay circuit 226 configured to delay the output command of the auxiliary comparator circuit 224 before emission of the nominal desaturation voltage DESAT.

[0077] Inhibition circuit 221

[0078] With reference to [Fig. 5], the auxiliary circuit 200b includes an inhibition circuit 221 configured to inhibit the detection of the auxiliary comparator circuit 224 during normal switching. This reduces the risk of false fault detection.

[0079] In this example, the inhibition circuit 221 includes an inhibition capacitor Cblnk referenced to the supply potential Vss. The inhibition circuit 221 further includes an inhibition resistor Rchg and an inhibition diode Ddischg, which are connected in parallel. The inhibition resistor Rchg and the inhibition diode Ddischg are both connected between the inhibition capacitor Cblnk and the high output OUT_H. During the ON turn-off command, the inhibition capacitor Cblnk charges slowly through the inhibition resistor Rchg and discharges rapidly during the OFF turn-off command through the inhibition diode Ddischg. In practice, the inhibition circuit 221 generates a slowly increasing drain voltage ramp VDST during the ON turn-off command and a rapidly decreasing ramp during the OFF turn-off command.

[0080] Pinch circuit 223

[0081] With further reference to [Fig. 5], the auxiliary circuit 200b includes a clamping circuit 223, also called a "clamp," which limits the voltage VDST below the detection threshold V* when transistor T2 is normally conducting and disconnects the drain of transistor T2 from the rest of the auxiliary circuit 200b to allow the voltage ramp VDst to exceed the detection threshold V* when transistor T2 is forced into desaturation at the beginning of a short circuit. The clamping circuit 223 includes a protection diode Ddst and a protection resistor Rdst connected in series between the potential VDST and the drain D of the gate transistor T2.

[0082] The pinch-off circuit 223 is configured to prevent short-circuit detection when transistor T2 is properly saturated and to allow short-circuit detection when transistor T2 is desaturated by a short circuit. In particular, the protection circuit 222 allows the voltage ramp VDst to be held at the desaturation voltage of the gate transistor T2 during the ON-turn-off control phase.

[0083] As will be shown later, it is thus possible to detect the presence of a short-circuit current by comparing the VDST potential to a predetermined threshold at the end or after the ON closing control phase of transistor T2 in order to detect if it is possibly desaturated.

[0084] Protection circuit 222

[0085] Preferably, the auxiliary circuit 200b includes a pinch protection circuit 222. The protection circuit 222 is mounted between the inhibition circuit 221 and the drain D of the gate transistor T2.

[0086] The protection circuit 222 comprises two clamping diodes DCLpi, DCLp2 connected in series. The cathode of the first clamping diode DClpi and the anode of the second clamping diode DCLp2 are connected to the inhibiting capacitor CMnk, as well as to The protection diode Ddst via the protection resistor RDST - The anode of the first pinch diode DClpi is connected to the supply potential Vss and the cathode of the second pinch diode DCLp2 to the first positive potential Vddl.

[0087] Auxiliary comparison circuit 224

[0088] With reference to [Fig. 5], the auxiliary circuit 200b includes an auxiliary comparator circuit 224 configured to compare the voltage VDst, i.e., a voltage representative of the drain voltage VDS, to an advanced desaturation threshold Vth. Such an advanced desaturation threshold V*, the value of which is lower than the nominal desaturation threshold VDsth of the main circuit 200a, enables rapid and early detection of desaturation by comparison to the main circuit 200a, thus enabling reactive protection of the SiC MOSFET power transistor T2, as will be shown later.

[0089] The auxiliary comparator circuit 224 includes a comparator, here an operational amplifier, which is configured to activate a two-level short-circuit opening circuit 227 for controlling the GRDV grid control, as will be shown later. The comparator is referenced to the supply potential Vss.

[0090] In this example, the auxiliary comparator circuit 224 includes a voltage divider to adapt the voltage VDST- In this example, the voltage divider includes two resistors Radapti, Radpt2-

[0091] The comparator circuit 224 enables the opening of a two-level short circuit 227 after a short delay (on the order of a few 10 ns) following the detection of an early desaturation. This delay is shorter compared to that of the nominal comparator circuit 214 of the main circuit 200a. Preferably, the comparator used is chosen to be very fast. For example, a comparator in a standard main circuit of the type "NCD57000 - Isolated High Current IGBT Gate Driver - ONSEMI - NCD57000 / D - June 2022 - Rev. 4" has a very slow response time (320 ns).

[0092] Adaptation circuit 225

[0093] Preferably, with reference to [Fig. 5], the auxiliary circuit 200b includes a matching circuit 225 configured to adapt the output voltage of the auxiliary comparator circuit 224 to the nominal desaturation input DES AT of the main circuit 200a. This is because the output voltage of the auxiliary comparator circuit 224 is a logic signal that is not compatible with the main circuit 200a, which is designed to detect higher desaturation voltages of an IGBT transistor. values. The adaptation circuit 225 thus makes it possible to compensate, in amplitude and in reference, for the action of the comparison circuit 224.

[0094] In this example, with reference to [Fig. 5], the 225 matching circuit is used to perform a voltage reference change by means of an open collector / drain logic output circuit, known by its English designation "open collector," powered by the first positive potential Vddl. The 225 matching circuit in this example comprises two transistors Q1, Q2, and two resistors Rbl, Rb2.

[0095] Delay circuit 226

[0096] Preferably, with reference to [Fig. 5], the auxiliary circuit 200b includes a delay circuit 226 configured to delay the output voltage of the auxiliary comparator circuit 224 before it is transmitted to the nominal desaturation input DES AT of the main circuit 200a. Indeed, since desaturation is detected in advance by the auxiliary circuit 200b, the output voltage of the auxiliary comparator circuit 224 is supplied in advance via the nominal desaturation input DES AT to the main circuit 200a. The matching circuit 225 thus compensates for the effect of the comparator circuit 224 by applying a delay.

[0097] In this example, the delay circuit 226 is referenced to the potential of the source S of transistor T2 and introduces a predetermined delay between the switching of the signal generated by the comparator circuit 224 when desaturation is detected and the nominal desaturation input DESAT of the main circuit 200a. The delay is fixed and advantageously set to correspond to the duration of an intermediate step during which the short-circuit current is controlled by the two-level opening circuit 227, as will be described later. Beyond the duration of this delay, the nominal desaturation input DESAT is activated, which allows the main circuit 200a to perform its functions as in the prior art, i.e., fault detection FLT, STO control, isolation, fault storage through the isolation barrier, reset, etc.From the perspective of the main circuit 200a, the early detection of the short circuit by the auxiliary circuit 200b is transparent.

[0098] In this example, with reference to [Fig. 5], the delay circuit 226 comprises two resistors RD1, RD2 and a capacitor CD. It is understood that the structure of the delay circuit 226 could be different.

[0099] Two-level short-circuit opening circuit 227

[0100] Preferably, with reference to [Fig. 5], the auxiliary circuit 200b includes a two-stage short-circuit opening circuit 227 configured to force an intermediate voltage plateau upon short-circuit opening command. The intermediate voltage plateau (also called the first plateau) is lower than the voltage A traditional GRDV gate (usually Vddl) is used to control the power transistor T2 in the ON state. This allows the transistor T2 to be used to control the short-circuit current and limit overvoltages when the short circuit is opened. In this example, the opening circuit of a two-level 227 short circuit includes a transistor Q2LT0, a diode D2Lto, and a resistor R2LT0. The intermediate voltage plateau is achieved by a voltage divider, formed by resistors R2Lto and Rg(On), which divides the ON-state control voltage (Vddl) of the power transistor T2.

[0101] The intermediate voltage step is lower than the on-state control voltage and greater than (or equal to) the threshold voltage of the power transistor T2. The intermediate voltage step is activated as soon as a short circuit is detected by the fast comparator module 224, thus enabling high responsiveness. When the output of the comparator circuit 224 switches from Vss to Vdd2, the Q2LTose transistor closes and the gate voltage GRDV is equal to the intermediate step voltage.

[0102] Advantages

[0103] Advantageously, the association of a classic main circuit 200a for an IGBT-type gate transistor with an auxiliary circuit 200b makes it possible to take advantage of the classic and robust functions of the main circuit 200a while benefiting from advanced functions via the auxiliary circuit 200b to allow compatibility with a SiC MOSFET-type gate transistor.

[0104] The auxiliary circuit 200b allows for reactive detection of desaturation, enabling rapid activation of the two-level short-circuit opening circuit 227. The short-circuit current is thus controlled due to the rapid detection coupled with the rapid two-level gate control of the power transistor T2, which is compatible with a SiC MOSFET. Advantageously, it is not necessary to add an additional mechanism to completely block the transistor with the cutoff control voltage Vss at the end of the intermediate step, as the internal mechanism of the main circuit 200a is used for this purpose.Indeed, the high output OUT_H and the low output OUT_L provided by the main 200a circuit are activated in STO mode by the early desaturation detection, adapted in amplitude to be compatible with the levels required by the main 200a circuit, with an adjustable delay allowing configuration of the intermediate plateau duration.

[0105] Advantageously, with reference to [Fig. 5], the inhibition circuit 221 is activated by the high output OUT_H, which simultaneously controls the ON switching of transistor T2 and the start of the voltage ramp Vdst achieved by charging the inhibition capacitor CBlnk through OUT_H via the resistor Rchg inhibition. Thus, there is no delay between the ON command of transistor T2 and the start of the voltage ramp. This minimizes the duration of the short-circuit opening phase during which the short-circuit current is not yet controlled by transistor T2.

[0106] Advantageously, with reference to [Fig. 5], the comparator circuit 224 is referenced to the supply potential Vss. As illustrated in [Fig. 6], this allows it to be protected with a DCpli protection diode without the latter being able to allow current to flow through the inhibition resistor Rchg or to cause overconsumption of the supply Vss with the inhibition diode Dd1Schg during the OFF control of the transistor because its anode is connected to Vss like the source of the transistor Q_L.

[0107] Advantageously, with reference to [Fig. 4], the supply voltage Vddl is identical to the GND potential, which allows only a single power supply to be used to generate the Vss and Vddl potentials, which are therefore identical. This is advantageously made possible when the inhibition circuit 221 and the comparator circuit 224 are referenced to the supply voltage Vss and when the gate of the SiC MOSFET power transistor is blocked with a negative voltage on the order of -5V (in this example - Vss) as illustrated in [Fig. 6]. The negative blocking of the gate transistor T2 is specific to the use of high-power SiC MOSFETs in a bridge-arm configuration.

[0108] This allows the gate-source capacitance of the gate transistor T2 to be taken advantage of to limit the rate of gate control changes during the transition from the intermediate voltage plateau to the threshold voltage, thanks to the two-level switching circuit 227, but also during STO switching. This limits the slope of the gate drive GDRV, which is advantageous and reduces the risk of faults.

[0109] Furthermore, with reference to [Fig. 7], referencing the first protection diode DCLpi to the supply voltage Vss is advantageous. The supply voltage Vss allows the DCLpi and Ddst diodes to be blocked during the passive rectification phase (MOSFET operation in the 3rd quadrant) of the OND inverter, thus preventing drain current from flowing through the Dclpi and Ddst diodes and potentially damaging them. Indeed, the forward voltage, denoted VF, of the body diode BD of the power transistor T2 is greater if it is a SiC MOSFET than if it is an IGBT. Thus, thanks to the reference to the supply voltage Vss according to the invention, the diodes Dclpi and Ddst remain blocked during the operating phases in the 3rd quadrant if the supply voltage Vss (negative) is chosen so as to respect the following formula:

[0110] [Math.l] vXDcLriWDofnl-V» > V^BO) [YES] 1 — variant: 228 buffer circuit

[0112] Advantageously, with reference to [Fig.8], the control device 200 is configured to control several parallel gated power transistors of the IGBT or MOSFET Sic type.

[0113] According to one aspect, with reference to [Fig. 8], the control device 200 includes a buffer circuit 228 for increasing the gate drive (GDRV) of the gate of the power transistor(s) to be driven. In this example, the buffer circuit 228 is of the push-pull type. The buffer circuit 228 comprises, in this example, two bipolar transistors QH, QL, and two resistors Ron, Roff. The buffer circuit 228 further includes a capacitor CSTo, which is connected between the base of QL and the collector of QL, itself connected to the reference potential Vss, in order to limit the decay rate of the gate drive (GDRV) at the opening of the current at the end of the intermediate step.

[0114] Preferably, and again with reference to [Fig. 8], the two-level gate control circuit 227 includes an additional capacitor C2lto connected between the cathode of diode D2Lto and the first positive voltage Vddl. The additional capacitor C2Lto limits the decay rate of the gate drive GDRV during the transition from the normal ON voltage to the intermediate step voltage, and thus limits the overvoltage at the onset of the short-circuit current. The additional capacitor C2Lto also limits the rate of change of the gate drive GDRV during an OFF gate control in the event of early detection.

[0115] Thus, the auxiliary circuit 200b retains the ability to limit the decay rate of the gate drive GDRV at the end of the intermediate step when using a buffer circuit 228, due to the additional capacitance CSto, which controls the switching at the end of the intermediate step. The capacitance Csto interacts with the internal RSTO resistor of the main circuit 200a, thereby limiting the rate of change of the current opening at the end of the second step. This advantageously allows the use of both the STO function of the main circuit 200a and the two-stage opening function of the auxiliary circuit 200b.

[0116] According to one aspect, since the RSTo resistance is only used for the slow opening at the end of the intermediate step when the short-circuit current has already decreased significantly, it is advantageous to choose the CSTo capacitance with a low value so as not to alter the normal switching speeds and therefore the losses during normal switching.

[0117] Preferably, the C2L to capacitance is connected between the first positive potential Vddl and the cathode diode DSTo- Thus it is biased at a constant voltage close to zero (the forward voltage of the DSTo diode). It therefore has high reliability and requires no load current when powered on.

[0118] Advantageously, diode D2LT0 and the capacitor rectify the OUT_H voltage during normal switching when transistor Q2lto is open. In normal operation, the high output OUT_H switches between the supply voltage Vss and the first positive voltage Vddl at a switching frequency that can vary from 1 kHz to 100 kHz depending on the application. Capacitor C2Lto is therefore kept discharged at each ON switching at the peak voltage of the high output OUT_H, i.e., at the first positive voltage Vddl, neglecting the voltage drop across diode D2LTO without generating losses in resistor Rg (0 N).

[0119] The CSTo capacitor, for its part, charges to the first positive voltage Vddl at the start of each ON switching operation, and discharges to the supply voltage Vss at the start of each OFF switching operation through the resistors Rg (oNjet Rg (off). Thus, fairly quickly at the start of an ON switching operation, both capacitors are at the same first positive voltage Vddl. When the two-level switching circuit 227 is activated by the ON switching of transistor Q2Lto, the two capacitors, in parallel, slow the voltage variation towards the intermediate voltage plateau with the following approximate formula:

[0120] [Math.2] v ~ v —{ùll— '2LTO~ ^dlR^R^)

[0121] With the following time constant:

[0122] [Math.3] _ RSTqR2LTO / \ t2LTO ~ Rsto+R2lto ' eSTO+v2LTO /

[0123] Variant s

[0124] In another variant, with reference to [Fig.9], since the supply voltage Vss is negative with respect to the potential of the source S, the protection circuit 222 intended to guard against overvoltages of the voltage VDST can be made by connecting the cathode of the first diode DClpi and the anode of the second diode DClp2 to the potential connecting the diode Ddst and the resistor RDst. In other words, with respect to the embodiment of [Fig.5], the resistor RDST is positioned upstream of the diodes DClpi and DClp2, that is, between the inhibition circuit 221 and the pinching circuit 222.

[0125] In another embodiment, with reference to [Fig. 12], the two-level opening circuit 227 is controlled by transistor Q2 of the matching circuit 225, in particular, by transistor Q2. This advantageously allows the use of less components by commonizing transistors Q2 and QLT0. It is trivial that the same arrangement works without using a C2LTO capacitor ([Fig. 10]).

[0126] In another embodiment, with reference to [Fig. 1 1], the capacitance C2LTO of the two-level switching circuit 227 is connected between the cathode of D2LTO and the supply voltage Vss. This advantageously allows the capacitance C2LTO to be charged before the activation of the two-level switching circuit 227 and thus avoids generating a current surge on the supply Vddl when the two-level switching circuit is activated.

[0127] In another embodiment, with reference to [Fig. 8], the two-level switching circuit 227 is controlled by the MOSFET-type transistor Q2lto. This advantageously limits the current that the comparator circuit MAI must supply.

[0128] In another embodiment, with reference to [Fig. 12], the two-level switching circuit 227 is controlled by the MOSFET-type transistor Q2. This advantageously limits the current that the comparator circuit MAI must supply.

Claims

Demands

1. An auxiliary circuit (200b) for a control device (200) of a power transistor (T2), the auxiliary circuit (200b) being configured to connect to the gate and drain of the gate transistor (T2), the auxiliary circuit (200b) being configured to receive from a main circuit (200a) of the control device (200) at least one switching command (OUT_H, OUT_L) and to output a gate command (GRDV) of the gate transistor (T2), the auxiliary circuit (200b) being configured to output a nominal desaturation voltage (DESAT), representative of a short circuit, to the main circuit (200a) so as to achieve nominal desaturation detection, the auxiliary circuit (200b) characterized in that it comprises: • at least one auxiliary comparator circuit (224) configured to compare a voltage representative of a drain voltage (VDS),to an advanced desaturation threshold (V*) so as to achieve early detection of desaturation, the auxiliary circuit (200b) being configured to modify the grid drive (GDRV) in case of early detection.

2. Auxiliary circuit (200b) according to claim 1, comprising a two-level opening circuit (227) configured to define an intermediate voltage step during an opening (OFF) command in case of early detection

3. Auxiliary circuit (200b) according to any one of claims 1 to 2, comprising an adaptation circuit (225) configured to increase the output control of the auxiliary comparator circuit (224) up to the nominal desaturation voltage (DESAT).

4. Auxiliary circuit (200b) according to any one of claims 1 to 3, comprising a delay circuit (226) configured to delay the output control of the auxiliary comparator circuit (224) before emission of the nominal desaturation voltage (DESAT).

5. Auxiliary circuit (200b) according to any one of claims 1 to 4, comprising an inhibition circuit (221) configured to generate a voltage stabilization delay representative of the drain voltage (VDS) for the comparator circuit (224).

6. Auxiliary circuit (200b) according to any one of claims 3 to 5, wherein the two-level opening circuit (227) is controlled by the output of the matching circuit (225).

7. Control device (200) of a gate transistor (T2) comprising a main circuit (200a) and an auxiliary circuit (200b) according to any one of claims 1 to 6, the auxiliary circuit (200b) being configured to receive from the main circuit (200a) of the control device (200) at least one switching command (OUT_H, OUT_L), the auxiliary circuit (200b) being configured to output a nominal desaturation voltage (DESAT) representative of a short circuit to the main circuit (200a) so as to achieve nominal desaturation detection.

8. Control device (200) according to claim 7, wherein the main circuit (200a) includes a comparator circuit (224) configured to compare the nominal desaturation voltage (DESAT) to a nominal desaturation threshold (VDSth) so as to achieve nominal desaturation detection, the main circuit (200a) being configured to modify the switching control (OUT_H, OUT_L) in the event of nominal detection.

9. Electrical converter (OND) comprising a plurality of gate transistors (T1-T6), at least one gate transistor (T2) being associated with a control device (200) according to any one of claims 7 to 8.

10. A method for controlling (200) a power transistor (T2) by an auxiliary circuit (200b) according to any one of claims 1 to 6, the method comprising steps of: • Comparing a voltage representative of a drain voltage (VDS), to an advanced desaturation threshold (V*) so as to achieve early detection of desaturation, and • Modifying the gate drive (GDRV) in case of early detection.

Images