Optoelectronic device and its manufacturing process

Abstract

Optoelectronic device and its manufacturing process The invention relates to a light-emitting diode with a three-dimensional structure (20) comprising: - a first part (21) having a first conductivity, - a second part (23) having a second conductivity, - an active region (22) configured to emit light radiation, interposed between the first part (21) and the second part (23), the diode also comprising: - A first electrical contact (31) configured to inject carriers into the first part (21), - A second electrical contact (32) configured to inject carriers into the second part (23). Advantageously, the diode comprises a slowing layer (33) interposed between the first contact (31) and the first part (21), configured to slow down the carriers from the first contact (31) before being injected into the first part (21).The invention also relates to a method for manufacturing such a 3D LED. Figure for the abstract: Fig.13.

Description

Title of the invention: Optoelectronic device and its manufacturing process. Technical field

[0001] The present invention relates to the field of optoelectronics. Its particularly advantageous application is the manufacture of optoelectronic devices having a three-dimensional (3D) structure, for example, light-emitting diodes based on nanowires. STATE OF THE ART

[0002] A light-emitting diode (LED) typically comprises carrier injection regions (electrons and holes) between which an active region is intercalated. The active region is where radiative recombinations of electron-hole pairs occur, resulting in light emission. This active region may include quantum wells, for example, InGaN-based wells.

[0003] LEDs exhibiting a three-dimensional structure (3D LEDs), typically in the form of nanowires or nanopyramids, can exhibit different architectures, particularly in the arrangement of the different constituent regions of the LED.

[0004] These different regions can be arranged in a stack along a longitudinal z-direction. Such an LED architecture is called axial. An axial 3D LED typically has, in a z-stacked configuration, a lower portion resting on a substrate, an active region resting on the lower portion, and an upper portion resting on the active region. The lower portion is generally used for electron injection and the upper portion for hole injection. The active region typically has quantum wells extending transversely to the longitudinal z-direction.

[0005] Alternatively, the different regions of the LED can be arranged radially around the longitudinal z-direction. Such an LED architecture is called radial or core-shell. A radial 3D LED typically has an inner part (the core) elongated along the z-axis and supported by a substrate, an active region surrounding the inner part, and an outer part (the shell) surrounding the active region. The inner part is generally used for electron injection and the outer part for hole injection. The active region typically has quantum wells extending parallel to the longitudinal z-direction.

[0006] To improve the radiative recombination rate, i.e. the external quantum efficiency (EQE) of LEDs, one solution is to confine the carriers within of the active region by adding one or more carrier blocking layers around the active region.

[0007] In particular, an electron blocking layer (EBL) can be added between the hole injection region and the active region. This EBL prevents electrons from the electron injection region from passing through the active region without recombining. The EBL is configured to block electrons and allow holes to pass through.

[0008] As a corollary, a hole-blocking layer (HBL) can be added between the electron injection region and the active region. This HBL prevents holes from the hole injection region from passing through the active region without recombining. The HBL is configured to block holes and allow electrons to pass through.

[0009] In practice, the introduction of these EBL and / or HBL layers leads to other problems, including the appearance of structural defects, the appearance of electrical resistances in series, and / or an undesirable slowing of the carriers that must pass through these layers. From a technological point of view, the formation of EBL and / or HBL layers in 3D LED architectures is not sufficiently controlled.

[0010] There is therefore a need to design a 3D LED architecture with improved EQE. The present invention aims to meet this need and / or at least partially overcome the drawbacks mentioned above.

[0011] In particular, one object of the present invention is to provide a 3D radial or axial light-emitting diode (LED) with an optimized EQE. Another object of the present invention is to provide a method for manufacturing such a light-emitting diode.

[0012] The other objects, features, and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. In particular, certain features and advantages of the device may be applied mutatis mutandis to the method, and vice versa. SUMMARY

[0013] To achieve the objectives mentioned above, a first aspect of the invention relates to a light-emitting diode comprising at least one three-dimensional (3D) structure including: - a first part exhibiting a first conductivity of a first type of carrier, - a second part exhibiting a second conductivity of a second type of carrier, - an active region configured to emit or receive light radiation of wavelength X, said active region being intercalated between the first part and the second part.

[0014] The diode further comprises: - a first electrically conductive contact configured to inject carriers of the first type into the first part, - a second electrically conductive contact configured to inject carriers of the second type into the second part.

[0015] Advantageously, the light-emitting diode includes a carrier-slowing layer interposed between the first contact and the first part of the 3D structure. This slowing layer is configured to slow down the first-type carriers from the first contact before they are injected into the first part.

[0016] During the development of the present invention, it was observed that the efficiency of LEDs is reduced by the very large difference in speed between electrons and holes. This difference limits the possibilities for recombination. Electrons can pass through the active region rapidly without encountering any holes. A means of slowing down the electrons was therefore developed.

[0017] Thus, the first part and the first contact are not directly in contact with each other. The retarding layer is an intermediate layer ensuring ohmic contact between the first contact and the first part of the 3D structure. The carriers of the first type are typically electrons. The first part of the 3D structure is typically based on n-GaN. The retarding layer can be based on a dilute magnetic semiconductor (DMS), for example, cobalt-doped ZnO.

[0018] The DMS material typically causes a modification of the trajectory of electrons transported towards the first GaN-n part. This alteration of the electron trajectory can result from an interaction between the electron spins and the spin-orbits of the ferromagnetic atoms of the DMS material.

[0019] The DMS material advantageously allows electrons to be injected into the first GaN-n portion along random or disordered trajectories. In particular, the electron trajectories have a component perpendicular to the electric field. The apparent mobility of the electrons is therefore reduced.

[0020] This lower electron mobility is maintained in the first part of the 3D structure up to the electron / hole recombination zones in the active region. This promotes radiative recombination between electrons and holes. The EQE efficiency of the LED is improved.

[0021] This electron slowing effect is all the more pronounced and persistent the closer the slowing layer is to the active region in the 3D structure according to the present invention. The benefit of the slowing is thus maximized. This is particularly advantageous for increasing the rate of radiative recombinations between electrons and holes in the active region of a 3D structure LED according to the present invention.

[0022] A second aspect of the invention relates to a method for manufacturing a light-emitting diode according to the first aspect. This method includes, in particular, the following steps: - to form the first part by epitaxy on a growth substrate, by localized growth through an opening in a masking layer placed on said growth substrate, - to form the active region on the first part by epitaxy, - to form the second part on the active region by epitaxy, then - to form the second contact on the second part, by depositing a layer of transparent conductive oxide, - deposit a planarization layer on the growth substrate, on and around at least one 3D structure protruding from the growth substrate, so as to obtain a flat surface above the at least one 3D structure, - adhere a manipulation substrate to said flat surface, - remove the growth substrate so as to expose a portion of the first part through the masking layer, - to form the retarding layer in contact with the exposed portion of the first part, - to form the first contact on the retarding layer. BRIEF DESCRIPTION OF THE FIGURES

[0023] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0024] [Fig.1] Fig.1 illustrates a radial 3D LED comprising an electron slowing layer, according to an embodiment of the present invention.

[0025] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig. 10] [Fig. 11] [Fig. 12] [Fig. 13] FIGURES 2 to 13 schematically illustrate different stages of a process for making a 3D LED with an electron slowing layer, according to an embodiment of the present invention.

[0026] [Fig. 14] The [Fig. 14] schematically illustrates a variant of the first contact of the 3D LED, according to an embodiment of the present invention.

[0027] The drawings are given by way of example and are not limiting of the invention. They are schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with the applications Practical considerations. In particular, the dimensions of the different layers and parts of the 3D LED are not necessarily representative of reality. DETAILED DESCRIPTION

[0028] Before beginning a detailed review of embodiments of the invention, it is recalled that the invention according to its first aspect includes in particular the following optional features which may be used in combination or alternatively:

[0029] According to one example, the carriers of the first type are electrons and the first conductivity is of type N, the carriers of the second type are holes and the second conductivity is of type P, and the slowing layer is an electron slowing layer based on a dilute magnetic semiconductor material.

[0030] According to one example, the dilute magnetic semiconductor material is based on ZnO doped with at least one element taken from among cobalt (Co), manganese (Mn), niobium (Nb), chromium (Cr), iron (Fe), nickel (Ni), neodymium (Nd).

[0031] In one example, the 3D LED further comprises a masking layer having a so-called lower face, a so-called upper face, and openings. In another example, the first part passes through the masking layer at the level of said openings, up to the retarding layer, the retarding layer being in contact with the lower face of the masking layer. This structural characteristic of the 3D LED is typically linked to a localized SAG (selected area growth) process for 3D structures. The presence of the masking layer is generally a residual element of the implementation of localized SAG growth. Such a masking layer is not present in so-called planar 2D LEDs. LEDs structured in a mesa pattern by etching planar layers, according to a technological approach designated by the term "top-down," do not have a masking layer.The masking layer is generally specific to the implementation of a SAG process for the formation of 3D structures, according to a technological approach known as "bottom-up". The presence of the masking layer is a means of differentiation between "bottom-up" 3D LEDs and "top-down" LEDs produced using planar technologies. In one scenario, the first part rests on the upper surface of the masking layer.

[0032] According to one example, the three-dimensional structure is obtained by localized growth through the openings in the masking layer. The openings in the masking layer can be regularly distributed in the form of a network. A portion at the base of the first part of the 3D structure is typically enclosed by the masking layer. The first part can also widen above the enclosed portion, and rest on the masking layer.

[0033] According to one example, the 3D structure has a so-called radial architecture such that: - the first part extends mainly along a z-direction, and has sides substantially parallel to the z-direction and a vertex substantially perpendicular to the z-direction, - the active region comprises a so-called radial part covering the flanks of the first part, and a so-called apex part covering the apex of the first part, - the second part covers the radial and apex parts of the active region.

[0034] According to one example, the radial part forms at least 80% of the active region.

[0035] According to one example, the retarding layer extends transversely to said radial part. According to another example, the first part and the retarding layer have a common interface which extends in a plane substantially perpendicular to the z direction.

[0036] According to an alternative example, the 3D structure has an axial architecture forming a stacking along a z-direction such that: - the first part has flanks that are substantially parallel to the z-direction and a vertex that is substantially perpendicular to the z-direction, - the active region covers only the apex of the first part, and has flanks substantially parallel to the z-direction directly above the flanks of the first part, and an apex substantially perpendicular to the z-direction, - the second part covers only the top of the active region, and has flanks substantially parallel to the z direction directly below the flanks of the active region.

[0037] According to one example, the flanks of the first part, the flanks of the active region, and the flanks of the second part extend substantially vertically from one another. According to one example, these flanks are oriented along crystallographic planes m {10-10}.

[0038] According to one example, the 3D LED further comprises a blocking layer for the first type of carrier interposed between the second part and the active region. A synergistic effect between the slowing of the carriers due to the slowing layer on the one hand, and the blocking of the carriers due to the blocking layer on the other, can thus be obtained.

[0039] According to one example, the first and second parts are based on GaN, and the active region includes InGaN-based quantum wells.

[0040] According to one example, the manipulation substrate is based on a material transparent at wavelength X. The manipulation substrate can thus be retained after the process. Alternatively, the manipulation substrate can be removed after the process, typically when the manipulation substrate is based on an opaque material such as silicon.

[0041] According to one example, the damping layer is structured in the form of a pad, and the first contact is formed on and around said pad, bearing against a lower face of the masking layer. In particular, when the LED comprises a plurality of 3D structures, each 3D structure can be contacted individually via the pads.

[0042] According to one example, the process further comprises, after formation of the retarding layer, a deposition of a dielectric layer on the retarding layer, then an etching of a via through the dielectric layer opening onto a face of the retarding layer, and the formation of the first contact through said via.

[0043] According to one example, the formation of the first and second parts, and the formation of the active region, are carried out by metal-organic vapor phase epitaxy (MOVPE). According to one example, the first part, the active region, and the second part are in an epitaxial relationship with each other.

[0044] According to one example, the at least one light-emitting diode comprises a plurality of light-emitting diodes, and the formation of the first parts is such that two adjacent first parts are separated from each other by a separation distance of less than 180 nm, preferably less than or equal to 100 nm. The first parts of the diodes are thus distributed on the substrate with a high surface density. This promotes axial growth of the parts overlying each first part, particularly the active regions.

[0045] Except where incompatibility exists, technical features described in detail for a given embodiment may be combined with technical features described in the context of other embodiments described by way of example and without limitation, so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0046] In the present invention, the device and method relate in particular to an architecture and the fabrication of 3D structured light-emitting diodes (LEDs). The invention can be implemented more broadly for various 3D structured optoelectronic devices. The invention can therefore also be implemented in the context of laser or photovoltaic devices. In this patent application, the terms "light-emitting diode," "LED," or simply "diode" are used synonymously. An "LED" can also refer to a "micro-LED".

[0047] In the present invention, the retarding layer is preferably based on a dilute magnetic semiconductor material. Such a material is typically obtained by introducing magnetic impurities into a semiconductor. The electronic and magnetic properties of this material are then strongly coupled.

[0048] Examples of dilute magnetic semiconductor material include II-VI semiconductors, for example ZnO, comprising a magnetic impurity, for example manganese or cobalt or nickel - as a substitute for zinc.

[0049] Unless explicitly stated otherwise, it is specified that, within the framework of the present invention, the relative disposition of a third layer intercalated between a first layer and a second layer does not necessarily mean that the layers are directly in contact with each other, but means that the third layer is either directly in contact with the first and second layers, or separated from them by at least one other layer or at least one other element.

[0050] Thus, the terms and phrases "to bear upon" and "to cover" or "to re-cover" do not necessarily mean "in contact with." Typically, the second part bears upon the active region either directly or indirectly, for example, via an intercalated electron-blocking layer. The active region can bear upon the first part either directly or indirectly, for example, via an intercalated quantum barrier.

[0051] The LEDs according to the present invention are preferably based on III-V materials, in particular GaN-based materials. The different parts and regions of the LED typically have a hexagonal crystallographic structure. According to the Miller-Bravais system, (hkil) denotes a plane of the hexagonal structure, {hkil} a family of planes of the hexagonal structure, and [hkil] a direction or vector of the hexagonal structure.

[0052] The external quantum efficiency EQE can be decomposed into three components: - The injection efficiency (IE) of carriers into the active region, - Internal quantum efficiency (IQE), which is the ratio between the number of radiative recombinations and the total number of recombinations, - Light extraction efficiency (LEE) which corresponds to the proportion of photons exiting the LED compared to the number of photons generated.

[0053] The term "3D structure" is understood in contrast to so-called planar or 2D structures, which have two dimensions in a plane much larger than the third dimension normal to the plane. Thus, the usual 3D structures used in the field of 3D LEDs can be in the form of a wire, nanowire, or microwire. Such a 3D structure has an elongated shape along the longitudinal direction. The The longitudinal dimension of the wire, along z in the figures, is greater, and preferably much greater, than the transverse dimensions of the wire, in the xy plane in the figures. The longitudinal dimension is, for example, at least twice, and preferably at least ten times, greater than the transverse dimensions, which are preferably between three and five times the transverse dimensions. In the example of pyramids, the ratios of longitudinal to transverse dimensions can be fixed. This typically depends on the geometries of the GaN crystals. For example, for a pyramid, the ratio of the longitudinal dimension to a transverse dimension is substantially less than or equal to 0.9. The 3D structures can also take the form of walls. In this case, only one transverse dimension of the wall is much smaller than the other dimensions, for example, three to five times smaller than the other dimensions. The 3D structures of this application preferably have substantially vertical walls or flanks. The vertical walls typically extend along crystallographic planes of the type m {10-10}.They can be involved in a so-called radial growth mechanism. The 3D structures of this application preferably have bases and vertices comprising substantially horizontal surfaces. These horizontal surfaces typically extend along crystallographic planes of type c(0001) or -c(000-1). They can be involved in a so-called axial growth mechanism. In one possibility, the 3D structures are in the form of pyramids or nanopyramids. In another possibility, the 3D structures are in the form of "elongated" pyramids or in the form of a "pencil," typically a nanowire surmounted by a pyramid.

[0054] "Axial growth" means anisotropic growth occurring essentially or exclusively along the longitudinal direction z. "Radial growth" means isotropic growth covering, in particular, surfaces parallel to the longitudinal direction z.

[0055] The steps of the process as claimed are understood in a broad sense and may possibly be carried out in several sub-steps.

[0056] A substrate, layer, or device "based" on a material M means a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example alloying elements, impurities, or dopant elements.

[0057] In the following, the following abbreviations relating to a material M may be used: - aM refers to the material M in amorphous form, according to the terminology usually used in the field of microelectronics for the prefix a-. - pM refers to the material M in polycrystalline form, according to the terminology usually used in the field of microelectronics for the prefix p-.

[0058] Similarly, the following abbreviations relating to a material M may be used: - Mi refers to intrinsic or unintentionally doped material M, according to the terminology usually used in the field of microelectronics for the suffix -i. - Mn refers to the M-type material doped with N, N+ or N++, according to the terminology usually used in the field of microelectronics for the suffix -n. - Mp refers to the M material doped with P, P+ or P++, according to the terminology usually used in the field of microelectronics for the suffix -p.

[0059] A coordinate system, preferably orthonormal, comprising the x, y, z axes is shown in some of the accompanying figures. This coordinate system can be applied by extension to the other accompanying figures. The z-axis is here parallel to the c-axis, that is to say to the crystallographic direction

[0001] .

[0060] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. The thickness is measured along a direction normal to the principal extension plane of the layer, and the height is measured perpendicular to the basal xy plane of the substrate. Thus, a layer typically has a thickness along z when it extends primarily along an xy plane, and an LED has a height along z. The relative terms "on," "under," and "below" refer to positions measured along the z direction.

[0061] Dimensional values ​​are understood to be within manufacturing and measurement tolerances. The terms "approximately," "about," and "in the order of" mean, when referring to a value, "within 10%" of that value or, when referring to an angular orientation, "within 10°" of that orientation. Thus, a direction substantially normal to a plane means a direction having an angle of 90+10° with respect to the plane.

[0062] A region, part or layer formed by axial growth typically has substantially the same diameter, taken in an xy plane, as the region, layer or part on which it rests.

[0063] When the LED is in the form of a nanowire or a microwire, a person skilled in the art can perfectly differentiate between an axial architecture and a radial architecture.

[0064] To determine the geometry of the 3D structures and the compositions of the different elements (wire, active region, slowing layer) of these 3D structures, one can perform Scanning Electron Microscopy (SEM) or Transmission Electron Microscopy (TEM) or Scanning Transmission Electron Microscopy (STEM).

[0065] TEM or STEM are particularly well suited to the observation and identification of quantum wells – whose thickness is generally on the order of a few nanometers – in the active region. Various techniques, listed below in a non-exhaustive manner, can be implemented: dark-field and bright-field imaging, weak beam imaging, and high-angle annular dark field (HAADF) diffraction.

[0066] The chemical compositions of the different elements can be determined using the well-known EDX or X-EDS method, an acronym for "energy dispersive x-ray spectroscopy" which means "energy dispersive analysis of X-ray photons".

[0067] This method is well suited for analyzing the composition of small optoelectronic devices such as 3D LEDs. It can be implemented on metallurgical sections within a Scanning Electron Microscope (SEM) or on thin sections within a Transmission Electron Microscope (TEM).

[0068] The techniques mentioned above make it possible in particular to determine whether an optoelectronic device with a 3D structure includes a slowing layer within the meaning of the present invention, and / or a masking layer indicative of an implementation of localized growth, as described in the present invention.

[0069] Figure 1 illustrates an LED comprising a 3D structure 20 in the form of a nanowire, according to an embodiment of the invention. The 3D structure 20 of the LED here exhibits a radial architecture, also called a core-shell architecture. Such a radial architecture may, in particular, comprise, from the inside to the outside of the nanowire along the y-direction: - A first part 21 having a diameter between 50 nm and 1.2 pm, typically on the order of 700 nm. This first part 21 forms the nucleus or core of the nanowire. It is preferably made of GaN-n. - An active region 22 with a thickness between 20 nm and 250 nm, typically on the order of 40 nm. The active region 22 covers the flanks and the top of the first part 21. It is preferably made of InGaN. The active region 22 preferably comprises InGaN-i quantum wells alternating with GaN-i quantum barriers. The quantum barriers may contain indium and / or aluminum. The quantum wells may have a thickness between 1 nm and 15 nm and the barriers Quantum particles can have a thickness between 3 nm and 20 nm. The active region 22 is configured to emit light radiation of X wavelength. - Optionally only, an electron blocking layer (EBL) with a thickness between 10 nm and 100 nm, typically 30 nm. The EBL layer is preferably made of AlGaN. Such an EBL layer is not shown in [Fig. 1]. - A second part 23 with a thickness between 20 nm and 500 nm, typically on the order of 100 nm. The second part 23 covers the sides and the top of the active region 22. It is preferably made of GaN-p.

[0070] The LED typically includes a masking layer 10 implemented during the nanowire growth process. This masking layer 10 may comprise several sublayers, for example, a silicon nitride-based layer 11 and an oxide-based layer 12. The masking layer 10 includes openings 110 configured to promote local nanowire growth. During growth, the first portion 21 typically passes through the masking layer 10 at an opening 110 and then extends essentially along the z-axis. According to a possibility not shown, the cross-sectional area in the xy plane of the first portion 21 increases sharply at the exit of the opening 110. The first portion 21 can thus bear against the upper face 101 of the masking layer 10.

[0071] The LED also includes an electrically conductive first contact 31, configured to inject charge carriers into the first portion 21. In the illustrated example, the charge carriers injected by the first contact 31 are electrons. The first contact 31 can be metallic, for example, aluminum-based. Advantageously, this first contact 31 can also be used as an optical reflector to reflect the light emitted by the active region 22 back to the top side of the nanowire (i.e., the "front" side of the device). This improves the LED's light extraction efficiency. The first contact 31 is typically electrically insulated by a dielectric layer 40, for example, silicon oxide-based, located on the underside 102 surrounding the first contact 31.

[0072] The LED also includes a second electrically conductive contact 32, configured to inject charge carriers into the second part 23. In the illustrated example, the charge carriers injected by the second contact 32 are holes. The second contact 32 is typically transparent to the wavelength of the light emitted by the active region 22. The second contact 32 is, for example, based on a transparent conducting oxide (TCO), for example, based on indium tin oxide (ITO). Alternatively, it can be based on gallium-doped zinc oxide (GZO) or aluminum oxide (AZO).

[0073] According to one principle of the present invention, the 3D LED advantageously comprises a slowing layer 33 interposed between the first contact 31 and the first part 21. This slowing layer 33 is typically based on a dilute magnetic semiconductor material, for example, cobalt-doped ZnO. The transparency of the ZnO is not altered by the cobalt doping. This material can also be easily deposited and structured to form the slowing layer 33 at the base of the nanowire.

[0074] During LED operation, electrons are slowed down by the slowing layer 33 before reaching the first part 21. In particular, spin interactions between the electrons and the ferromagnetic atoms of the slowing layer 33 modify the electron trajectories. The electrons follow randomly oriented trajectories when they enter the first part 21. The electrons are both slowed down and distributed along the entire height of the nanowire. This advantageously promotes carrier recombination in the vertical parts of the active region 22 and limits carrier recombination in the apex part of the active region 22. The radiative recombination rate is higher in the m planes than in the c planes.The EQE is improved, both by a slowing effect (the probability that a hole recombines with an electron increases) and by a distribution effect in the m planes (the probability that a recombination is radiative increases).

[0075] Figures 2 to 13 illustrate different stages of a process for making a 3D structure LED 20 comprising a slowing layer 33 as described above.

[0076] In the following, the 3D structures 20 are presented in the form of nanowires. The internal architecture of these 3D structures 20 is not detailed. It can be radial as illustrated and described previously. According to an alternative possibility, the 3D structures 20 have an "axial" internal architecture. In this case, in a manner known to those skilled in the art, the first part 21 based on GaN-n, the active region 22 based on InGaN-i, optionally the electron-blocking layer based on AlGaN, and the second part 23 based on GaN-p are stacked one on top of the other along z.

[0077] As illustrated in [Fig. 2], the nanowires 20 are first formed on a growth substrate 4L. The substrate 41 can be silicon-based and serve as a support. The substrate 41 typically carries one or more layers 13, 14 based on or made of III-V materials, typically based on metallic nitrides or carbides. A surface layer 13, called the nucleation layer, allows the nanowires 20 to grow. The nucleation layer 13 is preferably AlN-based. It can alternatively be based on other metallic nitrides, for example GaN or AlGaN. It can be formed on the silicon support 41 by epitaxy, preferably by Metal-organic vapor phase epitaxy (MOVPE) is advantageously a thickness of less than or equal to 200 nm, preferably less than or equal to 100 nm, for example around 50 nm.

[0078] A masking layer 10 is preferably formed on the nucleation layer 13. It may comprise several sublayers based on a dielectric material, for example, silicon nitride (Si3N4) and / or silicon oxide. The masking layer 10 may be formed by chemical vapor deposition (CVD). It partially masks the nucleation layer 13 and comprises openings 110, preferably circular, exposing areas of the nucleation layer 13. These openings 110 typically have a dimension, for example, a diameter, between 30 nm and 500 nm. The openings 110 may be regularly distributed within the masking layer 10, for example, in the form of an ordered array.

[0079] Such a masking layer 10 allows localized growth of a 3D structure 20 at each opening 110. In particular, during a preliminary growth step called germination, a GaN-based seed forms at the opening 110 and then fills said opening 110. The subsequent growth of the nanowire 20 then takes place from this seed, in a localized manner.

[0080] During the formation of the nanowires 20, the first parts 21, the active regions 22, and the second parts 23 are successively formed by epitaxy, preferably by metal-organic vapor-phase epitaxy (MOVPE). The nanowires 20 typically have a characteristic diameter or dimension in the xy plane between 20 nm and 1500 nm, preferably between 20 nm and 500 nm. The nanowires 20 preferably have a substantially horizontal apex, formed by a polar plane c (0001). They have substantially vertical sides, formed by non-polar planes m {10-10}.

[0081] As illustrated in [Fig. 3], after the formation of the nanowires 20 by localized growth through the masking layer 10, a dielectric layer 51 is conformally deposited on the nanowires 20 and on the exposed parts of the masking layer 10. The dielectric layer 51 is, for example, based on SiO2. It can be formed by plasma-enhanced chemical vapor deposition (PECVD).

[0082] As illustrated in [Fig. 4], the dielectric layer 51 is then partially etched so as to expose the tops and sides of the nanowires 20 over almost their entire height. The etching typically corresponds to isotropic wet etching. After etching, the dielectric layer 51 is retained on the masking layer 10. It preferably forms a ring at the base of the nanowires 20. It helps to reinforce the electrical insulation provided in part by the masking layer 10.

[0083] As illustrated in [Fig. 5], particularly when the nanowires 20 have a radial architecture, a layer based on a transparent electrically conductive material is continuously deposited on and between the nanowires 20. This continuous layer completely covers the exposed tips and sides of the nanowires 20. It forms the second electrical contact 32. It is typically based on a transparent conductive oxide, for example, ITO, AZO, or GZO. High-temperature annealing can be performed to obtain ohmic contact between the second electrical contact 32 and the second portion 23 of each nanowire 20.

[0084] As illustrated in [Fig.6], a layer of metal 34 is then deposited on the continuous layer forming the second electrical contact 32. This layer of metal 34 is preferably based on a metal that reflects the wavelengths of the light emitted by the active region 22. It is typically based on aluminum.

[0085] As illustrated in [Fig. 7], the metal layer 34 is then partially etched, so as to expose the underlying continuous layer over almost the entire height of the nanowires 20. The etching typically corresponds to isotropic wet etching. After etching, the metal layer 34 is retained on the second electrical contact 32 between the nanowires 20. It can form a ring at the base of the nanowires 20. It allows the formation of a power supply layer for the second electrical contact 32. It also allows the formation of a reflector for the light emitted by the active region 22. The light extraction efficiency of the LED is improved.

[0086] As illustrated in [Fig. 8], a passivation layer 61 can then be deposited on the exposed parts of the second electrical contact 32 and on the metal layer 34. This passivation layer 61 is, for example, based on an aluminum alloy, for example, based on Al₂O₃. It may be made of a dielectric material. It may be formed by plasma-assisted chemical vapor deposition (PECVD).

[0087] As illustrated in [Fig.9], the nanowires 20 protruding from the substrate 41 are then planarized by a planarization layer 62. This planarization layer 62 is typically deposited between and on the nanowires 20, and then polished by chemical-mechanical polishing (CMP) to obtain a flat surface 620 above the nanowires 20. This planarization layer 62 is typically electrically insulating and transparent.

[0088] A manipulation substrate 42, also called a "handle," is then bonded by molecular adhesion to the flat surface 620, on the "front face." This manipulation substrate 42 can be transparent, for example, glass-based. In this case, it can be retained in the final device after the manufacturing process. Alternatively, the manipulation substrate 42 is opaque, for example, based on silicon. In this case it is typically removed at the end of the manufacturing process, after the steps dedicated to the "back side" of the device have been completed.

[0089] As illustrated in [Fig. 10], after bonding the manipulation substrate 42, the growth substrate 41 is removed. This removal can be carried out in a known manner by a mechanical lapping step followed by a dry etching step.

[0090] As illustrated in [Fig. 11], the III-V material-based layers 13, 14 previously used for the germination / nucleation of the nanowires 20 are then removed from the back face, typically by one or more dry etchings. After the removal of layers 13, 14, the lower face 102 of the masking layer 10 is exposed. The portions 200 of nanowire 20 enclosed by the masking layer 10, initially corresponding to the seeds formed during the germination / nucleation steps, are also exposed after the removal of layers 13, 14.

[0091] As illustrated in [Fig. 12], a cobalt-doped ZnO layer is deposited on the lower face 102 and in contact with the portions 200, then etched to form the pads 33 corresponding to the LED's retarding layers. The deposition can advantageously be carried out by various conventional physical or chemical vapor deposition techniques, for example, by pulsed laser deposition (PLD) or atomic layer deposition (ALD). The cobalt-doped ZnO pads 33 are advantageously ferromagnetic at room temperature. They also form an ohmic contact with the portions 200 of the nanowires 20. Furthermore, they are transparent.

[0092] As illustrated in [Fig. 13], according to one possibility, the first electrical contacts 31 are formed directly on the cobalt-doped ZnO pads 33. They cover all the free surfaces of the pads 33 and bear against the lower face 102. The first electrical contacts 31 are preferably metallic, typically aluminum-based. They indirectly supply power to the nanowires 20 via the slowing pads 33. The first electrical contacts 31 also form reflectors on the rear face, in order to redirect the light emitted by the nanowires towards the front face of the device.

[0093] As illustrated in [Fig. 14], according to another possibility, before the formation of the first electrical contacts 31, a dielectric layer 11 is deposited on the rear face of the lower face 102 and on the cobalt-doped ZnO pads 33. Vias 310 are then formed within the dielectric layer 11, directly above the pads 33. The first electrical contacts 31 are then formed as pads on the dielectric layer 11, in contact with the previously filled vias 310. The filling of the vias 310 and the formation of the first electrical contacts 31 can be carried out simultaneously in a single step.

[0094] After the formation of the first electrical contacts 31, the nanowire-based LED 20 can be connected on the rear side, either directly to a power supply or to LED driver electronics, for example based on CMOS (Complementary Metal-Oxide-Semiconductor) technology. The manipulation substrate 42 can be removed, if necessary.

[0095] It appears that the 3D LED according to the invention is more efficient than a conventional 3D LED, particularly for a radial architecture. This is especially advantageous for LED technologies operating at medium or high voltage.

[0096] The invention is not limited to the embodiments described above. Those skilled in the art will readily adapt the embodiments described above to the case of a 3D LED with an axial architecture.

Claims

Demands

1. A light-emitting diode comprising at least one three-dimensional (3D) structure including: • a first part (21) having a first conductivity of a first type of carriers, • a second part (23) having a second conductivity of a second type of carriers, • an active region (22) configured to emit or receive light radiation of wavelength X, said active region (22) being interposed between the first part (21) and the second part (23), the diode further comprising: • A first electrically conductive contact (31) configured to inject carriers of the first type into the first part (21), • A second electrically conductive contact (32) configured to inject carriers of the second type into the second part (23),said light-emitting diode being characterized in that it comprises a carrier-slowing layer (33) interposed between the first contact (31) and the first part (21), said slowing layer (33) being configured to slow down the first-type carriers from the first contact (31) before being injected into the first part (21).

2. Diode according to the preceding claim, wherein the first type carriers are electrons and the first conductivity is of type N, the second type carriers are holes and the second conductivity is of type P, and the slowing layer (33) is an electron slowing layer based on a dilute magnetic semiconductor material.

3. Diode according to the preceding claim, wherein the dilute magnetic semiconductor material is ZnO-based doped with at least one element taken from cobalt (Co), manganese (Mn), niobium (Nb), chromium (Cr), iron (Fe), nickel (Ni), neodymium (Nd).

4. Diode according to any one of the preceding claims further comprising a masking layer (10) having a face (102) referred to as lower, a face (101) referred to as upper, and openings (110), in which the first part (21) passes through the masking layer (10) at the level of said openings (110), up to the slowing layer (33), the slowing layer (33) being in contact with the lower face (102) of the masking layer (10).

5. Diode according to the preceding claim in which the three-dimensional structure (20) is obtained by localized growth through the openings (110) of the masking layer (10).

6. Diode according to any one of the preceding claims wherein the 3D structure (20) has a so-called radial architecture such that: • the first part (21) extends mainly along a direction z, and has flanks substantially parallel to the direction z and a top substantially perpendicular to the direction z, • the active region (22) comprises a so-called radial part covering the flanks of the first part (21), and a so-called summit part covering the top of the first part (21), • the second part (23) covers the radial part and the summit part of the active region (22).

7. Diode according to the preceding claim wherein the radial portion forms at least 80% of the active region (22), and wherein the retarding layer (33) extends transversely to said radial portion.

8. Diode according to any one of the preceding claims wherein the first part (21) and the retarding layer (33) have a common interface which extends in a plane substantially perpendicular to the z direction.

9. Diode according to any one of claims 1 to 5 wherein the 3D structure (20) has an axial architecture forming a stack along a direction z such that: • the first part (21) has flanks substantially parallel to the direction z and a vertex substantially perpendicular to the direction z, • the active region (22) covers only the top of the first part (21), and has flanks substantially parallel to the direction z above the flanks of the first part (21), and a top substantially perpendicular to the direction z, • the second part (23) covers only the top of the active region (22), and has flanks substantially parallel to the direction z above the flanks of the active region (22).

10. Diode according to any one of the preceding claims further comprising a first-type carrier blocking layer intercalated between the second part (23) and the active region (22).

11. A method for making a light-emitting diode comprising at least one three-dimensional (3D) structure according to any one of the preceding claims, said method comprising: • forming the first part (21), • forming by epitaxy the active region (22) on the first part (21), • forming by epitaxy the second part (23) on the active region (22), • forming the second contact (32) on the second part (23), • forming the slowing layer (33) in contact with the first part (21), • forming the first contact (31) on the slowing layer (33).

12. A method of embodiment according to the preceding claim, said method comprising: • forming the first part (21) by epitaxy on a growth substrate (41), by localized growth through an opening (110) of a masking layer (10) disposed on said growth substrate (41), • forming by epitaxy the active region (22) on the first part (21), • form the second part (23) by epitaxy onto the active region (22), then • form the second contact (32) on the second part (23) by depositing a layer of transparent conductive oxide, • deposit a planarization layer (62) onto the growth substrate (41), on and around at least one 3D structure (20) protruding from the growth substrate (41), so as to obtain a flat surface (620) above the at least one 3D structure (20), • adhere a manipulation substrate (42) to said flat surface (620), • remove the growth substrate (41) so as to expose a portion (200) of the first part (21) through the masking layer (10), • form the retardation layer (33) in contact with the exposed portion (200) of the first part (21), • form the first contact (31) on the layer of slowing down (33).

13. Method according to the preceding claim, wherein the manipulation substrate (42) is based on a material transparent to the X emission wavelength of the light-emitting diode.

14. A method according to any one of claims 12 to 13, wherein the retarding layer (33) is structured in the form of a stud, and the first contact (31) is formed on and around said stud (33), bearing on a lower face (102) of the masking layer (10).

15. A method according to any one of claims 12 to 14 further comprising, after formation of the retarding layer (33), a deposition of a dielectric layer (11) on the retarding layer (33), then an etching of a via (310) through the dielectric layer (11) opening onto a face of the retarding layer (33), and the formation of the first contact (31) through said via (310).

16. A method according to any one of claims 11 to 15, wherein the formation of the first and second parts (21, 23), and the formation of the active region (22), are carried out by organometallic precursor vapor phase epitaxy (MOVPE).

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