Data transmission architecture and vehicle equipped with such an architecture

Abstract

The present invention relates to a data transmission architecture (100) within an avionics system (101) equipping a vehicle (102), the architecture (100) comprising a first fieldbus (A) and a first avionics bus (AVX A). According to the invention, the architecture (100) comprises at least two primary channels (A1, A2, A3, A4), each comprising: a primary field interface (IA1, IA2, IA3, IA4) enabling communication between each primary channel (A1, A2, A3, A4) via the first fieldbus (A), the field interfaces (IA1, IA2, IA3, IA4) being interconnected to the first fieldbus (A), and a first avionics interface (IAVX1, IAVX2, IAVX3, IAVX4) compatible with the first avionics bus (AVX A).The architecture (100) includes at least one primary computer (5) equipped with a second avionics interface (IAVX5) communicating via the first avionics bus (AVX A) with only one first avionics interface (IAVX1) among the first avionics interfaces (IAVX1, IAVX2, IAVX3, IAVX4). Abbreviated figure: Figure 2.

Description

Title of the invention: Data transmission architecture and vehicle equipped with such an architecture

[0001] The present invention relates to a data transmission architecture and a vehicle, such as an aircraft, equipped with this architecture enabling data transmission within an avionics system of the vehicle.

[0002] More particularly, the invention relates to the field of system architectures enabling critical data transmission between avionics equipment and a computer mounted on vehicles.

[0003] Generally, such architectures include one or more buses having at least one link to transmit this data between each avionics device and a computer configured to perform at least one critical function of the avionics system.

[0004] Document EP4236268 thus discloses a method and system for transferring data on an avionics bus. Such an avionics bus includes, in particular, a significant number of connections between each piece of avionics equipment and a computer.

[0005] Document US2007127521 describes an avionics bus interface particularly suited to communicate according to a communication protocol via an Ethernet bus or an avionics bus as designated by the English expression "Avionics Full Duplex" or its acronym "AFDX".

[0006] However, such a communication protocol is expensive and cumbersome to implement for all the electronic equipment of an aircraft, but also expensive and cumbersome to implement for a limited number of critical pieces of equipment of an aircraft.

[0007] Document WO0237791A1 describes a secure fieldbus system having an open communication channel as its transmission medium, which is also accessible to avionics equipment using other communication connections. These may include an existing standardized line connection, such as an Ethernet connection from an existing computer network, or a radio connection.

[0008] Finally, document US6003146A discloses a method for detecting errors in aircraft data transmitted periodically through an avionics data bus from a transmitting unit to a receiving unit.

[0009] The present invention aims to propose an alternative and innovative architecture that overcomes the limitations mentioned above. Furthermore, with a conventional architecture, each piece of equipment is connected to the computer. The The system can then have a significant mass. The invention aims to provide a safe and inexpensive system that overcomes this drawback.

[0010] Thus, the invention relates to a data transmission architecture within an avionics system equipping a vehicle, such as an aircraft, the architecture comprising a first fieldbus and a first avionics bus, the first avionics bus being distinct from the first fieldbus.

[0011] This architecture is remarkable in that it comprises: • at least two primary pathways, each comprising: • a primary field interface, with field interfaces being interconnected to the first fieldbus and • a first avionics interface compatible with the first avionics bus, • a primary processing unit generating uplink primary frames of avionics data, • at least one primary conversion unit converting each upstream primary avionics data frame generated by the primary processing unit into at least one upstream primary ground data frame intended for transmission via the first fieldbus to each of the other primary channels and, conversely, converting each upstream primary ground data frame received via the first fieldbus into an upstream primary avionics data frame, and • a primary memory storing a set of primary uplink avionics data frames comprising the primary uplink avionics data frames generated by each of the primary processing units of at least two primary channels.

[0012] Furthermore, the architecture includes at least one primary computer equipped with a second avionics interface communicating via the first avionics bus with only one first avionics interface among the first avionics interfaces of said at least two primary channels, the other first avionics interfaces being left free and disjoint from any avionics bus, said at least one primary computer receiving all the primary uplink avionics data frames via the first avionics bus and being configured to, from at least one of the primary uplink avionics data frames of the set of primary uplink avionics data frames, execute at least one critical function of the avionics system.

[0013] Furthermore, the expression "primary processing unit" may include, for example, at least one processor, at least one integrated circuit, at least one system programmable, at least one logic circuit; these examples do not limit the scope given to the expression "primary processing unit". The term processor can refer to a central processing unit known by the acronym CPU, a graphics processing unit (GPU), a digital signal processing unit (DSP), a microcontroller, etc.

[0014] Each primary channel then designates an entity independent of a computer or equipment. In addition to a primary processing unit and a primary memory, each primary channel may include an acquisition and control interface and a power supply.

[0015] In addition, the primary paths may or may not be synchronized with each other to perform the transmission of upstream primary field data frames through the first fieldbus.

[0016] Furthermore, the expression "upstream primary field data frame" refers to a basic structure of a set of data exchanged via the first fieldbus. This structure is enclosed by start and end bits. It is therefore generally composed of a header, the data to be transmitted on the first fieldbus, and a postamble. It is called "upstream" because it relates to data exchanged between the at least two primary channels and then sent back to the avionics computer, as opposed to downstream data sent by the avionics computer to the at least two primary channels.

[0017] Similarly, the expression "primary uplink avionics data frame" designates another basic structure of a set of data exchanged via the first avionics bus. This other structure is enclosed by start and end bits. It is therefore generally composed of a header, the data to be transmitted in the first avionics bus, and a postamble.

[0018] Cyclically, the primary conversion unit of each primary channel can prepare the upstream primary avionics data frames, and then store them in the primary memory at the level of an upstream primary avionics data frame transmission queue.

[0019] The primary conversion unit can then encapsulate each upstream primary avionics data frame into one or more upstream primary field data frames and transmit them by means of a primary field interface on the first field bus.

[0020] Upon receiving an upstream primary field data frame by the other primary channels, their primary conversion unit decapsulates the upstream primary avionics data frames it contains and stores them in their respective primary memory at the level of their upstream primary avionics data transmission queue.

[0021] Consequently, the first fieldbus allows the transmission between each primary channel of the upstream primary frames of avionics data originating from all the primary channels.

[0022] The first fieldbus thus allows all the primary upstream avionics data frames to be stored in each primary memory, with only one first avionics interface being connected to the first avionics bus to transmit all the primary upstream avionics data frames to the primary computer.

[0023] Such an architecture then comprises a single primary avionics bus for all primary channels. The architecture therefore has a minimal number of links or connections. Indeed, the architecture comprises a single link on the primary avionics bus connecting a first avionics interface and the second avionics interface of the primary computer receiving all uplink primary avionics data frames. Similarly, the primary computer has a single second avionics interface to receive all uplink primary avionics data frames.

[0024] Furthermore, such a single link on the first avionics bus can be made between any of the first avionics interfaces of said at least two primary channels and the second avionics interface of the primary computer.

[0025] The number of upstream primary field data frames required to transmit upstream primary avionics data frames on the fieldbus may depend on the type of fieldbus used.

[0026] Furthermore, the number of upstream primary frames of avionics data stored in each primary memory may depend on the implementation and occupancy budget of the first avionics bus and the first fieldbus.

[0027] Only one primary channel among several can transmit upstream primary avionics data frames by means of its first avionics interface as long as upstream primary avionics data frames are available in the transmit queue and as long as the latter is not empty.

[0028] Furthermore, and according to a first embodiment of the invention, the architecture may be of the simplex type and comprise only primary channels. In this case, the architecture comprises a single fieldbus formed by said first fieldbus and a single avionics bus formed by said first avionics bus.

[0029] According to a first example of simplex architecture, the architecture may include at least one piece of equipment comprising at least two primary paths among said at least two primary paths.

[0030] According to a first variant, the architecture may comprise a single piece of equipment having several field interfaces linked together via the first field bus and for example a single first avionics interface compatible with the first avionics bus.

[0031] The first fieldbus can in this case be totally part of the sole equipment of the architecture.

[0032] According to a second variant, the architecture may include several devices, each of which has several primary field interfaces connected to each other via the first fieldbus. However, only one of the devices may be connected to the first avionics bus by means of a first avionics interface.

[0033] According to a second example of simplex architecture, the architecture may include at least two pieces of equipment, each piece of equipment comprising only one of said at least two primary paths.

[0034] Consequently, when the said at least two primary paths comprise a first primary path and a second primary path, the architecture may comprise a first piece of equipment comprising exclusively the first primary path and a second piece of equipment comprising exclusively the second primary path.

[0035] In other words, the first piece of equipment may include a first primary field interface and the second piece of equipment may include a second primary field interface. These first and second field interfaces are then connected to each other via the first fieldbus.

[0036] Only the first piece of equipment can then be connected to the first avionics bus by means of a first avionics interface. The avionics interface corresponding to the second primary channel of the second piece of equipment is then left free.

[0037] The first fieldbus can in this case be both internal and external to the equipment of the architecture.

[0038] Advantageously, said at least one upstream primary field data frame received via the first field bus and / or all upstream primary avionics data frames can / may be transmitted by means of electrical or optical signals.

[0039] In other words, the first fieldbus and / or the first avionics bus may include at least one electrically conductive element, such as a copper wire, or at least one optical fiber to transmit said at least one upstream primary field data frame and / or all upstream primary avionics data frames.

[0040] In practice, the first fieldbus can be chosen from the group comprising a CAN bus, a CAN-FD bus, a LIN bus, a bus according to the EIA-485 standard, a bus according to the EIA-422 standard, a FlexRay bus, an Ethernet bus, an EtherCAT bus, a DeviceNet bus, a CANOpen bus, a CANOpen FD bus, a MODBUS bus, a PROFIBUS bus and a PROFINET bus.

[0041] Furthermore, said at least one upstream primary field data frame and / or all upstream primary avionics data frames received via the first avionics bus can / may be transmitted by means of electrical or optical signals.

[0042] In other words, the first fieldbus and / or the first avionics bus may include at least one electrically conductive element, such as a copper wire, or at least one optical fiber allowing the transmission of said at least one upstream primary field data frame and / or of all upstream primary avionics data frames between the first avionics interface and the second avionics interface.

[0043] Advantageously, the first avionics bus can be selected from the group comprising a bus according to STANAG 3910, a bus according to ARINC 429, a bus according to MIL-STD-1553B, a bus according to ARINC 629, a bus according to EIA-485, a bus according to EIA-422, an Ethernet bus and a bus according to ARINC-664.

[0044] According to a second embodiment of the invention, the architecture may be of the duplex type and may include, in addition to the first fieldbus, the first avionics bus and the primary channels: • a second field bus, the second field bus being separate from the first field bus and the first avionics bus, • a second avionics bus, the second avionics bus being separate from the first field bus, the first avionics bus and the second field bus, • at least two secondary pathways distinct from said at least two primary pathways, said at least two secondary pathways each comprising: • a secondary fieldbus interface, with secondary fieldbus interfaces interconnected to the second fieldbus, • a third avionics interface compatible with the second avionics bus, • a secondary processing unit generating uplink secondary frames of avionics data, • at least one secondary conversion unit converting each upstream avionics data secondary frame generated by the secondary processing unit into at least one upstream ground data secondary frame intended for transmission via the second fieldbus to each of the other secondary channels and, conversely, converting each upstream ground data secondary frame received via the second fieldbus into an upstream avionics data secondary frame, and • a secondary memory storing a set of upstream secondary avionics data frames comprising the upstream secondary avionics data frames generated by each of the secondary processing units of said at least two secondary channels.

[0045] Furthermore, the architecture may include at least one secondary computer equipped with a fourth avionics interface in communication via the second avionics bus with only one third avionics interface among the third avionics interfaces of said at least two secondary channels, the other third avionics interfaces being left free and separate from any avionics bus, said at least one secondary computer receiving all upstream secondary frames of avionics data via the second avionics bus and being configured to, from at least one of the upstream secondary frames of avionics data of the set of upstream secondary frames of avionics data, execute at least one critical function of the avionics system.

[0046] Furthermore, the expression "secondary processing unit" may include, for example, at least one processor, at least one integrated circuit, at least one programmable system, at least one logic circuit, these examples not limiting the scope given to the expression "secondary processing unit". The term processor may also refer to a central processing unit known by the acronym CPU, a graphics processing unit (GPU), a digital signal processing unit (DSP), a microcontroller, etc.

[0047] Furthermore, each secondary channel designates an entity independent of a computer or equipment. In addition to a secondary processing unit and secondary memory, each secondary channel may include an acquisition and control interface and a power supply.

[0048] In addition, the secondary paths may or may not be synchronized with each other to carry out the transmission of upstream secondary field data frames through the second fieldbus.

[0049] Furthermore, the expression "upstream secondary field data frame" refers to a basic structure of a set of data exchanged via the second fieldbus. This structure is enclosed by start and end bits. It is therefore generally composed of a header, the data to be transmitted in the second fieldbus, and a postamble.

[0050] Similarly, the expression "upstream secondary avionics data frame" designates another basic structure of a set of data exchanged via the second avionics bus. This other structure is enclosed by start and end bits. It is therefore generally composed of a header, the data that we want to transmit in the second avionics bus and a postamble.

[0051] Cyclically, the secondary conversion unit of each secondary channel can prepare the avionics data frames, then store them in secondary memory at the level of a queue for transmitting upstream secondary avionics data frames.

[0052] The secondary conversion unit can then encapsulate each upstream secondary frame of avionics data into one or more upstream secondary frames of field data and transmit them by means of a secondary field interface on the second field bus.

[0053] Upon receiving an upstream secondary frame of field data via the other secondary channels, their secondary conversion unit decapsulates the upstream secondary frames of avionics data that it contains and stores them in their respective secondary memory at the level of their upstream secondary avionics data transmission queue.

[0054] Consequently, the second fieldbus allows the transmission between each secondary channel of upstream secondary frames of avionics data from all secondary channels.

[0055] The second fieldbus thus makes it possible to store all the upstream secondary frames of avionics data in each secondary memory, with only one third avionics interface being connected to the second avionics bus to transmit all the upstream secondary frames of avionics data to the secondary computer.

[0056] Furthermore, the secondary computer may be separate from or identical to the primary computer. Similarly, at least one critical function of the avionics system implemented by the secondary computer may be separate from or identical to at least one critical function of the avionics system implemented by the primary computer.

[0057] Consequently, such an architecture comprises a single second avionics bus for all secondary channels. The architecture therefore has a minimal number of links or connections. The architecture thus includes a single connection on the second avionics bus linking a third avionics interface and the fourth avionics interface of the secondary computer receiving all uplink secondary avionics data frames. Similarly, the secondary computer has a single fourth avionics interface to receive all uplink secondary avionics data frames.

[0058] Furthermore, such a single link on the second avionics bus can be made between any of the third avionics interfaces of said at least two secondary channels and the fourth avionics interface of the secondary computer.

[0059] The number of secondary field data frames required to transmit avionics frames on the second fieldbus may depend on the type of fieldbus used.

[0060] Furthermore, the number of secondary frames of avionics data stored in each secondary memory may depend on the implementation and the occupancy budget of the second avionics bus and the second field bus.

[0061] Only one secondary channel among several can transmit secondary avionics data frames by means of its third avionics interface as long as secondary avionics data frames are available in the transmit queue and as long as the latter is not empty.

[0062] According to a first example of duplex architecture, the architecture may include at least one piece of equipment, each piece of equipment comprising each of said at least two primary paths and said at least two secondary paths.

[0063] According to a first alternative, a single piece of equipment may include several field interfaces connected to each other respectively via the first fieldbus and via the second fieldbus.

[0064] This single piece of equipment may also include a single first avionics interface connected to the first avionics bus and a single third avionics interface connected to the second avionics bus.

[0065] The first fieldbus and the second fieldbus can in this case be part of the single equipment of the architecture.

[0066] According to a second alternative, the architecture may comprise several devices, each device then comprising several primary field interfaces connected to each other via the first fieldbus and several secondary field interfaces connected to each other via the second fieldbus. One of the devices may comprise the first avionics interface compatible with the first avionics bus and another device may comprise the third avionics interface compatible with the second avionics bus.

[0067] The first and second fieldbuses can in this case be part of the at least two pieces of equipment in the architecture.

[0068] According to a second example of duplex architecture, the architecture may include at least two pieces of equipment, each piece of equipment comprising only one of said at least two primary paths and only one of said at least two secondary paths.

[0069] In other words, a first piece of equipment may include first primary and secondary field interfaces corresponding to each of the first primary and secondary paths. The second piece of equipment may include second primary and secondary field interfaces corresponding to each of the first primary and secondary paths. These first and second primary and secondary field interfaces are then respectively connected to each other via the first fieldbus and via the second fieldbus.

[0070] Only the first piece of equipment may then include the first avionics interface compatible with the first avionics bus. Similarly, in order to provide a minimal duplex architecture, only the second piece of equipment may include the third avionics interface compatible with the second avionics bus.

[0071] The first and second fieldbuses can in this case be external to the architecture equipment.

[0072] Advantageously, said at least one upstream secondary field data frame received via the second field bus and / or all upstream secondary avionics data frames can / may be transmitted by means of electrical or optical signals.

[0073] In other words, the second fieldbus and / or the second avionics bus may include at least one electrically conductive element, such as a copper wire, or at least one optical fiber to transmit said at least one uplink secondary field data frame and / or all uplink secondary avionics data frames.

[0074] In practice, the second fieldbus can be distinct from the first fieldbus and the first avionics bus, the second fieldbus being chosen from the group comprising a CAN bus, a CAN-FD bus, a LIN bus, a bus according to the EIA-485 standard, a bus according to the EIA-422 standard, a FlexRay bus, an Ethernet bus, an EtherCAT bus, a DeviceNet bus, a CANOpen bus, a CANOpen FD bus, a MODBUS bus, a PROFIBUS bus, and a PROFINET bus.

[0075] Furthermore, said at least one uplink secondary field data frame received via the second field bus and / or all of said secondary avionics data frames received via the second avionics bus may be transmitted by means of optical or optical signals.

[0076] In other words, the second fieldbus and / or the second avionics bus may include at least one electrically conductive element, such as a copper wire, or at least one optical fiber allowing the transmission of said at least one uplink secondary field data frame and / or all the secondary avionics data frames between the third avionics interface and the fourth avionics interface.

[0077] In addition, the second avionics bus can be selected from the group comprising a bus according to STANAG 3910, a bus according to ARINC 429, a bus according to MIL-STD-1553B, a bus according to ARINC 629, a bus according to EIA-485, a bus according to EIA-422, an Ethernet bus and a bus according to ARINC-664.

[0078] The invention also relates to a data transmission architecture within an avionics system equipping a vehicle, the architecture comprising a first fieldbus and a first avionics bus, the first avionics bus being distinct from the first fieldbus.

[0079] According to the invention, such an architecture is remarkable in that it comprises: • at least two primary pathways, each comprising: • a primary field interface, with field interfaces interconnected to the first fieldbus, • a first avionics interface compatible with the first avionics bus, • at least one primary computer equipped with a second avionics interface communicating via the first avionics bus with only one of the first avionics interfaces of said at least two primary channels, the other first avionics interfaces being left free and disconnected from any avionics bus, said at least one primary computer transmitting at least one downlink primary frame of avionics data via said first avionics bus,

[0080] said at least two primary channels, each comprising: • a primary processing unit using said at least one downlink primary frame of avionics data, • at least one primary conversion unit converting said at least one downsloping primary avionics data frame transmitted by said at least one primary computer into at least one downsloping primary field data frame intended for transmission via the first fieldbus to each of the other primary channels and, conversely, converting each downsloping primary field data frame received via the first fieldbus into a downsloping primary avionics data frame, and • a primary memory storing a set of the primary downlink frames of avionics data.

[0081] As before, such an architecture can be of different kinds and in particular be implemented according to the first embodiment by being of the simplex type, or according to the second embodiment by being of the duplex type.

[0082] Furthermore, the expression "primary downlink avionics data frame" designates a basic structure of a set of data exchanged via the first avionics bus from said at least one primary computer to the at least two primary channels.

[0083] Similarly, the expression "downstream primary field data frame" refers to another basic structure of a dataset exchanged via the first bus of terrain. This structure is called "downstream" because it relates to the data emitted by the avionics computer towards the at least two primary channels.

[0084] Furthermore, and according to a first embodiment of the invention, the architecture may be of the simplex type and comprise only primary channels. In this case, the architecture comprises a single fieldbus formed by said first fieldbus and a single avionics bus formed by said first avionics bus.

[0085] According to a second embodiment of the invention, the architecture may be of the duplex type and may include, in addition to the first fieldbus, the first avionics bus and the primary channels: • a second field bus, the second field bus being separate from the first field bus and the first avionics bus, • a second avionics bus, the second avionics bus being separate from the first field bus, the first avionics bus and the second field bus, • at least two secondary pathways distinct from the at least two primary pathways, each of the at least two secondary pathways comprising: • a secondary fieldbus interface, with secondary fieldbus interfaces interconnected to the second fieldbus, • a third avionics interface compatible with the second avionics bus, • at least one secondary computer equipped with a fourth avionics interface communicating via the second avionics bus with only one third avionics interface among the third avionics interfaces of at least two secondary channels, the other third avionics interfaces being left free and disconnected from any avionics bus, said at least one secondary computer transmitting at least one downlink secondary frame of avionics data via the second avionics bus,

[0086] said at least two secondary routes each comprising: • a secondary processing unit using said at least one downstream secondary frame of avionics data, • at least one secondary conversion unit converting said at least one downlink secondary frame of avionics data transmitted by said at least one secondary computer into at least one downlink secondary frame of field data intended for transmission via the second fieldbus to each of the other secondary channels and, conversely, converting each downlink secondary frame of field data received via the second fieldbus into a downlink secondary frame of avionics data, and • a secondary memory storing a set of descending secondary frames of avionics data.

[0087] Furthermore, such an architecture, regardless of the simplex or duplex embodiment, may, as before, comprise at least one piece of equipment, each piece of equipment comprising each of said at least two primary paths, or even also said at least two secondary paths.

[0088] Alternatively, the architecture may comprise at least two pieces of equipment, each piece of equipment comprising only one of said at least two primary channels, or even only one of said at least two secondary channels.

[0089] The present invention also relates to a vehicle, such as an aircraft, comprising a data transmission architecture within an avionics system equipping the vehicle, the architecture comprising a first fieldbus and a first avionics bus.

[0090] This vehicle is remarkable in that its architecture is as described above. Furthermore, the architecture can be of different types and, in particular, can be implemented according to the first embodiment, being of the simplex type, or according to the second embodiment, being of the duplex type.

[0091] The invention and its advantages will become apparent in more detail in the following description, with illustrative examples given by reference to the accompanying figures, which represent:

[0092] [Fig. 1], a diagram illustrating a prior art data transmission architecture,

[0093] [Fig.2], a representative diagram of a data transmission architecture according to the invention,

[0094] [Fig. 3], a flowchart illustrating in detail a data transmission architecture according to the invention,

[0095] [Fig. 4], a first example of an architecture according to a first embodiment of a data transmission architecture according to the invention,

[0096] [Fig. 5], a second example of an architecture according to a first embodiment of a data transmission architecture according to the invention,

[0097] [Fig. 6], a third example of an architecture according to a first embodiment of a data transmission architecture according to the invention,

[0098] [Fig.7], a first example of an architecture according to a second embodiment of a data transmission architecture according to the invention,

[0099] [Fig.8], a second example of an architecture according to a second embodiment of a data transmission architecture according to the invention,

[0100] [Fig.9], a third example of an architecture according to a second embodiment of a data transmission architecture according to the invention,

[0101] [Fig. 10], another flowchart illustrating in detail a first embodiment of another data transmission architecture according to the invention,

[0102] [Fig. 1 1], another flowchart illustrating in detail a second embodiment of another data transmission architecture according to the invention,

[0103] the [Fig.12], an example of architecture not covered by the invention, and

[0104] the [Fig.13], another example of architecture not covered by the invention.

[0105] Elements present in several separate figures are assigned one and the same reference.

[0106] Classically and as represented in [Fig.1], a prior art data transmission architecture may include several E1-E4 devices connected to a computer, such as a flight control computer FCC, an acronym for the English expression "Flight Control Computer".

[0107] In addition, each E1-E4 device can have two channels. The FFC computer is then connected to each of the E1-E4 devices by means of complex avionics buses having a plurality of connections and interfaces dedicated to these avionics buses.

[0108] As represented, the example architecture of [Fig.1] then presents eight avionics interfaces arranged on the four E1-E4 pieces of equipment and eight avionics interfaces on the FCC computer.

[0109] As shown in [Fig. 2], according to the invention, a data transmission architecture shared between four pieces of equipment in an avionics system and a computer can be simplified. Thus, architecture 1 comprises a first network including a first fieldbus A and a first avionics bus AVX A. Furthermore, architecture 1 can also include a second network including a second fieldbus B and a second avionics bus AVX B.

[0110] However, unlike the architecture of [Fig. 1], the number of connections between the avionics interfaces is minimal. The number of avionics interfaces at the computer level is also reduced to one per network.

[0111] Indeed, the first AVX A avionics bus has a single connection 6 linking only the equipment 1 with a primary computer 5 and the second AVX B avionics bus has a single connection 7 linking the equipment 4 with a secondary computer 105 which, as shown in [Fig.2], can be confused with the primary computer 5.

[0112] To achieve this, architecture 1 comprises four primary channels A1-A4, each comprising a primary field interface IA1-IA4 connected to the first fieldbus A.

[0113] Similarly, architecture 1 includes four secondary channels B1-B4 each having a secondary field interface IB1-IB4 connected to the second fieldbus B.

[0114] Consequently, the equipment 1-4 can communicate with each other via the fieldbuses A and B and only a first avionics interface IAVX1 compatible with the first avionics bus AVX A of the equipment 1 can be connected to the computer 5 by means of the connection 6. The other first avionics interfaces IAVX2-IAVX4 are left free.

[0115] To do this, the primary computer 5 is equipped with a second avionics interface IAVX5 in communication with the first avionics interface IAVX1 via the first avionics bus AVX A.

[0116] Similarly, only a third avionics interface IBVX4 compatible with the second avionics bus AVX B of equipment 4 can be connected to the secondary computer 105 by means of connection 7. The other third avionics interfaces IBVX1-IBVX3 are left free.

[0117] The secondary computer 105 is equipped with a fourth avionics interface IBVX5 in communication with the third avionics interface IBVX4 via the second avionics bus AVX B.

[0118] Furthermore, as shown in [Fig.3], each primary channel A1, A2 includes a primary processing unit 11,21 generating upstream primary frames of avionics data.

[0119] Each primary channel A1, A2 also includes at least one primary conversion unit 12, 22 which may include a first converter 14, 24 for converting each upstream primary avionics data frame generated by the primary processing unit 11, 21 into at least one upstream primary field data frame, intended to be transmitted, via the first field bus A, to all other primary channels A1, A2 among said at least two primary channels A1, A2.

[0120] Each primary conversion unit 12, 22 may also include a second converter 13, 23 configured to convert each upstream primary field data frame received via the first field bus A into an upstream primary avionics data frame.

[0121] Each primary channel Al, A2 also includes a primary memory 15, 25 storing a set of upstream primary avionics data frames comprising the upstream primary avionics data frames generated on the one hand by the primary processing unit 11,21 of the primary channel Al, A2 concerned and on the other hand by each of the primary processing units 12, 22 of said at least two primary channels Al, A2.

[0122] The set of primary uplink frames of avionics data can then be inserted into a queue which is then transmitted to each first IAVX1, IAVX2 avionics interface compatible with the first AVX A avionics bus

[0123] The primary computer 5 then receives all the upstream primary avionics data frames via the first AVX A avionics bus. The primary computer 5 can then, from at least one of said upstream primary avionics data frames from this set of upstream primary avionics data frames, execute at least one critical function of the avionics system.

[0124] Furthermore, each secondary channel Bl, B2 includes a secondary processing unit 111, 121 generating uplink secondary frames of avionics data.

[0125] Each secondary channel B1, B2 also includes at least one secondary conversion unit 112, 122 enabling the conversion of each upstream secondary avionics data frame generated by the secondary processing unit 111, 121 into at least one upstream secondary field data frame intended to be transmitted via the second field bus B to all other secondary channels Bl, B2 among said at least two secondary channels Bl, B2.

[0126] Each secondary conversion unit 112, 122 is configured to convert each upstream secondary field data frame received via the second field bus B into an upstream secondary avionics data frame.

[0127] Each secondary channel B1, B2 also includes a secondary memory 115, 125 storing a set of upstream secondary avionics data frames comprising the upstream secondary avionics data frames generated on the one hand by the secondary processing unit 111, 121 of the secondary channel Bl, B2 concerned and on the other hand by each of the secondary processing units 112, 122 of said at least two secondary channels Bl, B2.

[0128] The set of upstream secondary frames of avionics data can then be inserted into a queue which is then transmitted to each third avionics interface IBVX1, IBVX2 compatible with the second avionics bus AVX B.

[0129] Similarly, when the latter is present, the secondary computer 105, here represented in [Fig.3] as being separate from the primary computer 5, receives all the secondary uplink frames of avionics data via the second avionics bus AVX B and is configured to, from at least one of said secondary uplink frames of avionics data of the set of said secondary uplink frames of avionics data, execute at least one critical function of the avionics system.

[0130] As shown in Figures 4 to 6, according to a first embodiment of the invention, such an architecture may be of the simplex type. Alternatively, as shown in Figures 7 to 9, according to a second embodiment of the invention, such an architecture may be of the duplex type.

[0131] Thus, according to a first example of the first embodiment shown in [Fig.4], the architecture 200 can include a single piece of equipment 201 comprising said at least two primary channels A1, A2, A3.

[0132] Architecture 200 thus includes a single first avionics bus AVX A between the primary computer 5 (not shown) and the first avionics interface IAVX1 of equipment 201 to transmit all the upstream primary frames of avionics data from the different primary channels A1, A2, A3. The other first avionics interfaces IAVX2, IAVX3 of equipment 201 are thus left free.

[0133] According to a second example of the first embodiment shown in [Fig.5], the architecture 300 can include at least two pieces of equipment 301, 302, each piece of equipment 301, 302 comprising respectively the at least two primary channels A1, A2.

[0134] As in the previous example, the 300 architecture includes a single first avionics bus AVX A between the primary computer 5 (not shown) and the first avionics interface IAVX1 arranged on a first piece of equipment 301 to transmit all the uplink primary frames of avionics data from the various primary channels A1, A2. The other first avionics interface IAVX2 of the first piece of equipment 301 is thus left free. Similarly, the other first avionics interfaces IAVX1, IAVX2 of a second piece of equipment 302 are thus left free.

[0135] According to a third example of the first embodiment shown in [Fig.6], the said at least two primary paths Al, A2 comprising a first primary path Al and a second primary path A2, the architecture 400 can comprise a first piece of equipment 401 comprising exclusively the first primary path Al and a second piece of equipment 402 comprising exclusively the second primary path A2.

[0136] Similarly, the 400 architecture always includes a single first avionics bus AVX A between the primary computer 5 (not shown) and the first avionics interface IAVX1 arranged on a first piece of equipment 401 to transmit all the upstream primary frames of avionics data from the different primary channels A1, A2. The other first avionics interface IAVX2 of the second piece of equipment 402 is left free.

[0137] According to a first example of the second embodiment shown in [Fig.7], the architecture 500 can include a single piece of equipment 501 comprising at least two primary channels Al, A2, A3 or even at least two secondary channels Bl, B2, B3.

[0138] In this case, the 500 architecture includes a single second AVX B avionics bus between the secondary computer 105 (not shown) and the third IBVX3 avionics interface of the 501 equipment to transmit all upstream secondary frames of avionics data from the various secondary channels Bl, B2, B3.

[0139] The other third avionics interfaces IBVX1, IBVX2 of the 501 equipment are thus left free.

[0140] Furthermore, according to a second example of the second embodiment shown in [Fig.8], the architecture 600 can include at least two pieces of equipment 601, 602, each piece of equipment 601, 602 having at least two primary channels Al, A2 and at least two secondary channels Bl, B2.

[0141] As in the previous example, the 600 architecture still includes a single second avionics bus AVX B between the secondary computer 105 (not shown) and the third avionics interface IBVX2 arranged on a second piece of equipment 602 to transmit all the uplink secondary frames of avionics data from the various secondary channels B1, B2. The other third avionics interface IBVX1 of the second piece of equipment 602 is thus left free. Similarly, the other third avionics interfaces IBVX1, IBVX2 of a first piece of equipment 601 are thus left free.

[0142] Finally, according to a third example of the second embodiment shown in [Fig. 9], the at least two primary channels A1, A2 may comprise a first primary channel A1 and a second primary channel A2. Similarly, the at least two secondary channels B1, B2 may comprise a first secondary channel B1 and a second secondary channel B2. The architecture 700 may then comprise a first piece of equipment 701 comprising the first primary channel A1 and secondary channel B1, and a second piece of equipment 702 comprising the second primary channel A2 and secondary channel B2.

[0143] The second avionics bus AVX B always has a single connection between the secondary computer 105 and the third avionics interface IBVX2 arranged on a second piece of equipment 702 to transmit all the uplink secondary frames of avionics data from the different secondary channels Bl, B2. The other third avionics interface IBVX1 of the first piece of equipment 701 is left free.

[0144] Fig. 10 illustrates a first embodiment of a simplex type 800 architecture allowing data transmission within an avionics system 101 equipping a vehicle 102. Such an 800 architecture includes, as before, a first fieldbus A and a first avionics bus AVX A distinct from each other.

[0145] Such an 800 architecture comprises at least two primary channels A1, A2 each comprising a primary field interface IA1, IA2, these field interfaces IA1, IA2 being interconnected to the first field bus A.

[0146] The at least two primary channels A1, A2 also each include a first avionics interface IAVX1, IAVX2 compatible with the first avionics bus AVX A.

[0147] The 800 architecture also includes at least one primary computer 5 equipped with a second avionics interface IAVX5 in communication via the first avionics bus AVX A with only one first avionics interface IAVX1 among the first avionics interfaces IAVX1, IAVX2 of said at least two primary channels A1, A2, the other first avionics interfaces IAVX2 being left free and separate from any avionics bus, said at least one primary computer 5 transmitting at least one downlink primary frame of avionics data via the first avionics bus AVX A.

[0148] Therefore, the at least two primary channels A1, A2 also each include a primary processing unit 11, 21 using said at least one primary downlink avionics data frame.

[0149] The at least two primary channels A1, A2 also each include at least one primary conversion unit 12, 22 converting said at least one downsloping primary avionics data frame emitted by said at least one primary computer 5 into at least one downsloping primary terrain data frame intended to be transmitted via the first field bus A to each of the other primary channels A2 and, conversely, converting each downsloping primary terrain data frame received via the first field bus A into a downsloping primary avionics data frame.

[0150] Finally, the at least two primary channels A1, A2 include a primary memory 15, 25 storing a set of the primary downlink frames of avionics data.

[0151] In addition, such an architecture 800 can, as previously for the architectures 200 and 300 shown in figures 4 and 5, comprise at least one piece of equipment, each piece of equipment comprising each of said at least two primary channels A1, A2.

[0152] Alternatively, the 800 architecture can, as previously for the 400 architecture shown in [Fig.6], comprise at least two pieces of equipment, each piece of equipment comprising only one of said at least two primary channels A1, A2.

[0153] Like the 500, 600 and 700 architectures, and as represented in [Fig. 11] according to a second duplex-type embodiment, the 900 architecture can include at least two secondary channels Bl, B2 in addition to at least two primary channels Al, A2.

[0154] In addition to the first fieldbus A, the 900 architecture includes a second fieldbus B, the second fieldbus B being separate from the first fieldbus A and the first avionics bus AVX A.

[0155] Similarly, each secondary channel Bl, B2 has a secondary field interface IB1, IB2, the secondary field interfaces IB1, IB2 being interconnected to the second field bus B.

[0156] In addition, each secondary channel Bl, B2 includes a third avionics interface IBVX1, IBVX2 compatible with the second avionics bus AVX B.

[0157] The 900 architecture also includes a secondary computer 105, here represented as being separate from the primary computer 5, allowing the transmission of a set of downlink secondary frames of avionics data via the second avionics bus AVX B. Such a secondary computer 105 can also be confused with the primary computer 5.

[0158] The secondary computer 105 is thus equipped with a fourth avionics interface IBVX5 in communication via the second avionics bus AVX B with only a third avionics interface IBVX2 among the third avionics interfaces IBVX1, IBVX2 of the at least two secondary channels Bl, B2.

[0159] Thus, the other third avionics interface IBVX1 is left free and separate from any avionics bus.

[0160] In addition, each of the secondary channels Bl, B2 includes a secondary processing unit 111, 121 using at least one downside secondary frame of avionics data and a secondary conversion unit 112, 122 configured to convert a downside secondary frame of avionics data transmitted by the secondary computer 105 into at least one downside secondary frame of terrain data intended to be transmitted via the second field bus B to each of the other secondary channels Bl, B2 and, conversely, converting each downside secondary frame of terrain data received via the second field bus B into a downside secondary frame of avionics data.

[0161] Furthermore, each of the secondary channels Bl, B2 includes a secondary memory 115, 125 storing a set of several descending secondary frames of avionics data.

[0162] Furthermore, each secondary channel Bl, B2 includes a secondary processing unit 111, 121 generating uplink secondary frames of avionics data.

[0163] In addition, such an architecture 900 can, as previously for the architectures 500 and 600 shown in figures 7 and 8, comprise at least one piece of equipment, each piece of equipment comprising each of said at least two primary channels Al, A2 and said at least two secondary channels Bl, B2.

[0164] Alternatively, the 900 architecture can, as previously for the 700 architecture shown in [Fig.9], comprise at least two pieces of equipment, each piece of equipment comprising only one of said at least two primary channels Al, A2 and only one of said at least two secondary channels Bl, B2.

[0165] According to the unclaimed example in [Fig. 12], the 1000 architecture may include at least two primary channels Al, A2.

[0166] However, each primary channel A2 that is not connected to the first AVX avionics bus A may include a primary processing unit 1011 for preparing upstream primary frames of avionics data and a primary conversion unit 1013 converting said at least one upstream primary frame of avionics data prepared by the primary processing unit 1011 and then transmitted on the first fieldbus A.

[0167] One of the primary channels A1 which is connected to the first avionics bus AVX A may include a primary processing unit 1001 for preparing uplink primary avionics data frames and then storing the uplink primary avionics data frames in a primary memory 1002

[0168] The primary channel A1 then receives the upstream primary avionics data frames from the other primary channels A2 via the first fieldbus A and also stores these upstream primary avionics data frames from the other primary channels A2 in primary memory 1002.

[0169] The primary channel Al then includes a first avionics interface IAVX 1 allowing the upstream primary frames of avionics data contained in the primary memory 1002 to be transmitted on the first avionics bus AVX A.

[0170] According to the unclaimed example in [Fig. 13], the 1100 architecture may include at least two primary channels Al, A2.

[0171] However, each primary channel A2 that is not connected to the first AVX avionics bus A may include a primary conversion unit 1113 converting at least one downlink primary frame of avionics data received via the first fieldbus A.

[0172] Each primary channel A2 also includes a primary processing unit 1111 enabling the use of at least one downlink primary frame of avionics data retrieved via the fieldbus A.

[0173] One of the primary channels A1 which is connected to the first avionics bus AVX A may include an avionics interface for receiving avionics data frames and storing them in a primary memory 1102.

[0174] The primary channel Al also includes a primary processing unit 1101 allowing the use of the primary downlink avionics data frames intended for it.

[0175] The primary channel A1 includes a primary conversion unit 1113 converting said at least one primary downlink frame of avionics data stored in primary memory 1102 and then transmits them by means of a field interface on the first fieldbus A if they are not intended for it.

[0176] Naturally, the present invention is subject to numerous variations in its implementation. Although several embodiments have been described, it is understood Although it is not conceivable to exhaustively identify all possible methods, it is of course possible to replace a described means with an equivalent means without departing from the scope of the present invention as defined by the claims.

Claims

Demands

1. Data transmission architecture (100, 200, 300, 400, 500, 600, 700) within an avionics system (101) equipping a vehicle (102), said architecture (100, 200, 300, 400, 500, 600, 700) comprising a first fieldbus (A) and a first avionics bus (AVX A), said first avionics bus (AVX A) being distinct from said first fieldbus (A), characterized in that said architecture (100, 200, 300, 400, 500, 600, 700) comprises: at least two primary pathways (A1, A2, A3, A4) each comprising: • a primary field interface (IA1, IA2, IA3, IA4), said field interfaces (IA1, IA2, IA3, IA4) being interconnected to said first field bus (A) • a first avionics interface (IAVX1, IAVX2, IAVX3, IAVX4) compatible with said first avionics bus (AVX A), • a primary processing unit (11,21) generating uplink primary avionics data frames, • at least one primary conversion unit (12, 22) converting each upstream primary avionics data frame generated by said primary processing unit (11, 21) into at least one upstream primary field data frame intended for transmission via said first field bus (A) to each of the other primary channels (A1, A2, A3, A4) and, conversely, converting each upstream primary field data frame received via said first field bus (A) into an upstream primary avionics data frame, and • a primary memory (15, 25) storing a set of said primary uplink avionics data frames comprising said primary uplink avionics data frames generated by each of the processing units primary (12, 22) of said at least two primary channels (A1, A2, A3, A4), and, in that said architecture (100, 200, 300, 400, 500, 600, 700) comprises at least one primary computer (5) equipped with a second avionics interface (IAVX5) communicating via said first avionics bus (AVX A) with only one first avionics interface (IAVX1) among said first avionics interfaces (IAVX1, IAVX2, IAVX3, IAVX4) of said at least two primary channels (A1, A2, A3, A4), the other first avionics interfaces (IAVX1, IAVX2, IAVX3, IAVX4) being left free and disconnected from any avionics bus, said at least one primary computer (5) receiving said set of said upstream primary avionics data frames via said first avionics bus (AVX A) and being configured to, from at least one of said primary uplink avionics data frames of said set of said primary uplink avionics data frames,perform at least one critical function of said avionics system (101).

2. Architecture according to claim 1, characterized in that said architecture (200, 300) comprises at least one piece of equipment (201, 301, 302) comprising at least two primary paths (A1, A2) among said at least two primary paths (A1, A2).

3. Architecture according to claim 1, characterized in that said architecture (400) comprises at least two pieces of equipment (401, 402), each piece of equipment (401, 402) comprising only one of said at least two primary paths (A1, A2).

4. Architecture according to any one of claims 1 to 3, characterized in that said first fieldbus (A) is selected from the group comprising a CAN bus, a CAN-FD bus, a LIN bus, a bus according to EIA-485, a bus according to EIA-422, a FlexRay bus, an Ethernet bus, an EtherCAT bus, a DeviceNet bus, a CANOpen bus, a CANOpen FD bus, a MODBUS bus, a PROFIBUS bus and a PROFINET bus.

5. Architecture according to any one of claims 1 to 4,

6. characterized in that said first avionics bus (AVX A) is selected from the group comprising a bus conforming to STANAG 3910, a bus conforming to ARINC 429, a bus conforming to MIL-STD-1553B, a bus conforming to ARINC 629, a bus conforming to EIA-485, a bus conforming to EIA-422, an Ethernet bus and a bus conforming to ARINC-664. Architecture according to claim 1, characterized in that said architecture (500, 600, 700) comprises: a second field bus (B), said second field bus (B) being distinct from said first field bus (A) and said first avionics bus (AVX A), a second avionics bus (AVX B), said second avionics bus (AVX B) being distinct from said first field bus (A), said first avionics bus (AVX A) and said second field bus (B), at least two secondary pathways (B1, B2, B3, B4) distinct from said at least two primary pathways (A1, A2, A3, A4), said at least two secondary pathways (B1, B2, B3, B4) each comprising: • a secondary fieldbus interface (IB1, IB2, IB3, IB4), said secondary fieldbus interfaces (IB1, IB2, IB3, IB4) being interconnected to said second fieldbus (B), • a third avionics interface (IBVX1, IBVX2, IBVX3, IBVX4) compatible with said second avionics bus (AVX B), • a secondary processing unit (111, 121) generating uplink secondary frames of avionics data, • at least one secondary conversion unit (112, 122) converting each upstream secondary avionics data frame generated by said secondary processing unit (111, 121) into at least one upstream secondary field data frame intended for transmission via said second fieldbus (B) to each of the other secondary channels (B1, B2, B3, B4) and, conversely, converting each upstream secondary field data frame received via said second field bus (B) into an upstream secondary avionics data frame, • a secondary memory (115, 125) storing a set of said upstream secondary avionics data frames comprising said upstream secondary avionics data frames generated by each of the secondary processing units (111, 121) of said at least two secondary channels (B1, B2, B3, B4), and, in that said architecture (500, 600, 700) comprises at least one secondary computer (105) equipped with a fourth avionics interface (IBVX5) communicating via said second avionics bus (AVX B) with only a third avionics interface (IBVX2, IBVX4) among said third avionics interfaces (IBVX1, IBVX2, IBVX3, IBVX4) of said at least two secondary channels (B1, B2, B3, B4), the other third avionics interfaces (IBVX1, IBVX2, IBVX3,IBVX4) being left free and disconnected from any avionics bus, said at least one secondary computer (105) receiving said set of said upstream secondary avionics data frames via said second avionics bus (AVX B) and being configured to, from at least one of said upstream secondary avionics data frames of said set of said upstream secondary avionics data frames, execute at least one critical function of said avionics system (101).

7. Architecture according to claim 6, characterized in that said architecture (500, 600) comprises at least one piece of equipment (501, 601, 602), each piece of equipment (501, 601, 602) comprising each of said at least two primary paths (A1, A2) and of said at least two secondary paths (B1, B2).

8. Architecture according to claim 6, characterized in that said architecture (700) comprises at least two pieces of equipment (701, 702), each piece of equipment (701, 702) comprising only one of said at least two primary paths (A1, A2) and only one of said at least two secondary paths (B1, B2).

9. Architecture according to any one of claims 6 to 8, characterized in that said second fieldbus (B) is selected from the group comprising a CAN bus, a CAN-FD bus, a LIN bus, a bus conforming to EIA-485, a bus conforming to EIA-422, a FlexRay bus, an Ethernet bus, an EtherCAT bus, the DeviceNet bus, the CANOpen bus, the CANOpen FD bus, a MODBUS bus, a PROFIBUS bus, and a PROFINET bus.

10. Architecture according to any one of claims 6 to 9, characterized in that said second avionics bus (AVX B) is selected from the group comprising a bus according to ARINC 429, a bus according to MIL-STD-1553B, a bus according to ARINC 629, a bus according to EIA-485, a bus according to EIA-422, an Ethernet bus and a bus according to ARINC-664.

11. Data transmission architecture (800, 900) within an avionics system (101) equipping a vehicle (102), said architecture (800, 900) comprising a first fieldbus (A) and a first avionics bus (AVX A), said first avionics bus (AVX A) being distinct from said first fieldbus (A), characterized in that said architecture (800, 900) comprises: • at least two primary channels (A1, A2, A3, A4) each comprising: • a primary field interface (IA1, IA2, IA3, IA4), said field interfaces (IA1, IA2, IA3, IA4) being interconnected to said first fieldbus (A) • a first avionics interface (IAVX1, IAVX2, IAVX3, IAVX4) compatible with said first avionics bus (AVX A),• at least one primary computer (5) equipped with a second avionics interface (IAVX5) communicating via said first avionics bus (AVX A) with only one first avionics interface (IAVX1) among said first avionics interfaces (IAVX1, IAVX2, IAVX3, IAVX4) of said at least two primary channels (A1, A2, A3, A4), the other first avionics interfaces (IAVX1, IAVX2, IAVX3, IAVX4) being left free and disconnected from any avionics bus, said at least one primary computer (5) transmitting at least one frame,

12. primary downlink of avionics data via said first avionics bus (AVX A), said at least two primary pathways (A1, A2, A3, A4) each comprising: • a primary processing unit (11,21) using said at least one downlink primary frame of avionics data, • at least one primary conversion unit (12, 22) converting said at least one downsloping primary avionics data frame transmitted by said at least one primary computer (5) into at least one downsloping primary terrain data frame intended for transmission via said first fieldbus (A) to each of the other primary channels (A1, A2, A3, A4) and, conversely, converting each downsloping primary terrain data frame received via said first fieldbus (A) into a downsloping primary avionics data frame, and • a primary memory (15, 25) storing a set of said primary downlink frames of avionics data. Architecture according to claim 11, characterized in that said architecture (900) comprises: • a second field bus (B), said second field bus (B) being distinct from said first field bus (A) and said first avionics bus (AVX A), • a second avionics bus (AVX B), said second avionics bus (AVX B) being separate from said first field bus (A), said first avionics bus (AVX A) and said second field bus (B), • at least two secondary pathways (B1, B2, B3, B4) distinct from said at least two primary pathways (A1, A2, A3, A4), said at least two secondary pathways (B1, B2, B3, B4) each comprising: • a secondary field interface (IB1, IB2, IB3, IB4), said secondary field interfaces

13. (IB1, IB2, IB3, IB4) being interconnected to said second fieldbus (B), • a third avionics interface (IBVX1, IBVX2, IBVX3, IBVX4) compatible with said second avionics bus (AVX B), • at least one secondary computer (105) equipped with a fourth avionics interface (IBVX5) in communication via said second avionics bus (AVX B) with only one third avionics interface (IBVX2) among said third avionics interfaces (IBVX1, IBVX2) of said at least two secondary channels (B1, B2), the other third avionics interfaces (IBVX1) being left free and separate from any avionics bus, said at least one secondary computer (105) transmitting at least one downlink secondary frame of avionics data via said second avionics bus (AVX B), said at least two secondary pathways (B1, B2) each comprising: • a secondary processing unit (111, 121) using said at least one downlink secondary frame of avionics data, • at least one secondary conversion unit (112, 122) converting said at least one downlink secondary frame of avionics data transmitted by said at least one secondary computer (105) into at least one downlink secondary frame of terrain data intended for transmission via said second fieldbus (B) to each of the other secondary channels (B1, B2) and, conversely, converting each downlink secondary frame of terrain data received via said second fieldbus (B) into a downlink secondary frame of avionics data, and • a secondary memory (115, 125) storing a set of said descending secondary frames of avionics data. Vehicle (102) comprising a data transmission architecture (100, 200, 300, 400, 500, 600, 700, 800, 900) within a system avionics (101) equipping said vehicle (102), said architecture (100, 200, 300, 400, 500, 600, 700, 800, 900) comprising a first fieldbus (A) and a first avionics bus (AVX A), characterized in that said architecture (100, 200, 300, 400, 500, 600, 700, 800, 900) is according to any one of claims 1 to 12.

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