Method for manufacturing an electronic device

Abstract

Method for manufacturing an electronic device. This description relates to a method for manufacturing an electronic device comprising the following steps: - providing an assembly comprising a substrate (100) in which a first chip is formed and on which conductive pads (110) are positioned, a second chip being mounted on the substrate (100) and connected to the first chip, the second chip comprising through-vias (220), - forming conductive pillars (150) on the connection pads (110), an upper face (151) of the conductive pillars (150) being at the level of the second face of the second chip, - forming a passivation layer (420) on the substrate (100) and on the second chip, - forming conductive elements (160) on the conductive pillars (150) and on the vias (220), the periphery of the conductive elements (160) covering the passivation layer (420). Figure for the abstract: Fig. 2D

Description

Title of the invention: Method for manufacturing an electronic device. Technical field.

[0001] The present description relates generally to the field of electronic devices and, more particularly, to electronic devices comprising chips assembled by direct bonding onto substrates ('Die to Wafer') and their integration onto external devices by a technique of reverse transfer ('Flip-Chip'). Previous technique

[0002] In a heterogeneous D2W (die-to-wafer) integration, the active face of an upper chip is hybrid-bonded to the active face of a lower chip formed on a substrate. When it is necessary to have connections directly on both chips (for example, to have a power / distribution network without ohmic drop), through-hole vias (TSVs) are formed in the upper chip. Interconnecting elements (pillars or bumps) are then formed. Some of the interconnecting elements are formed on the TSVs and thus connected to the upper chip via the TSVs, and others are formed on connection pads positioned on the substrate and connected to the lower chip. The resulting electronic component can then be assembled to an external element, such as a printed circuit board.

[0003] However, even with very thin upper chips (typically between 20 and 30 µm thick), the height difference between the base of the various interconnecting elements is significant. The resulting interconnecting elements are therefore non-coplanar. Mounting the electronic component on a printed circuit board is then impossible and / or can cause thermomechanical stress within the final device, thus reducing its reliability over time. Summary of the invention

[0004] There is a need for electronic components comprising a substrate in which a chip is formed and on which another chip is mounted, for example by means of a die-to-wafer (D2W) bonding process, the electronic components being able to be easily assembled to external elements, typically printed circuits, by a flip chip technique in a durable and reliable manner.

[0005] This object is achieved by a process for manufacturing an electronic device comprising the following steps: a) provide an assembly comprising a substrate in which a first chip is formed and on which conductive areas are positioned, a second chip being mounted on the substrate, a first face of the second chip being arranged opposite the first chip and connected to the first chip, the second chip comprising through-vias emerging on a second face of the second chip, b) form conductive pillars on the connection pads, through openings in a resin, with one upper face of the conductive pillars being at the level of the second face of the second chip, c) remove the resin, d) form a passivation layer on the substrate and on the second chip, with openings formed in the passivation layer opposite the through-vias of the second chip and the top face of the conductive pillars formed in step b), e) form conductive elements on the conductive pillars and on the through vias, the perimeter of the conductive elements covering the passivation layer.

[0006] According to a particular embodiment, the conducting elements are electrically conductive pillars.

[0007] According to a particular embodiment, step e) is carried out through openings in an additional resin.

[0008] According to a particular embodiment, between step a) and step b), the process includes a step in which a primer layer is formed on the conductive surfaces.

[0009] According to a particular embodiment, the primer layer is deposited full plate and, between step c) and step d), the part of the primer layer not covered by the conductive pillars is removed.

[0010] According to a particular embodiment, the conductive elements are brazing balls.

[0011] According to a particular embodiment, between step d) and step e), a step in which electrically conductive layers, preferably of aluminium, are formed on the conductive pillars, the electrically conductive layers extending over the passivation layer.

[0012] According to a particular embodiment, the conductive pillars formed during step e) have a height less than the thickness of the passivation layer.

[0013] This object is reached by an electronic device comprising a substrate in which a first chip is formed and on which conductive areas are positioned, a second chip being mounted on the substrate, a first face of the second chip being arranged opposite the first chip and connected to the first chip, the second chip comprising through vias emerging on a second face of the second chip, conductive pillars being formed on the connection pads, one upper face of the conductive pillars being at the level of the second face of the second chip, a passivation layer being disposed on the substrate and on the second chip, openings being formed in the passivation layer opposite the vias of the second chip and the upper face of the conductive pillars, conductive elements being formed on the conductive pillars and on the vias, the periphery of the conductive elements covering the passivation layer, the upper faces of the conductive elements being at the same distance from the first face of the substrate.

[0014] According to a particular embodiment, the conductive elements are brazing balls or conductive pillars.

[0015] This object is also reached by an assembly comprising a device as defined above, and a printed circuit board comprising connection pads, the conductive elements being assembled on the connection pads.

[0016] This object is also achieved by a manufacturing process for an assembly as defined above, the process comprising a step in which the conductive elements are assembled on the connection pads of the printed circuit board, for example during a soldering step. Brief description of the drawings

[0017] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0018] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D] and [Fig.1E] schematically represent different stages of a first part of a manufacturing process for a D2W type electronic component according to a particular embodiment;

[0019] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] schematically represent different stages of a second part of a manufacturing process for a D2W type electronic component according to a particular embodiment;

[0020] [Fig.3A] and [Fig.3B] schematically represent different stages of a second part of a manufacturing process for a D2W type electronic component according to another particular embodiment;

[0021] [Fig.4] and [Fig.5] are schematic cross-sectional representations of different assemblies comprising an electronic component and a printed circuit board, according to different particular embodiments.

[0022] The different elements in the figures are not necessarily represented at a uniform scale to make them more legible. Description of the implementation methods

[0023] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0025] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures in a normal position of use.

[0027] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean at 10%, preferably at 5%.

[0028] We will now describe in detail the manufacturing process of an electronic component with reference to Figures 1 to 1E as well as Figures 2A to 2D and 3A and 3B.

[0029] The process comprises the following steps: a) providing an assembly comprising a substrate 100 in which a first chip is formed and on which conductive areas 110 are positioned, a second chip 200 being mounted on the substrate 100, a first face 201 of the second chip 200 being disposed opposite the first chip and connected to the first chip, the second chip 200 comprising vias 220 emerging on a second face 202 of the second chip 200 and forming conductive contacts ([Fig.1A]), b) forming conductive pillars 150 on the connection areas 110, through openings 411 in a resin 410, the upper face 151 of the pillars 150 being at the level of the second face 202 of the second chip 200 ([Fig.1C]), c) remove resin 410 ([Fig.1D]), d) form a passivation layer 420 on the substrate 100 and on the second chip 200, openings 421 being formed in the passivation layer 420 opposite the vias 220 of the second chip 200 and the conductive pillars 150 formed during step b) ([Fig. 1E]), e) form conductive elements 160, 190 on the conductive pillars 150 and on the connecting pads 220, thereby obtaining interconnections for the first chip and interconnections for the second chip 200 (Figures 2C, 3B).

[0030] Thus, the interconnections of the electronic components are formed in two stages: - initially, the lower part of the interconnects of the first chip is formed, the height of the lower part of the interconnects being equal to the thickness of the second chip 200, and - in a second step, the upper part of the interconnections of the first chip and the interconnections of the second chip 200 are formed simultaneously, the upper part of the interconnections of the first chip and the interconnections of the second chip 200 having the same height.

[0031] The resulting interconnections are coplanar. No thinning step is required during the process. With such a process, it is possible to achieve a very fine pitch (for example, on the order of 100 pm).

[0032] The assembly provided in step a) comprises the substrate 100 in which the first chip (or lower chip) and the second chip 200 (or upper chip) are formed ([Fig. 1A]). The first chip and the second chip are arranged face-to-face and connected to each other by connecting pads 120, 210.

[0033] The substrate 100 comprises a first face 101 and a second face 102. The connection pads 120 of the first chip are positioned on the first face of the substrate 100. Connection pads 110, connected to the first chip, are also positioned on the first face 101 of the substrate 100. The connection pads 110 are positioned around the first chip and are used to connect the first chip to an external element.

[0034] The second chip 200 comprises a first face 201 (front face) and a second face 202 (rear face).

[0035] The first face 201 of the second chip 200 is positioned opposite the first chip and connected to the first chip by means of the connection pads 210 positioned on the first face 201 of the second chip 200.

[0036] The second chip 200 includes through-silicon vias 220 (TSV). The vias 220 run from the first face 201 of the second chip 200 to the second face 202 of the chip 200. The through-silicon vias 220 lead to the second face 202 of the second chip 200 and form conductive contacts used to connect the second chip to an external element.

[0037] The second chip 200 has a thickness, for example, less than 60pm, for example less than or equal to 30pm (for example between 20 and 30pm) or less than 1Opm (for example between 6 and 1 Opm).

[0038] Preferably, a plurality of first chips is formed in the substrate 100 and a plurality of second chips 200 is assembled to the plurality of first chips. This is a die-to-wafer (D2W) assembly obtained by hybrid bonding. The pads 120 of the first chips are assembled to the pads 210 of the second chips 200. A low chip-to-chip impedance is obtained. The process includes a step, after step e), in which the substrate 100 is cut to separate the chips.

[0039] During step b), conductive pillars 150 are formed on the connection areas 110, through the openings 411 of a resin 410. The openings 411 of the resin layer 410 is positioned at the level of the conductive areas 110 of the substrate 100.

[0040] Step b) can be carried out according to the following sub-steps: - deposit a seed layer 310 to cover at least the conductive areas 110, the seed layer 310 preferably being deposited full plate ([Fig.1B]), - to form a layer of resin 410 having openings 411 ([Fig.lC]), - to form the pillars 150 through the openings 421 of the layer of resin 410 ([Fig.lD])..

[0041] The primer layer 310 allows the pillars 150 to grow by electrolytic deposition. It covers, for example, the substrate 100 and the second chip 200. It may or may not cover the sides of the second chip 200. The discontinuity of the primer layer is not problematic for implementing the process. The primer layer 310 is, for example, made of TiCu.

[0042] The resin is, for example, a photoresin. Conventional photolithography techniques can be used to form a resin layer with openings.

[0043] During this step, the second chip 200 is protected by the resin layer 410. At this stage, the interconnections of the second chip 200 have not started to be formed.

[0044] In step b), the height of the resin layer 410 is preferably greater than the desired height of the pillars 150. The upper part 151 of the pillars 150 is thus well defined. The upper part 151 of the pillars 150 is level with the second face 201 of the second chip 200. In other words, the height of the pillars 150 hi is identical to the thickness e of the chip.

[0045] Preferably, the surface area of ​​the openings 411 is less than the surface area of ​​the conductive areas 110. The pillars 150 thus formed have a surface area less than the surface area of ​​the conductive areas 110.

[0046] The pillars are, for example, made of copper.

[0047] During step c), the resin 410 is removed ([Fig.1D]).

[0048] The part of the primer layer 310 not covered by the pillars 150 is removed ([Fig.lE]).

[0049] In step d), a passivation layer 420 is formed on the substrate 100 and on the second chip 200 ([Fig.1E]). The passivation layer 420 includes openings 421 both opposite the connecting pads 220 of the second chip 200 and opposite the upper face 151 of the pillars 150 formed in step b).

[0050] The passivation layer 420 is, for example, a polymer layer, preferably made of polyimide (PI) or polybenzoxazole (PBO), or oxide.

[0051] The passivation layer 420 acts as a buffer layer and absorbs part of the mechanical stresses applied to the conductive pillars 150.

[0052] During step e), conductive elements 160, 190 are formed on the conductive pillars 150 and on the vias 220.

[0053] The conductive elements 160, 190 are formed simultaneously on the conductive pillars 150 and on the vias 220 with the same processing parameters.

[0054] The conducting elements 160, 190 are coplanar.

[0055] A part (the periphery) of the conductive elements 160, 190 covers the passivation layer 420, which improves resistance to mechanical stress.

[0056] Step e) can be carried out according to two embodiment variants.

[0057] According to a first embodiment shown, for example in Figures 2A to 2D, the conductive elements 160 are pillars. The pillars may have the same or a different diameter from the pillars 150 deposited in step b).

[0058] According to this alternative embodiment, step e) can be carried out according to the following substeps: - deposit an additional 320 primer layer, preferably full plate ([Fig.2A]), - to form a resin 430 having openings 431 opposite the pillars 150 and the connecting pads 220 ([Fig.2B]), - form the conductive elements 160 on the connecting pillars 150 and then deposit a layer of solder 170 ([Fig.2C]), - remove the resin 430 and the part of the additional primer layer 320 not covered by the conductive elements 160 ([Fig.2D]), - preferably, perform a reflow to melt the brazing layer 170 and form brazing pads 171 on the connecting elements 160.

[0059] The brazing layer 170 can be made of a tin-based alloy, for example an SnAgCu alloy.

[0060] The conductive elements 160 in the form of pillars are, for example, made of copper.

[0061] The additional primer layer 320 can be made of the same material or of a different material from the primer layer 310.

[0062] According to a second embodiment shown, for example, in Figures 3A and 3B, the conductive elements 190 are solder balls. They can be deposited through a mask or by an automatic ball placement tool.

[0063] According to this alternative embodiment, step e) can be carried out according to the following substeps: - deposit electrically conductive layers 180 at the openings 421 of the passivation layer 420, the electrically conductive layers 180 partially covering the passivation layer 420 and being in contact with the vias 220 and with the pillars 150 ([Fig.3A]), - form the conductive elements 190 on the electrically conductive layers 180 ([Fig.3B]).

[0064] The conductive layers 180 are made of metal or a metal alloy. They are, for example, made of aluminum ('AluCap') or NiAu.

[0065] The brazing balls 190 can be made of a tin-based alloy, for example an SnAgCu alloy.

[0066] As previously stated, after the implementation of steps a) to e), a cutting step, during which the chips are separated, can be carried out.

[0067] The resulting electronic device comprises ([Fig.2D] and [Fig.3B]): - a first interconnection group formed on substrate 100 and connected to the first connection ranges 110, and - a second interconnection group formed on the second face 202 of the second chip 200 and connected to the vias 220.

[0068] The first interconnection group allows the substrate chip 100 to be connected to the external element and the second interconnection group allows the second chip 200 to be connected to the external element.

[0069] The interconnections of the first interconnection group comprise a first part (or lower part) formed by the conductive pillar 150 on which rests a second part (or upper part) formed by the conductive element 160, 190. More particularly, the interconnections of the first interconnection group may comprise successively from the conductive areas 110: a starter layer 310, a conductive pillar 150, an additional starter layer 320, a conductive element 160, optionally a solder pad 171. The conductive element 160 may have an identical surface area to the surface area of ​​the additional starter layer 320. Alternatively, the interconnections of the first interconnection group may successively comprise from the conductive ranges 110: a starter layer 310, a conductive pillar 150, a conductive layer 180, a conductive element 190. The conductive element 190 may have a surface area greater than the surface area of ​​the conductive layer 180.

[0070] The interconnections of the second interconnection group include the conductive element 160, 190. More particularly, the interconnections of the second interconnection group include successively from the through vias 220: an additional starter layer 320 or a conductive layer 180 in contact with the through vias 220, a conductive element 160, 190, optionally a solder pad 171.

[0071] The periphery of the conductive elements 160, 190 of the first interconnection group and the second interconnection group covers the passivation layer 420, which reduces the mechanical stress on the interconnections.

[0072] The upper faces of the conductive elements 160, 190 are at the same distance from the first face 101 of the substrate 100, which facilitates the positioning and assembly of the interconnections with an external element 500, such as a printed circuit board (PCB) or a laminated substrate (Figures 4 and 5).

[0073] Since the interconnections are coplanar, the electronic device can be assembled by any conventional technique, for example by wire bonding or by bumping.

[0074] In particular, the method for assembling the device to an external element 500 includes a step in which the interconnections are aligned and brought into contact with the connection pads 510 of the device 500, and a step, for example, of brazing, in which the interconnections are fixed to the connection pads 510. The brazing ensures electrical and mechanical contact between the device and the external element. It can be carried out either by adding additional solder paste or with a brazing flux that deoxidizes and holds the device during the reflow step of the brazing beads 190 or the brazing pads 171 onto the connection pads 510.

[0075] The electronic device can be an analog memory device. It can be used in systems requiring a large number of inputs / outputs (I / O) (or LO (for Input / Output)). It is particularly interesting for the automotive field (especially for a Microcontroller Unit (or MCU)) or for personal (consumer) devices.

[0076] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to the person of the trade.

[0077] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for manufacturing an electronic device comprising the following steps: a) providing an assembly comprising a substrate (100) in which a first chip is formed and on which conductive areas (110) are positioned, a second chip (200) being mounted on the substrate (100), a first face (101) of the second chip (200) being disposed opposite the first chip and connected to the first chip, the second chip (200) comprising through-vias (220) emerging on a second face (201) of the second chip (200), b) forming conductive pillars (150) on the connection areas (110), through openings (411) in a resin (410), an upper face (151) of the conductive pillars (150) being at the level of the second face (202) of the second chip (200), c) removing the resin (410), d) forming a passivation layer (420) on the substrate (100) and on the second chip (200),openings (421) being formed in the passivation layer (420) opposite the through vias (220) of the second chip (200) and the upper face (151) of the conductive pillars (150) formed during step b), e) forming conductive elements (160, 190) on the conductive pillars (150) and on the through vias (220), the periphery of the conductive elements (160, 190) covering the passivation layer (420).

2. Method according to claim 1, wherein the conductive elements (160) are electrically conductive pillars.

3. A method according to the preceding claim, wherein step e) is carried out through openings (431) in an additional resin (430).

4. A method according to any one of claims 2 and 3, wherein between step a) and step b), the method comprises a step in which a primer layer (310) is formed on the conductive pads (110).

5. A method according to the preceding claim, wherein the primer layer (310) is deposited full plate and, between step c) and In step d), the portion of the primer layer (310) not covered by the conductive pillars (150) is removed.

6. Method according to claim 1, wherein the conductive elements (190) are brazing balls.

7. A method according to the preceding claim, comprising, between step d) and step e), a step in which electrically conductive layers (180), preferably of aluminium, are formed on the conductive pillars (150), the electrically conductive layers (180) extending over the passivation layer (420).

8. A method according to any one of the preceding claims, wherein the conductive pillars (150) formed in step e) have a height less than the thickness of the passivation layer (420).

9. A device comprising a substrate (100) in which a first chip (200) is formed and on which conductive areas (110) are positioned, a second chip (200) being mounted on the substrate (100), a first face (201) of the second chip (200) being disposed opposite the first chip and connected to the first chip, the second chip (200) comprising through vias (220) emerging on a second face (202) of the second chip (200), conductive pillars (150) being formed on the connection areas (110), an upper face (151) of the conductive pillars (150) being at the level of the second face (202) of the second chip (200), a passivation layer (420) being disposed on the substrate (100) and on the second chip (200), openings (421) being formed in the passivation layer (420) opposite the vias (220) of the second chip (200) and the upper face (151) of the conductive pillars (150), of the conductive elements (160,190) being formed on the conducting pillars (150) and on the vias (220), the perimeter of the conducting elements (160, 190) covering the passivation layer (420), the upper faces of the conducting elements (160, 190) being at the same distance from the first face (101) of the substrate (100).

10. Device according to the preceding claim, wherein the conductive elements (160, 190) are brazing balls (190) or conductive pillars (160).

11. Assembly comprising a device as defined in any one of claims 9 to 10, and a printed circuit board (500) comprising connection pads (510), the conductive elements (160, 190) being assembled on the connection pads (510).

12. A method for manufacturing an assembly as defined in claim 11, the method comprising a step in which the conductive elements (160, 190) are assembled on the connection pads (510) of the printed circuit board (500), for example during a soldering step.