Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a groove which extends into an epitaxial layer along a first surface, and the first surface is the surface of one side, away from a substrate, of the epitaxial layer; the source region is located in the epitaxial layer on the two sides of the groove, and the source region is a region formed by carrying out ion implantation on part of the first surface; the grid electrode is located in the groove, the grid electrode comprises a first part and a second part which are distributed in the first direction, in the second direction, the maximum width of the first part is smaller than that of the second part, the bottom of the grid electrode is an arc face protruding towards the substrate, the first direction is the direction, away from the substrate, of the groove, and the second direction is perpendicular to the extending direction of the groove. According to the invention, the problems of low reliability of the gate oxide layer and non-uniform electric field distribution caused by electric field concentration of the semiconductor device in the related technology are solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the increasing global demand for energy efficiency and electrification, wide-bandgap semiconductor devices, represented by silicon carbide (SiC), have become a research hotspot and core industry in the field of power electronics. Compared to traditional silicon (Si) devices, SiC MOSFETs exhibit unparalleled advantages in high-voltage, high-temperature, and high-frequency applications due to their superior characteristics such as high breakdown electric field, high saturated electron drift velocity, and high thermal conductivity. Among them, the trench gate structure has great development potential because it can eliminate the resistance of the JFET region, thereby achieving lower on-resistance within a given chip area.

[0003] In traditional rectangular or trapezoidal trench structures, the corners and bottom of the trench are areas where electric fields tend to concentrate. When the device is off, the electric field strength in these areas may exceed the critical breakdown field strength of the SiC / SiO2 interface, leading to premature degradation or even breakdown of the gate oxide layer. This is the primary factor limiting the long-term reliability of SiC MOSFETs. Early trench gate devices suffered breakdown voltages far below theoretical values ​​due to gate oxide layer cracking. Optimizing the trench structure to disperse the electric field is a core challenge in improving device durability. Furthermore, the reliability of the gate oxide layer is limited by the dielectric constant. Currently, mainstream devices still use SiO2 as the gate dielectric. To achieve high gate capacitance, the oxide layer thickness needs to be reduced to an extremely thin level. However, an excessively thin SiO2 layer is prone to interface states, leakage current, and thermal breakdown.

[0004] Therefore, conventional trench semiconductor devices suffer from low gate oxide reliability and uneven electric field distribution due to concentrated electric fields. In particular, existing technologies cannot actively adjust the electric field distribution according to operating conditions, and under load conditions, sudden electric field changes and localized breakdown risks may still occur. Therefore, there is an urgent need for a semiconductor device and its fabrication method that can overcome these problems. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method to solve the problems of low reliability of the gate oxide layer and uneven electric field distribution caused by electric field concentration in related technologies.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising:

[0007] The substrate includes a stacked substrate and an epitaxial layer;

[0008] The trench extends along a first surface into the interior of the epitaxial layer, the first surface being the side of the epitaxial layer facing away from the substrate;

[0009] The source region is located in the epitaxial layers on both sides of the trench, and the source region is the area formed by ion implantation of a portion of the first surface;

[0010] A gate is located within the trench. The gate includes a first portion and a second portion distributed along a first direction. Along a second direction, the maximum width of the first portion is less than the maximum width of the second portion. The bottom of the gate is an arc surface protruding toward the substrate. The first direction is the direction in which the trench is away from the substrate, and the second direction is perpendicular to the extension direction of the trench.

[0011] Optionally, the gate and the trench have corresponding cross-sectional shapes in the first direction and the second direction, the cross-section being a trapezoidal structure, wherein the bottom edge of the trapezoidal structure near the substrate along the second direction is smaller than the bottom edge away from the substrate, and the bottom of the cross-section is arc-shaped.

[0012] Optionally, the semiconductor device further includes a composite gate oxide layer located between the inner surface of the trench and the gate, the composite gate oxide layer comprising an oxide layer and a high-k dielectric layer, the oxide layer contacting the inner surface of the trench, the high-k dielectric layer contacting the gate, and the dielectric constant of the high-k dielectric layer being greater than the dielectric constant of the oxide layer; or the semiconductor device further includes a ternary composite layer located between the inner surface of the trench and the gate, the ternary composite layer comprising, sequentially along the first direction, a buffer layer, a high-k dielectric layer, and a surface passivation layer, the dielectric constant of the high-k dielectric layer being greater than the dielectric constants of the buffer layer and the surface passivation layer; the oxide layer The high-k dielectric layer has three cross-sections in the first direction and the second direction, respectively. The oxide layer includes a first oxide portion, a second oxide portion, and a third oxide portion connected in sequence. The high-k dielectric layer includes a first high-k dielectric portion, a second high-k dielectric portion, and a third high-k dielectric portion connected in sequence. The first oxide portion, the first oxide portion, the first high-k dielectric portion, and the third high-k dielectric portion are located between the inner wall of the trench and the gate. The second oxide portion and the second high-k dielectric portion are located between the bottom surface of the trench and the gate. The second oxide portion and the second high-k dielectric portion have arc surfaces protruding toward the substrate.

[0013] Optionally, the source region includes a first implantation region and a second, third, and fourth implantation regions sequentially distributed in the first direction. The first and fourth implantation regions are regions formed by ion implantation of a portion of the first surface, and the second and third implantation regions are regions formed by ion implantation of a portion of the epitaxial layer. The second, third, and fourth implantation regions are located between the first implantation region and the trench. The second and third implantation regions are in contact with each other, and the third and fourth implantation regions are in contact with each other. The second and fourth implantation regions have the same doping type, and the second and third implantation regions have opposite doping types.

[0014] Optionally, the doping concentration of the epitaxial layer increases in a gradient along the first direction.

[0015] Optionally, the depth of the second injection region is less than the depth of the first injection region.

[0016] Optionally, the semiconductor device further includes a source electrode located on the side of the epitaxial layer away from the substrate and in contact with the source region; an insulating layer and an ohmic contact metal layer located between the epitaxial layer and the source electrode, wherein the insulating layer isolates the source electrode from the gate electrode, and the ohmic contact metal layer contacts the source electrode and the source region respectively; and a drain electrode located on the side of the substrate away from the epitaxial layer.

[0017] According to one aspect of this application, a method for fabricating a semiconductor device is provided, the method comprising the following steps:

[0018] A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer;

[0019] A trench extending along a first surface into the source region and the source region are formed in the epitaxial layer, wherein the first surface is the side surface of the epitaxial layer facing away from the substrate, and the source region is a region formed by ion implantation of a portion of the first surface;

[0020] A gate is formed in the trench, the gate including a first portion and a second portion distributed along a first direction, the maximum width of the first portion being less than the maximum width of the second portion along a second direction, the bottom of the gate being an arc surface protruding toward the substrate, the first direction being the direction in which the trench is away from the substrate, and the second direction being perpendicular to the extension direction of the trench.

[0021] Optionally, the step of forming the source region in the epitaxial layer includes: ion implantation of a portion of the first surface to form a first implantation region; ion implantation of a portion of the epitaxial layer to form a second implantation region located between the first implantation region and the trench, wherein the two sides of the second implantation region are in contact with the first implantation region and the trench, respectively; ion implantation of a portion of the epitaxial layer to form a third implantation region located between the first implantation region and the trench, wherein the two sides of the third implantation region are in contact with the first implantation region and the trench, respectively; and ion implantation of another portion of the first surface to form a fourth implantation region located between the first implantation region and the trench, wherein the two sides of the fourth implantation region are in contact with the first implantation region and the trench, respectively; wherein the second implantation region and the third implantation region are in contact, the third implantation region and the fourth implantation region are in contact, and the second implantation region and the fourth implantation region have the same doping type, and the second implantation region and the third implantation region have opposite doping types.

[0022] Optionally, the step of forming the trench in the epitaxial layer includes: forming a pre-existing trench extending from a first surface into the interior of the epitaxial layer; a deposition step: depositing a passivation layer on the sidewalls of the pre-existing trench, exposing a portion of the bottom surface of the trench; an etching step: etching the epitaxial layer along the exposed bottom surface to obtain a new pre-existing trench; alternately performing the deposition step and the etching step at least once to form the upper half of the trench; and modifying the bottom of the trench using an isotropic plasma etching process to form the lower half of the trench, wherein the bottom surface of the lower half of the trench is an arc surface protruding toward the substrate.

[0023] According to this application, a trench extending along a first surface into the epitaxial layer is formed inside the epitaxial layer of a semiconductor device. The source region is located in the epitaxial layer on both sides of the trench, and the gate is located inside the trench. The gate includes a first portion and a second portion distributed along a first direction. Along the second direction, the maximum width of the first portion is smaller than the maximum width of the second portion. The bottom of the gate is an arc surface protruding towards the substrate, thereby increasing the trench opening width, which is beneficial for polysilicon filling and metallization processes. The wide top also increases the contact area between the gate and the epitaxial layer, effectively reducing the parasitic capacitance between the gate and the source region, thereby improving the switching speed of the device. At the same time, its sloping sidewalls help improve the electric field distribution in the channel region. The lower layer's arc curve replaces... This design eliminates the sharp corners that generate electric field peaks in traditional designs. By using a large radius of curvature, the electric field lines are smoothly guided to the center of the trench bottom, creating a gradient distribution of the electric field at the bottom of the trench. This significantly reduces the peak electric field intensity and the risk of breakdown caused by electric field concentration. In addition, the curved bottom helps improve charge migration in the channel, optimizes the current distribution in the on-state of the device, reduces on-resistance, and thus reduces power consumption and heat generation. This enhances the stability of the device in high-voltage and high-frequency applications, solves the problems of unreasonable electric field distribution and gate oxide reliability caused by electric field concentration in traditional device designs, and significantly improves the performance and reliability of semiconductor devices in high-voltage, high-frequency, and high-power application environments. Attached Figure Description

[0024] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0025] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of this application;

[0026] Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0027] Figure 3 This illustration shows a cross-sectional schematic diagram of the substrate provided in a method for fabricating a semiconductor device according to an embodiment of this application;

[0028] Figure 4 It shows in Figure 3 A cross-sectional schematic diagram of the matrix after the first injection region is formed in the epitaxial layer;

[0029] Figure 5 It shows in Figure 4 A cross-sectional schematic diagram of the matrix after the formation of the second injection region in the epitaxial layer;

[0030] Figure 6It shows in Figure 5 A cross-sectional schematic diagram of the matrix after the formation of the third injection region in the epitaxial layer;

[0031] Figure 7 It shows in Figure 6 A cross-sectional schematic diagram of the matrix after the fourth injection region is formed in the epitaxial layer;

[0032] Figure 8 It shows in Figure 7 A cross-sectional schematic diagram of the substrate after trenches are formed in the epitaxial layer;

[0033] Figure 9 It shows in Figure 8 A cross-sectional schematic diagram of the substrate after an oxide layer has formed in the trenches;

[0034] Figure 10 It shows in Figure 9 A cross-sectional schematic diagram of the substrate after a high-k dielectric layer is formed in the trench;

[0035] Figure 11 It shows in Figure 10 A cross-sectional schematic diagram of the substrate after the gate is formed in the trench;

[0036] Figure 12 It shows in Figure 11 A cross-sectional schematic diagram showing the formation of an insulating layer, an ohmic contact metal layer, and a source substrate on the epitaxial layer.

[0037] 10. Substrate; 20. Epitaxial layer; 210. First surface; 30. Source region; 310. First implantation region; 320. Second implantation region; 330. Third implantation region; 340. Fourth implantation region; 40. Trench; 50. Composite gate oxide layer; 510. Oxide layer; 511. First oxide portion; 512. Second oxide portion; 513. Third oxide portion; 520. High-k dielectric layer; 521. First high-k dielectric portion; 522. Second high-k dielectric portion; 523. Third high-k dielectric portion; 60. Gate; 610. First portion; 620. Second portion; 70. Insulating layer; 80. Ohmic contact metal layer; 90. Source; 100. Drain. Detailed Implementation

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0039] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0040] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0042] According to embodiments of this application, a semiconductor device is provided, such as... Figure 1 As shown, it includes:

[0043] The substrate includes a stacked substrate 10 and an epitaxial layer 20;

[0044] The trench 40 extends along the first surface 210 into the interior of the epitaxial layer 20, where the first surface 210 is the side of the epitaxial layer 20 facing away from the substrate 10.

[0045] The source region 30 is located in the epitaxial layers 20 on both sides of the trench 40. The source region 30 is the region formed by ion implantation of a portion of the first surface 210.

[0046] The gate 60 is located within the trench 40. The gate 60 includes a first portion 610 and a second portion 620 distributed along a first direction A. Along a second direction B, the maximum width of the first portion 610 is smaller than the maximum width of the second portion 620. The bottom of the gate 60 is an arc surface protruding toward the substrate 10. The first direction A is the direction in which the trench 40 is away from the substrate 10, and the second direction B is perpendicular to the extension direction of the trench 40.

[0047] In this embodiment, a trench 40 extending along the first surface 210 into the interior of the epitaxial layer 20 in the semiconductor device is formed. The source region 30 is located in the epitaxial layers 20 on both sides of the trench 40, and the gate 60 is located in the trench 40. The gate 60 includes a first portion 610 and a second portion 620 distributed along a first direction A. Along the second direction B, the maximum width of the first portion 610 is smaller than the maximum width of the second portion 620. The bottom of the gate 60 is an arc surface protruding towards the substrate 10, thereby increasing the opening width of the trench 40, which is beneficial for polysilicon filling and metallization processes. The wide top also increases the contact surface between the gate 60 and the epitaxial layer 20. The layer effectively reduces the parasitic capacitance between the gate 60 and the source region 30, thereby improving the switching speed of the device. At the same time, its sloping sidewalls help improve the electric field distribution in the channel region. The arc curve of the lower layer replaces the sharp corners that generate electric field peaks in traditional designs. With a large radius of curvature, the electric field lines are smoothly guided to the center of the bottom of the trench 40, so that the electric field presents a gradient distribution at the bottom of the trench 40, thereby significantly reducing the peak electric field intensity. This solves the problem of unreasonable electric field distribution and gate oxide reliability caused by electric field concentration in traditional device designs, and significantly improves the performance and reliability of semiconductor devices in high voltage, high frequency and high power application environments.

[0048] In this embodiment, the substrate material can be silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figure 1 As shown, the substrate includes a substrate 10 and an epitaxial layer 20. The doping concentration of the substrate 10 is higher than that of the epitaxial layer 20. The higher doping concentration of the substrate 10 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 10 can absorb charge carriers from the epitaxial layer 20, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 20 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0049] In this embodiment, the bottom of the gate 60 is designed as an arcuate surface protruding towards the substrate 10, replacing the sharp corners of traditional designs. Its larger radius of curvature smoothly guides the electric field lines, avoiding electric field concentration at the bottom of the trench. This significantly reduces the peak electric field intensity, substantially improving the reliability and lifespan of the gate oxide layer and reducing the risk of breakdown due to electric field concentration. Furthermore, the arcuate bottom also helps improve charge migration in the channel, reducing on-resistance, thereby reducing device power consumption and heat generation, and enhancing the stability of the semiconductor device in high-voltage, high-frequency applications.

[0050] In some alternative embodiments, the gate 60 and the trench 40 have corresponding cross-sectional shapes in the first direction A and the second direction B. The cross-section is a trapezoidal structure, and the bottom edge of the trapezoidal structure near the substrate 10 along the second direction B is smaller than the bottom edge away from the substrate 10. The bottom of the cross-section is arc-shaped.

[0051] Specifically, the slope of the trapezoidal sidewalls helps improve the electric field distribution in the channel region, thereby reducing the stress on the gate oxide layer, lowering the risk of degradation and breakdown, and improving the reliability and lifespan of the device.

[0052] In some optional embodiments, the semiconductor device further includes a composite gate oxide layer 50 located between the inner surface of the trench 40 and the gate 60. The composite gate oxide layer 50 includes an oxide layer 510 and a high-k dielectric layer 520. The oxide layer 510 is in contact with the inner surface of the trench 40, and the high-k dielectric layer 520 is in contact with the gate 60. The dielectric constant of the high-k dielectric layer 520 is greater than that of the oxide layer 510. The oxide layer 510 includes a first oxide portion 511, a second oxide portion 512, and a third oxide portion 513 connected in sequence. The high-k dielectric layer 520 includes a first high-k dielectric portion 521, a second high-k dielectric portion 522, and a third high-k dielectric portion 523 connected in sequence. The first oxide portion 511, the third oxide portion 513, the first high-k dielectric portion 521, and the third high-k dielectric portion 523 are located between the inner wall of the trench 40 and the gate 60. The second oxide portion 512 and the second high-k dielectric portion 522 are located between the bottom surface of the trench 40 and the gate 60, and the second oxide portion 512 and the second high-k dielectric portion 522 have arcuate surfaces protruding toward the substrate 10.

[0053] In the above optional embodiments, the oxide layer 510 can be made of SiO2, and the high-k dielectric layer 520 can be made of HfO2 or Al2O3. The thickness of the oxide layer 510 is less than the thickness of the high-k dielectric layer 520. The thin SiO2 layer ensures a high-quality interface with the substrate 10, thereby reducing the interface state density. HfO2 provides a high dielectric constant, which is about 4 to 5 times that of SiO2. This can significantly reduce the equivalent oxide layer thickness while maintaining a high breakdown field strength, thereby reducing the gate charge and increasing the switching speed without sacrificing reliability.

[0054] In some alternative embodiments, the semiconductor device further includes a ternary composite layer located between the inner surface of the trench 40 and the gate 60, the ternary composite layer comprising, in sequence along the first direction A, a buffer layer, a high-k dielectric layer and a surface passivation layer, wherein the dielectric constant of the high-k dielectric layer is greater than the dielectric constants of the buffer layer and the surface passivation layer.

[0055] In the above optional embodiments, the material of the buffer layer can be ZrO2, the material of the high-k dielectric layer 520 can be HfO2, and the material of the surface passivation layer can be Al2O3. This combination improves the interface state density while maintaining a high dielectric constant, and is suitable for high-frequency switching applications to ensure film uniformity and excellent interface state density.

[0056] In this embodiment, the source region 30 may include a first implantation region 310 and a second implantation region 320, a third implantation region 330, and a fourth implantation region 340 sequentially distributed in the first direction A. The first implantation region 310 and the fourth implantation region 340 are regions formed by ion implantation of a portion of the first surface 210, and the second implantation region 320 and the third implantation region 330 are regions formed by ion implantation of a portion of the epitaxial layer 20. The second implantation region 320, the third implantation region 330, and the fourth implantation region 340 are located between the first implantation region 310 and the trench 40. The second implantation region 320 and the third implantation region 330 are in contact, and the third implantation region 330 and the fourth implantation region 340 are in contact. The second implantation region 320 and the fourth implantation region 340 have the same doping type, and the second implantation region 320 and the third implantation region 330 have opposite doping types.

[0057] In the above embodiments, the second implantation region 320 and the fourth implantation region 340 can be first-type doped regions, having N-type or P-type doping, and the fourth implantation region 340 can be a second-type doped region, having P-type or N-type doping. For example, the first-type doped region has N-type doping and the second-type doped region has P-type doping, or the first-type doped region has P-type doping and the second-type doped region has N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). The embodiments of this application do not specifically limit the doping element.

[0058] Specifically, taking the first type of doped region having N-type doping and the second type of doped region having P-type doping as an example, the second implantation region 320, the third implantation region 330, and the fourth implantation region 340 form a shallow layer. The -PN structure, functionally equivalent to a junction field-effect transistor (JFET), is positioned on both sides of trench 40. When the MOSFET is turned off, a high voltage is applied between the drain and source. This voltage reverse-biases the PN junction in the JFET guard ring, thereby forming depletion regions on both sides of trench 40. These depletion regions constitute an electric field shielding ring with active current regulation capability, pushing the electric field lines away from the vulnerable bottom region of trench 40 and reducing the electric field peak at the gate oxide.

[0059] In this embodiment, the doping concentration of the epitaxial layer 20 can increase in a gradient along the first direction A.

[0060] In the above embodiments, a stepped gradient drift region with a total thickness of 10 μm is epitaxially grown on the substrate 10. For example, the doping concentration starts from 5E+15 cm near the substrate 10. -3 Smooth transition to 1.5E+16cm near the channel. -3 This allows for continuous gradient doping along the first direction A from low to high concentration, making the electric field distribution in the off state closer to the ideal rectangular distribution. This means that the electric field intensity in the entire drift region is more uniform, allowing it to withstand higher voltages. Furthermore, compared to traditional uniform doping, it can effectively reduce the on-resistance, achieving the optimal balance between electric field homogenization and on-resistance minimization.

[0061] In this embodiment of the application, the depth of the second injection region 320 may be less than the depth of the first injection region 310.

[0062] In the above embodiment, the depth of the second injection region 320 is less than the depth of the first injection region 310, which can avoid excessive leakage current and breakdown voltage drop under high drain voltage, so as to ensure that it can be depleted within the operating voltage range.

[0063] In this embodiment, the semiconductor device may further include: a source 90 located on the side of the epitaxial layer 20 away from the substrate 10 and in contact with the source region 30; an insulating layer 70 and an ohmic contact metal layer 80 located between the epitaxial layer 20 and the source 90, wherein the insulating layer 70 isolates the source 90 from the gate 60, and the ohmic contact metal layer 80 is in contact with the source 90 and the source region 30 respectively; and a drain 100 located on the side of the substrate 10 away from the epitaxial layer 20.

[0064] Specifically, the source 90 is disposed on the side of the epitaxial layer 20 away from the substrate 10 and directly contacts the source region 30, ensuring good conductivity between the source 90 and the source region 30. The insulating layer 70 is located between the gate 60 and the source 90, effectively isolating the source 90 from the gate 60 and avoiding parasitic capacitance between them, thereby further optimizing the switching performance of the device. The drain 100 is disposed on the side of the substrate 10 away from the epitaxial layer 20, ensuring continuity between the drain 100 and the substrate 10 and providing a stable current path for the device.

[0065] In the above embodiments, the materials of the source electrode 90 and the drain electrode 100 include metals and / or metal compounds, such as nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc., and metal compounds such as TiSi2 (titanium silicide), CoSi2 (cobalt silicide), etc. The embodiments of this application do not specifically limit the materials.

[0066] According to embodiments of this application, a method for fabricating a semiconductor device is provided, used to fabricate the semiconductor device described in the above embodiments, such as... Figure 2 As shown, the preparation method includes:

[0067] Step S1, providing a substrate, the substrate comprising a stacked substrate and an epitaxial layer, wherein the doping concentration of the epitaxial layer increases in a gradient along a first direction;

[0068] Step S2: A trench extending from the first surface to the interior and a source region are formed in the epitaxial layer. The first surface is the side of the epitaxial layer facing away from the substrate, and the source region is the area formed by ion implantation of a portion of the first surface.

[0069] Step S3: A gate is formed in the trench. The gate includes a first part and a second part distributed along a first direction. Along the second direction, the maximum width of the first part is smaller than the maximum width of the second part. The bottom of the gate is an arc surface protruding toward the substrate. The first direction is the direction in which the trench is away from the substrate, and the second direction is perpendicular to the extension direction of the trench.

[0070] In this embodiment, a trench extending from the first surface to the interior and a source region are formed within the epitaxial layer, and a gate is formed within the trench. The gate includes a first portion and a second portion distributed along a first direction. Along the second direction, the maximum width of the first portion is smaller than the maximum width of the second portion. The bottom of the gate is an arc surface protruding towards the substrate, thereby increasing the trench opening width, which is beneficial for polysilicon filling and metallization processes. The wide top also increases the contact area between the gate and the epitaxial layer, effectively reducing the parasitic capacitance between the gate and the source region, thereby improving the switching speed of the device. At the same time, its sloping sidewalls help improve the electric field distribution in the channel region. The arc curve of the lower layer replaces the traditional design. The sharp bends that generate electric field peaks in the trench smoothly guide the electric field lines to the center of the trench bottom through a large radius of curvature, resulting in a gradient distribution of the electric field at the bottom of the trench. This significantly reduces the peak electric field intensity and the risk of breakdown caused by electric field concentration. In addition, the arc-shaped bottom helps improve charge migration in the channel and optimizes the current distribution of the device in the on state, thereby reducing the power consumption and heat generation of the device and enhancing the stability of the device in high-voltage and high-frequency applications. It solves the problems of unreasonable electric field distribution and gate oxide reliability caused by electric field concentration in traditional device designs, and significantly improves the performance and reliability of semiconductor devices in high-voltage, high-frequency and high-power application environments.

[0071] Exemplary embodiments of the method for fabricating a semiconductor device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0072] First, such as Figure 3 As shown, a substrate is provided, the substrate comprising a stacked substrate 10 and an epitaxial layer 20, the doping concentration of the epitaxial layer 20 increasing in a gradient along a first direction A.

[0073] In some optional embodiments, this application further includes the step of forming the above-described substrate: providing a substrate 10 and forming an epitaxial layer 20 on the substrate 10 using an epitaxial process. Specifically, the material of the epitaxial layer 20 includes silicon carbide, and the material of the substrate 10 includes, but is not limited to, semiconductor materials such as silicon, silicon carbide, and gallium nitride; this application does not impose specific limitations on these materials.

[0074] In the above optional embodiments, the doping type of the substrate 10 and the epitaxial layer 20 is not specifically limited in this application embodiment. Taking the epitaxial layer 20 having N-type doping as an example: using N... - Type 4H-SiC ( <0001> Using a 4° off-axis wafer as the starting material, chemical vapor deposition is employed to grow a substrate 10 with a total thickness of 10 μm along the first direction A, from near the substrate 10 to near the channel. The silicon source is silane, and the carbon source is propane. Hydrogen is used as the carrier gas, and nitrogen is the nitrogen source. The nitrogen flow rate is gradually increased. - ³ increases in a gradient to 1.5E+16cm - ³ of N - The stepped gradient drift region, taking three segments as an example, can be grown separately: the bottom layer has a thickness of 4 μm and a doping concentration of 5E+15cm. - ³, middle layer thickness 3μm, doping concentration 1E+16cm - ³, with a top layer thickness of 3 μm and a doping concentration of 1.5E+16cm. - ³, the parameters are for reference only.

[0075] Specifically, the N of the device - The drift region has a doping gradient with a concentration distribution from low to high along the first direction A, which makes the electric field distribution in the off state closer to the ideal rectangular distribution. That is, the electric field intensity in the entire drift region is more uniform, and it can withstand higher voltage. Moreover, compared with traditional uniform doping, it can effectively reduce the on-resistance.

[0076] After providing a substrate including substrate 10 and epitaxial layer 20, step S2 is performed: as follows Figures 4 to 8 As shown, a trench 40 extending along the first surface 210 and a source region 30 are formed in the epitaxial layer 20. The first surface 210 is the side surface of the epitaxial layer 20 facing away from the substrate 10, and the source region 30 is the region formed by ion implantation of a portion of the first surface 210.

[0077] In some alternative implementations, the step of forming the source region 30 includes: as follows Figure 4 As shown, ion implantation is performed on a portion of the first surface 210 to form a first implantation region 310; as Figure 5 As shown, ion implantation is performed on a portion of the epitaxial layer 20 to form a second implantation region 320, and one side of the second implantation region 320 contacts the first implantation region 310; as Figure 6 As shown, ion implantation is performed on a portion of the epitaxial layer 20 to form a third implantation region 330, and one side of the third implantation region 330 contacts the first implantation region; as Figure 7 As shown, ion implantation is performed on another portion of the first surface 210 to form a fourth implantation region 340, and one side of the fourth implantation region 340 is in contact with the first implantation region 310; wherein, the second implantation region 320 and the third implantation region 330 are in contact, the third implantation region 330 and the fourth implantation region 340 are in contact, and the second implantation region 320 and the fourth implantation region 340 have the same doping type, while the second implantation region 320 and the third implantation region 330 have opposite doping types.

[0078] For example, the doping type of the first implantation region 310 can be p-type, and the doping concentration can be 1E+19~1E+20 cm⁻¹. -3 The doping depth can be 1.0~1.5μm. The P+ region is in 90° contact with the source. When the device is turned on, it can firmly clamp the P-well region potential at the source voltage, making the N... + The PN junction formed by the source region and the P-well is always in a reverse bias state, which can quickly remove excess holes generated in the P-well region, preventing the accumulation of holes in the P-well region that could lead to the conduction of parasitic NPN transistors and suppressing the latch-up effect; the doping type of the second implantation region 320 can be N-type, and the doping concentration can be 1E+17~5E+17cm. -3 The doping depth can be 0.5~0.8μm. The presence of the N-type region can reduce local resistance, decrease device on-resistance, and allow current to be distributed more evenly in the drift layer, thereby improving the device's current carrying capacity. The third implantation region 330 can be p-type doped, with a doping concentration of 1E+17~5E+17cm⁻¹. -3The doping depth can be 0.3~0.5μm. When a positive voltage is applied to the gate, an electron inversion layer is generated in the P-well region, forming an inversion channel that turns the device on. When the device is turned off in reverse, it interacts with the adjacent N-cells. + The source region and N-type layer form a reverse-biased PN junction, improving the device's blocking capability; the fourth implantation region 340 can be N-type doped, with a doping concentration of 1E+19~1E+20cm⁻¹. -3 The doping depth can be 0.2~0.3μm, N + The injected region is in direct contact with the source metal. The high concentration of doping significantly reduces the gold-semiconductor contact barrier, forming a low-resistance ohmic contact and reducing the on-resistance. The injected N-type charge carriers are pentavalent elements, including any one of phosphorus (P), arsenic (As), and antimony (Sb), and the injected P-type charge carriers are trivalent elements, including any one of boron (B), aluminum (Al), and gallium (Ga). The injection of N / P type charge carriers can be done in one or multiple injections. The energy and dose of each injection can be the same or different. This application does not make specific limitations on the embodiments.

[0079] In the above example, taking the first type of doped region as having N-type doping and the second type of doped region as having P-type doping, the second implantation region 320, the third implantation region 330, and the fourth implantation region 340 form a shallow layer. The -PN structure, functionally equivalent to a junction field-effect transistor (JFET), is positioned on both sides of the trench. When the MOSFET is turned off, a high voltage is applied between the drain and source. This voltage reverse-biases the PN junction in the JFET's guard ring, creating depletion regions on both sides of the trench. These depletion regions form an electric field shielding ring with active current regulation capability, pushing the electric field lines away from the vulnerable bottom region of the trench and reducing the electric field peak at the gate oxide.

[0080] In some alternative implementations, such as Figure 8 As shown, the steps for forming the trench 40 include: forming a pre-existing trench extending from the first surface 210 into the epitaxial layer 20; a deposition step: depositing a passivation layer on the sidewall of the pre-existing trench, exposing the bottom surface of the trench 40; an etching step: etching the epitaxial layer 20 along the exposed bottom surface to obtain a new pre-existing trench; alternating the deposition and etching steps at least once to form the upper half of the trench 40; and using an isotropic plasma etching process to modify the bottom of the trench to form an arc curve that smoothly connects with the trapezoidal trench and eliminate stress concentration points that may be left by the previous process, forming the lower half of the trench 40, wherein the bottom surface of the lower half of the trench is an arc surface protruding toward the substrate 10.

[0081] For example, the upper half of the trench 40 has a trapezoidal cross-section in the first direction A and the second direction B, while the lower half is a circular arc. The upper half of the trench 40 has a depth of 1.0~1.2μm, a bottom width of 1μm, and a sidewall inclination angle of 70~80°. The radius of the circular arc at the bottom of the lower half is 0.3~0.4μm. The trapezoidal structure of the upper half increases the trench opening width, which is beneficial for subsequent polysilicon filling and metallization processes. At the same time, its inclined sidewalls help improve the electric field distribution in the trench region. The circular arc radius of the lower half is 0.3μm~0.4μm. The circular arc changes the sharp corners that generate electric field peaks in traditional designs. By using a large radius of curvature, the electric field lines are smoothly guided to the center of the trench bottom, so that the electric field presents a gradient distribution at the bottom of the trench, effectively suppressing electric field concentration and thus significantly reducing the peak electric field intensity.

[0082] After forming the source region 30 and trench 40 within the epitaxial layer 20, step S3 is performed: (e.g.) Figures 9 to 11 As shown, a gate 60 is formed in the trench 40. The gate 60 includes a first portion 610 and a second portion 620 distributed along a first direction A. Along the second direction B, the maximum width of the first portion 610 is smaller than the maximum width of the second portion 620. The bottom of the gate 60 is an arc surface protruding toward the substrate 10. The first direction A is the direction in which the trench 40 is away from the substrate 10, and the second direction B is perpendicular to the extension direction of the trench 40.

[0083] In some alternative implementations, such as Figure 9 and Figure 10 As shown, an oxide layer 510 and a high-k dielectric layer 520 are grown between the surface of the trench 40 and the gate 60 using atomic layer deposition technology to form a composite gate oxide layer 50. The oxide layer 510 includes a first oxide portion 511, a second oxide portion 512, and a third oxide portion 513 connected in sequence. The high-k dielectric layer 520 includes a first high-k dielectric portion 521, a second high-k dielectric portion 522, and a third high-k dielectric portion 523 connected in sequence. The first oxide portion 511, the third oxide portion 513, the first high-k dielectric portion 521, and the third high-k dielectric portion 523 are located between the inner wall of the trench 40 and the gate 60. The second oxide portion 512 and the second high-k dielectric portion 522 are located between the bottom surface of the trench 40 and the gate 60, and the second oxide portion 512 and the second high-k dielectric portion 522 have arc surfaces protruding towards the substrate.

[0084] Specifically, the oxide layer 510 can be 2 nm thick and can be made of SiO2, while the high-k dielectric layer 520 can be 5 nm thick and can be made of HfO2 or Al2O3. The thin oxide layer 510 is used to ensure a high-quality interface with the epitaxial layer 20, and the high-k dielectric layer 520 provides a high dielectric constant (the dielectric constant of HfO2 is about 4 to 5 times that of SiO2). While maintaining the same physical thickness, the equivalent oxide layer thickness will be significantly reduced.

[0085] In some alternative embodiments, the composite gate oxide layer in the above alternative embodiments is replaced with a ternary composite layer, including a buffer layer, a high-k dielectric layer and a surface passivation layer. The high-k dielectric layer is an intermediate layer with a thickness of 4 nm and can be made of HfO2. The buffer layer is located at the bottom of the trench 40 with a thickness of 1 nm and can be made of ZrO2. The surface passivation layer is in contact with the gate and has a thickness of 2 nm and can be made of Al2O3. This combination improves the interface state density while maintaining a high dielectric constant, making it suitable for high-frequency switching applications to ensure film uniformity and excellent interface state density.

[0086] In the above optional implementations, such as Figure 11 As shown, N is filled in the trench 40. + Doped polysilicon is used as the gate 60, and its thickness can be 0.5~1μm.

[0087] After the step of forming the gate 60, embodiments of this application may further include the following steps: such as Figure 12 As shown, an ohmic contact metal layer 80 and an insulating layer 70 are formed on the epitaxial layer 20, and a source electrode 90 is formed on the ohmic contact metal layer 80; as Figure 1 As shown, a drain 100 is formed on the side of the substrate 10 away from the epitaxial layer 20.

[0088] Specifically, the source 90 is disposed on the side of the epitaxial layer 20 away from the substrate 10 and directly contacts the source region 30, ensuring good conductivity between the source 90 and the source region 30. The insulating layer 70 is located between the gate 60 and the source 90, effectively isolating the source 90 from the gate 60 and avoiding parasitic capacitance between them, thereby further optimizing the switching performance of the device. The drain 100 is disposed on the side of the substrate 10 away from the epitaxial layer 20, ensuring continuity between the drain 100 and the substrate 10 and providing a stable current path for the device.

[0089] It should be noted that the process steps and sequence in the above method for fabricating a MOSFET power device in the embodiments of this application are not fixed and can be adjusted according to the actual process. The formation of each layer structure requires one or more semiconductor processes such as masking, photolithography, etching, and cleaning, which will not be described in detail in the embodiments of this application.

[0090] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0091] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A semiconductor device, characterized by, The application relates to a semiconductor device, comprising: a substrate, including a laminated substrate and an epitaxial layer; a trench extending into the epitaxial layer along a first surface, the first surface being a side surface of the epitaxial layer facing away from the substrate; a source region in the epitaxial layer on both sides of the trench, the source region being a region formed by ion implantation on part of the first surface; a gate in the trench, the gate including a first part and a second part distributed along a first direction, the maximum width of the first part being smaller than the maximum width of the second part along a second direction, the bottom of the gate being an arc surface protruding towards the substrate, the first direction being a direction in which the trench faces away from the substrate, and the second direction being perpendicular to the extension direction of the trench.

2. The semiconductor device according to claim 1, wherein The shape of the cross section of the gate and the trench in the first direction and the second direction corresponds, the cross section being a trapezoidal structure, the bottom edge of the trapezoidal structure close to the substrate along the second direction being smaller than the bottom edge facing away from the substrate, and the bottom of the cross section being in a circular arc shape.

3. The semiconductor device of claim 1, wherein Further comprising a composite gate oxide layer between the inner surface of the trench and the gate, the composite gate oxide layer including an oxide layer and a high-k dielectric layer, the oxide layer being in contact with the inner surface of the trench, the high-k dielectric layer being in contact with the gate, and the dielectric constant of the high-k dielectric layer being greater than the dielectric constant of the oxide layer; or Further comprising a ternary composite layer between the inner surface of the trench and the gate, the ternary composite layer including, in sequence along the first direction, a buffer layer, a high-k dielectric layer and a surface passivation layer, the dielectric constant of the high-k dielectric layer being greater than the dielectric constant of the buffer layer and the surface passivation layer; The oxide layer includes a first oxide part, a second oxide part and a third oxide part connected in sequence, the high-k dielectric layer includes a first high-k dielectric part, a second high-k dielectric part and a third high-k dielectric part connected in sequence, the first oxide part, the third oxide part, the first high-k dielectric part and the third high-k dielectric part being between the inner wall of the trench and the gate, the second oxide part and the second high-k dielectric part being between the bottom surface of the trench and the gate, and the second oxide part and the second high-k dielectric part having an arc surface protruding towards the substrate.

4. The semiconductor device of claim 1, wherein The source region includes a first implantation region and second, third and fourth implantation regions distributed in sequence along the first direction, the first implantation region and the fourth implantation region being regions formed by ion implantation on part of the first surface, the second implantation region and the third implantation region being regions formed by ion implantation on part of the epitaxial layer, the second implantation region, the third implantation region and the fourth implantation region being between the first implantation region and the trench, the second implantation region and the third implantation region being in contact, the third implantation region and the fourth implantation region being in contact, and the second implantation region and the fourth implantation region having a first doping type, and the second implantation region and the third implantation region having opposite doping types.

5. The semiconductor device of claim 1, wherein The doping concentration of the epitaxial layer increases in a gradient along the first direction.

6. The semiconductor device of claim 4, wherein The depth of the second implantation region is smaller than the depth of the first implantation region.

7. The semiconductor device according to any one of claims 1 to 6, wherein Further comprising: a source electrode on a side of the epitaxial layer facing away from the substrate and in contact with the source region; an insulating layer and an ohmic contact metal layer between the epitaxial layer and the source electrode, the insulating layer separating the source electrode and the gate electrode, and the ohmic contact metal layer in contact with the source electrode and the source region, respectively; a drain electrode on a side of the substrate facing away from the epitaxial layer.

8. A method of manufacturing a semiconductor device, characterized by, A method for manufacturing the semiconductor device of any one of claims 1 to 7, the method comprising the steps of: providing a substrate comprising a layered substrate and an epitaxial layer; forming a trench extending to an interior along a first surface in the epitaxial layer, the first surface being a side surface of the epitaxial layer facing away from the substrate, and forming the source region in the epitaxial layer, the source region being a region formed by ion implantation on part of the first surface; forming a gate electrode in the trench, the gate electrode comprising a first portion and a second portion distributed along a first direction, the maximum width of the first portion being smaller than the maximum width of the second portion along a second direction, the bottom of the gate electrode being a curved surface protruding towards the substrate, the first direction being a direction of the trench facing away from the substrate, and the second direction being perpendicular to the direction of extension of the trench.

9. The production method according to claim 8, characterized by, The step of forming the source region in the epitaxial layer comprises: ion implantation on part of the first surface to form a first implantation region; ion implantation on part of the epitaxial layer to form a second implantation region between the first implantation region and the trench, the second implantation region being in contact with the first implantation region and the trench on both sides, respectively; ion implantation on part of the epitaxial layer to form a third implantation region between the first implantation region and the trench, the third implantation region being in contact with the first implantation region and the trench on both sides, respectively; ion implantation on another part of the first surface to form a fourth implantation region between the first implantation region and the trench, the fourth implantation region being in contact with the first implantation region and the trench on both sides, respectively; wherein the second implantation region and the third implantation region are in contact, the third implantation region and the fourth implantation region are in contact, the second implantation region and the fourth implantation region have the same doping type, and the second implantation region and the third implantation region have opposite doping types.

10. The preparation method according to claim 8, characterized in that, The step of forming the trench in the epitaxial layer comprises: forming a preliminary trench extending to an interior along a first surface in the epitaxial layer; a deposition step of depositing a passivation layer on the sidewall of the preliminary trench, part of the bottom surface of the trench being exposed; an etching step of etching the epitaxial layer along the exposed part of the bottom surface to obtain a new preliminary trench; alternately performing the deposition step and the etching step at least once to form an upper half of the trench; modifying the bottom of the trench using an isotropic plasma etching process to form a lower half of the trench, the bottom surface of the lower half of the trench being a curved surface protruding towards the substrate.

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