Manufacturing process for vertical GaN-based microelectronic devices

Abstract

Title: Method for manufacturing vertical microelectronic devices based on GaN The invention relates to a method for manufacturing at least one microelectronic device (1a, 1b, 2a, 2b) comprising the provision of a substrate (10) and the performance of a localized epitaxy of gallium nitride (GaN) on the substrate, so as to form at least one island (100a, 100b) based on GaN, each island comprising a migration layer (130a, 130b) based on GaN. The process further comprises, at each island (100a, 100b), a step of forming a first layer (110a, 110b) based on GaN doped with a first type (p or n), the first layer (110a, 110b) forming a plurality of doped wells separated from each other, and a step of forming a drain electrically connected to each island (100a, 100b), thus forming at least one vertical transistor (1a, 1b). Figure for the abstract: Fig. 2J

Description

Title of the invention: Method for manufacturing vertical microelectronic devices based on GaN. Technical field

[0001] The present invention relates to the field of microelectronic devices, in particular GaN-based components. It finds, for example, a particularly advantageous application in the field of power electronics. STATE OF THE ART

[0002] The main microelectronic devices, and in particular transistors and diodes, can be designed according to numerous transistor architectures, including vertical microelectronic devices. The properties of vertical transistors, for example, are currently being particularly exploited in power electronics applications.

[0003] Vertical GaN-based devices are typically fabricated by epitaxy from GaN substrates. However, the GaN substrates available in industry are of small diameter. Current processes for fabricating vertical GaN devices on GaN substrates therefore do not allow for the simultaneous production of a quantity of devices comparable to that achieved on larger diameter substrates (typically silicon substrates). These processes are also very expensive due to the high price of GaN substrates.

[0004] One objective of the present invention is therefore to propose a method for manufacturing vertical GaN-based devices that solves at least some of the problems mentioned above. SUMMARY

[0005] To achieve this objective, a first aspect of the invention relates to a method for manufacturing at least one microelectronic device comprising the following steps: - provide a substrate with a top surface, - to carry out localized epitaxy of gallium nitride (GaN) on the upper face of the substrate, so as to form at least one GaN-based island, each island having a face, called the lower face, facing the upper face of the substrate, each island comprising a so-called migration layer based on GaN, the migration layer having a lower face facing the upper face of the substrate and an upper face opposite to the lower face, - at the level of each island, form a first layer based on GaN doped with a first type taken from an n-type doping and a p-type doping, the first layer forming a plurality of doped wells separated from each other and each extending from the upper face of the migration layer, - to form an electrically conductive layer forming a drain, the drain being electrically connected to the underside of each island, thus forming at least one vertical transistor.

[0006] Thus, the process according to the invention makes it possible to initiate the formation of devices on a large and inexpensive substrate, such as a silicon substrate. This avoids the need for a costly and small GaN substrate. The steps for forming grids, source contacts, anodes, or other conventional elements can be carried out while the islands are resting on the substrate, or after removing the substrate. Forming the drain on the back side simply requires prior removal of the substrate by grinding and / or CMP and / or etching, or by creating metallic interconnects within the substrate, which is perfectly reasonable in the case of a silicon substrate. This results in fully vertical GaN devices without having to sacrifice a GaN substrate.

[0007] Local epitaxy of GaN can also allow the formation of islands up to 10 pm or even 20 pm in height. Thanks to this, the transistors formed by the process can withstand voltages as high as 1200V or even 2200V.

[0008] Furthermore, the process makes it possible to efficiently manufacture vertical devices with a very high substrate coverage rate. For hexagonal islands, for example, the surface area lost due to gaps between islands is between 5 and 10% of the total surface area, which is very low.

[0009] Thus, the process according to the invention allows for efficient, large-scale, and inexpensive manufacturing of vertical GaN-based devices. The manufactured devices are also very compact and robust. BRIEF DESCRIPTION OF THE FIGURES

[0010] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0011] [Fig. 1 A] Figures 1A to II illustrate a first embodiment of the process according to the invention for manufacturing diodes.

[0012] [Fig.1B]

[0013] [Fig.1C]

[0014] [Fig.1D]

[0015] [Fig.1E]

[0016] [Fig.1F] Figures 1F and 1G illustrate an example in which the substrate is removed and the drain is formed in direct contact with the islands.

[0017] [Fig.1G]

[0018] [Fig.1H] Figures 1H and II illustrate an example in which metallic interconnections are formed in the substrate and the drain is formed at the contact of these interconnections.

[0019] [Fig. II]

[0020] [Fig.2A] Figures 2A to 2J illustrate a second embodiment of the process according to the invention for manufacturing transistors.

[0021] [Fig.2B]

[0022] [Fig.2C]

[0023] [Fig.2D]

[0024] [Fig.2E]

[0025] [Fig.2F]

[0026] [Fig.2G]

[0027] [Fig.2H]

[0028] [Fig.2I]

[0029] [Fig.2J]

[0030] [Fig.3A] Figures 3A to 3C are scanning electron microscopy (SEM) images of GaN islands grown by localized epitaxy.

[0031] [Fig.3B] [Fig.3B] is an enlargement of [Fig.3A].

[0032] [Fig.3C] [Fig.3C] is an enlargement of [Fig.3B].

[0033] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0034] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0035] According to one example, the substrate is silicon-based.

[0036] According to an example, each island has a height hiOo greater than or equal to 10 pm, preferably greater than or equal to 20 pm, hiOo being measured in a direction perpendicular to a plane in which the upper face of the substrate extends predominantly.

[0037] According to one embodiment, the drain formation step comprises the following steps: - after the formation of at least one island, remove the substrate, then - form the drain against the underside of at least one island.

[0038] According to one embodiment, the drain formation step comprises the following steps: - for each island, form at least one metallic interconnection passing through the substrate and opening onto said island, - form the drain against an underside of the substrate opposite its upper side, the drain being in contact with at least one metallic interconnection.

[0039] According to a particular embodiment, the process according to the invention is a process for manufacturing at least one vertical transistor and further comprises the following steps: - at the level of each island, partially implant the first layer so as to form at least one pair of regions, called sources, doped with the other type of doping, either n-type or p-type, the sources of the same pair of sources being located in distinct doped wells, - to form at least one electrically conductive pattern, called a grid, in contact with both sources of the same pair of sources, - to form an electrically conductive contact, called a source contact, at the contact of each source of the same pair of sources.

[0040] According to one example, the first layer forms at least three doped wells and in which at least two pairs of sources are formed in these at least three doped wells, two sources belonging to distinct pairs of sources being formed in the same doped well.

[0041] According to one example, the source contacts in contact with the sources formed in the same doped well are in electrical continuity and form a common source contact for the two transistors.

[0042] According to one example, the substrate removal step is carried out before the formation of the source contact, possibly before the formation of the grid, possibly before the implantation and formation of the sources step.

[0043] According to one example, the substrate removal step is carried out after the source implantation and formation step, possibly after grid formation, possibly after source contact formation.

[0044] According to one embodiment, the first layer formation step comprises the following steps: - at the level of each islet, form at least one opening in the migration layer extending from the upper face of the migration layer, - at the level of each islet, form the first layer in each of the openings in the migration layer of the islet, the first layer thus forming the plurality of doped wells.

[0045] According to one embodiment, the first layer formation step comprises the following steps: - at the level of each island, form on the migration layer a continuous layer of GaN doped with the first type, - at the level of each island, form in the continuous GaN layer secondary openings separated from each other and completely traversing said continuous layer of doped GaN, so as to partially update the migration layer, the remaining portions of the continuous layer forming the first layer, - at the level of each islet, grow the migration layer in the secondary openings by epitaxy.

[0046] According to a particular embodiment, the process according to the invention is a process for manufacturing at least one diode and further comprises the following step: - form an electrically conductive pattern called an anode in contact with at least two doped wells, preferably with all doped wells.

[0047] According to one example, the substrate removal step is carried out before the anode formation.

[0048] According to one example, the substrate removal step is carried out after the formation of the anode.

[0049] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0050] A layer may also be composed of several sub-layers of the same material or of different materials.

[0051] A substrate, layer, or device "based" on a material M means a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example alloying elements, impurities, or dopant elements.

[0052] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. The selectivity is the ratio between the etching speed of material A and the etching speed of material B. The selectivity between A and B is denoted SA:B.

[0053] Two elements are said to be "electrically connected" when they are each in contact with the same continuous electrical connection element having an electrical conductivity preferably greater than 107 S / m.

[0054] A coordinate system, preferably orthonormal, comprising the X, Y, Z axes is shown in figures IA, 2A and 3A. This coordinate system is applicable by extension to the other figures. The Z direction may be designated as the "stacking direction".

[0055] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the longitudinal plane XY. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along Z when it extends mainly along the longitudinal plane XY, and a projecting element, for example an insulation trench, has a height along Z. The relative terms "on," "under," "above," "below," and "below" preferentially refer to positions measured along the Z direction.

[0056] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0057] A first embodiment of the process according to the invention for manufacturing diodes la, 1b will now be described with reference to Figures IA to IG. These figures illustrate the simultaneous formation of two diodes la, 1b, but it is understood that a larger number of diodes can be manufactured simultaneously by the process according to the invention.

[0058] Figure 1A illustrates the provision of a substrate 10. This substrate 10 is typically silicon-based. It has a top face 11 extending mainly in an XY plane, which can be designated the longitudinal XY plane. This plane is defined by a first direction X and a second direction Y. The substrate 10 further has a bottom face 12 opposite its top face 11.

[0059] Advantageously, buffer layers 15 are deposited on the upper face 11 of the substrate 10. These buffer layers 15 can, for example, each be based on one of the following materials: GaN, AIN, AlGaN, BN.

[0060] As illustrated in [Fig. 1B], GaN-based islands 100a, 100b are then locally grown by epitaxy on the upper face 11 of the substrate 10. Typically, these Islands 100a and 100b are grown from buffer layers 15. Figure 3A illustrates the experimental result of this step: it is a top view obtained by SEM of a set of islands grown by localized epitaxy on a silicon substrate. This image notably shows that a large number of islands can be grown simultaneously by localized epitaxy.

[0061] The islands 100a, 100b are separated from each other. Thus, preferably, no residual continuous layer of GaN is found on the upper face 11 of the substrate 10 (with the exception of possible buffer layers which may include GaN).

[0062] The islands 100a, 100b each have a lower face 102a, 102b which is opposite the upper face 11 of the substrate 10, and typically in contact with the buffer layers 15. They also each have an upper face 101a, 101b opposite the lower face 102a, 102b.

[0063] The epitaxy step of the GaN islands 100a, 100b is advantageously configured to form GaN layers within each island 100a, 100b having different doping levels. According to an advantageous example, the islands 100a, 100b comprise, from the lower faces 102a, 102b of the islands 100a, 100b towards their upper faces 101a, 101b, an n+ doped GaN layer and an n- doped GaN layer, which can be designated as a migration or drift layer 130a, 130b.

[0064] In a perfectly classical way, the dopant of the n-doped layers can be silicon (Si) or germanium (Ge) and the dopant of the p-doped layers magnesium (Mg).

[0065] The islands 100a, 100b have a characteristic dimension in the XY plane denoted lioo-. In projection onto the XY plane, the islands 100a, 100b typically each have a hexagonal shape, as can be seen in [Fig. 3A]. In this case, the characteristic dimension hoo corresponds to the distance between two facing sides of the islands 100a, 100b. In [Fig. 3B], lioo is, for example, measured along the first X direction. hoo is preferably greater than 100 pm, and preferably less than or equal to 200 pm.

[0066] The lateral sides 103a, 103b of the islands 100a, 100b are typically inclined with respect to the stacking direction Z, as illustrated in the figures, l^o is then measured at the base of the islands 100a, 100b, at the level of their lower face 102a, 102b.

[0067] The islands 100a, 100b have a height hiOo measured along the Z direction (also designated the stacking direction Z) perpendicular to the longitudinal plane XY. The height h»» is preferably greater than 10 pm or even 20 pm.

[0068] In the longitudinal plane XY, the islands 100a, 100b are separated by a distance D (taken along the first direction X in Figures 1B, 3B and 3C). D is measured at the base of the islands 100a, 100b, that is, at the height along Z at which the lower faces 102a, 102b of the islands 100a, 100b are located. The distance D is typically greater at 5 pm. The distance D is preferably less than 20 pm, or even less than 15 pm, or even 10 pm. D is typically between 10 and 15 pm. This allows for the fabrication of devices with a better density. For example, it is approximately equal to 8 pm.

[0069] The numerical values ​​given above are also valid for the second embodiment which will be described further.

[0070] As also illustrated in [Fig.1B], the lateral sides 103a, 103b of the islands 100a, 100b are advantageously covered with a passivation layer 150. The passivation layer 150 is for example based on alumina or SiN.

[0071] The spaces left empty between the islands 100a, 100b are preferably filled by a filler layer 160 based on a dielectric material, for example, silica-based or tetraethyl orthosilicate (TEOS). The filler layer 160 can be deposited by chemical vapor deposition (CVD). Advantageously, this deposition is carried out using a low-stress method.

[0072] The deposition of the filling layer 160 can be followed by a planarization step at the level of the upper face 101a, 101b of the islands 100a, 100b.

[0073] An etching step is then carried out starting from the upper faces 101a, 101b of the islands 100a, 100b ([Fig. 1C]). This etching step is configured to form at least one aperture 20, and preferably a plurality of apertures 20, in each island 100a, 100b. Each aperture 20 partially penetrates the migration layer 130a, 130b. As will become apparent later, the dimensions of the apertures 20 determine those of the active areas of the diodes 1a, 1b. The apertures 20, for example, have a width l20 along the first X direction, with l20 ranging from 100 nm to 4000 nm. Along the second Y direction, the apertures 20 can completely penetrate the islands 100a, 100b. The 20 apertures also have a height h2o along the stacking direction Z. h20 is typically greater than or equal to 400nm.

[0074] In a perfectly conventional manner, this etching step can be carried out by dry etching through a masking layer 30, as illustrated in [Fig. 1C]. For this, conventional photolithography steps can be used. The masking layer 30 can, for example, be made of alumina, SiN, SiO2, or even be a SiO2 / Al2O3 multilayer.

[0075] In a step illustrated in [Fig. 1D], a first layer 110a, 110b is formed by epitaxy in the openings 20 of each island 100a, 100b. The first layer 110a, 110b is based on doped GaN. Its doping can be n-type or p-type. Since the first layer 110a is formed in the openings 20, it is discontinuous. It thus forms separate doped regions in the migration layer 130a, 130b. These are called doped wells. The width l110 of each doped well is approximately equal to the width l20 of the openings 20. The same is true for the thickness en0 of the doped wells, which is approximately equal to the height h20 of the openings 20.

[0076] Doping of the first layer 110a, 110b is preferably performed during epitaxy of the latter. This allows for better control of the concentration and activation of the dopants within the first layer 110a, 110b. However, it is also possible to perform epitaxy followed by doping by implantation.

[0077] The masking layer 30 is then removed.

[0078] According to an alternative embodiment not shown, the first layer 110a, 110b can be formed as follows, from the assembly shown in [Fig. 1B]. A continuous layer of n- or p-doped GaN is first formed above the migration layer 130a, 130b of each island 100a, 100b. The thickness of the continuous layer is substantially equal to the height of the apertures 20 of the previous embodiment, h2o. An etching step is then performed in this continuous layer. This etching step is configured to form at least one secondary aperture, and preferably a plurality of secondary apertures, in the continuous GaN layer of each island 100a, 100b. The etching is also configured so that the secondary openings fully traverse the continuous layer of doped GaN, in order to partially update the underlying 130a, 130b migration layer.This etching step can be carried out using conventional masking and photolithography techniques.

[0079] The remaining portions, i.e., the unetched portions, of the continuous GaN layer form the doped wells. They thus form the first layer 110a, 110b. The secondary openings are therefore sized so that the remaining doped wells have the desired dimensions. Epitaxial growth is then carried out from the migration layer 130a, 130b in the secondary openings. The migration layer 130a, 130b is thus preferably extended so as to be flush with the first layer 110a, 110b. This results in the assembly illustrated in [Fig. 1D] (with the exception of the masking layer 30).

[0080] As illustrated in [Fig. 1E], an electrically conductive pattern, designated anode 500, is then formed on the stack. The anode 500 is in contact with at least two doped wells of the same island 100a, 100b. Advantageously, it is in contact with all the doped wells of the same island 100a, 100b. According to an advantageous embodiment illustrated in [Fig. 1E], the anode extends continuously over a plurality of islands 100a, 100b. It can thus contact all the doped wells of these islands 100a, 100b, as illustrated.

[0081] As illustrated in [Fig. 1F], it is then possible to remove the substrate 10 and any buffer layers 15. This removal is typically carried out by grinding and chemical-mechanical polishing (CMP). Advantageously, a major part of the removal is carried out by grinding and CMP, and then the removal is finalized by selective etching or time etching to stop precisely on the lower face 102a, 102b of the islands 100a, 100b.

[0082] Advantageously, the removal of the substrate 10 and the buffer layers 15 occurs after the islands 100a, 100b have been transferred onto a handle-substrate (not shown). This transfer takes place on the upper face 101a, 101b side of the islands 100a, 100b. The handle-substrate is removed after the formation of the drain 400 described above.

[0083] The removal of the substrate 10 and the buffer layers 15 can also occur earlier in the process. The substrate 10 can indeed be removed after the formation of the islands 100a, 100b (and the optional formation of the passivation layer 150 and the filling layer 160), and before the formation of the first layer 110a, 110b or the anode 500, between the steps illustrated in Figures IB and IC, IC and 1D or 1E and 1D. This makes it possible to reduce the mechanical stresses within the stack during the formation of the first layer 110a, 110b and the anode 500.

[0084] After the substrate 10 is removed, an electrically conductive layer called the drain 400 is formed in contact with the lower faces 102a, 102b of the islands 100a, 100b. This drain 400 extends continuously under the islands 100a, 100b. It is thus common to all the diodes 1a, 1b. The formation of the drain 400 is typically carried out by electrochemical metal deposition.

[0085] According to another example, after the removal of the substrate 10 and the buffer layers 15, the islands 100a, 100b are transferred by their lower faces 102a, 102b onto a silicon wafer heavily doped with n-type doping. Advantageously, the transfer is achieved via metallic layers promoting adhesion and / or electrical conduction between the islands 100a, 100b and the silicon wafer, such as Ti, Au and / or Al-based layers. The drain 400 is then deposited on the rear face of the silicon wafer, opposite the islands 100a, 100b.

[0086] According to an alternative embodiment illustrated in Figures 1H and 1H, rather than removing the substrate 10 and the buffer layers 15, metallic interconnections are made. Thus, as illustrated in [Fig. 1H], it is possible to create through-holes 13 by etching, completely traversing the substrate 10 and optionally the buffer layers 15. The through-holes 13 thus extend, in particular, from the upper face 11 to the lower face 12 of the support. At least one through-hole 13 is formed opposite each island 100a, 100b. The through-holes 13 are typically formed by a photolithography and etching process. The openings The through-holes 13 are then filled with an electrically conductive material, typically a metal, to form metallic interconnections 14 that also pass through the substrate 10 and the buffer layers 15. The drain 400 is then formed against the underside 12 of the substrate 10 ([Fig. II]). The drain 400 is formed in contact with at least one metallic interconnection 14, preferably all of the metallic interconnections 14. The metallic interconnections 14 provide the electrical connection between the drain 400 and the islands 100a, 100b.

[0087] The process thus makes it possible to form at least one diode la, 1b, each formed of the following elements: - Drain 400, or at least a portion of drain 400, - An island 100a, 100b, comprising layers of GaN with distinct doping levels including the migration layer 130a, 130b and the first layer 110a, 110b (in the form of doped wells), - At least one anode 500 deposited in contact with the first layer 110a, 110b of the island 100a, 100b considered, or at least a portion of this anode 500.

[0088] The presence of a plurality of doped wells within each diode la, 1b makes it possible to increase their power. Advantageously, each diode la, 1b comprises at least three doped wells, preferably at least five doped wells.

[0089] A second embodiment allowing the manufacture of transistors 2a, 2b will now be described with reference to figures 2A to 2J.

[0090] The second embodiment can, for example, begin like the first embodiment with the provision of a substrate 10 and advantageously buffer layers 15, as illustrated in [Fig. 2A], then the formation of islands 100a, 100b, as illustrated in [Fig. 2B]. The characteristics described with reference to Figures IA and IB in the context of the first embodiment apply fully here.

[0091] An etching step is then performed starting from the upper faces 101a, 101b of the islands 100a, 100b. This etching step is configured to form at least two apertures 20', and preferably at least three apertures 20', in each island 100a, 100b. Each aperture 20' partially penetrates the migration layer 130a, 130b. As will become apparent later, the dimensions of the apertures 20' determine those of the active areas of the transistors 2a, 2b. The apertures 20', for example, have a width l20' along the first X direction, with l20' ranging from 1500 nm to 5000 nm. Along the second Y direction, the apertures 20' preferably pass completely through the islands 100a, 100b. In this case, the openings have a band-like shape in the longitudinal XY plane. However, other configurations are perfectly possible. For example, the 20' openings can have a square, circular, or hexagonal shape in the longitudinal XY plane.The openings 20'. They can be arranged in the longitudinal XY plane according to a square or hexagonal lattice, particularly in the case of apertures that are themselves hexagonal. The 20' apertures also have a height h20' along the Z stacking direction. Regardless of the shape of the 20' apertures in the longitudinal XY plane, h20' is typically greater than or equal to 400 nm.

[0092] In a perfectly conventional manner, this etching step can be carried out by dry etching through a masking layer 30, as illustrated in [Fig. 2C]. For this, conventional photolithography steps can be used.

[0093] Similar to the first embodiment, in a step illustrated in [Fig. 2D], a first layer 110a, 110b is formed in the openings 20' of each island 100a, 100b. The first layer 110a, 110b is based on doped GaN. Its doping, carried out during epitaxy or by implantation, can be of type n or type p. Since the first layer 110a is formed in the openings 20, it is discontinuous. It thus forms doped regions separated from each other in the migration layer 130a, 130b, called doped wells. The width l110 of each doped well is substantially equal to the width l20' of the openings 20' formed previously. The same applies to the thickness en0 of the doped wells, which is approximately equal to the height h20' of the 20' openings.

[0094] The masking layer 30 is then removed ([Fig.2E]).

[0095] As in the first embodiment, alternatively, the formation of the The first layer 110a, 110b can go through the following steps: - Deposition of a continuous layer of doped GaN on the migration layer 130a, 130b, - Formation of secondary openings in the continuous layer so as to partially update the migration layer 130a, 130b, - Growth by epitaxy of the migration layer 130a, 130b through secondary openings.

[0096] We then obtain the set illustrated in [Fig.2E].

[0097] Next, a localized implantation is carried out in the first layer 110a, 110b ([Fig. 2F]). This implantation is configured to form at least two doped regions, called sources, forming a pair of sources 120a, 120a', 120b, 120b'. Within a pair of sources 120a, 120a', 120b, 120b', a first source is located in a first doped well and a second source is located in a second doped well distinct from the first. A single doped well can accommodate several sources, preferably two sources. [Fig. 2F] illustrates, for example, at each island 100a, 100b, two pairs of sources distributed in three doped wells. The implantation is advantageously an n-type implantation, with silicon as the species implanted. Following implantation, activation annealing is preferably performed. Preferably, activation annealing is carried out in the presence of a protective layer overlying the migration layer 130a, 130b in order to protect the GaN. The protective layer can, for example, be based on SiN, SiO2, or AIN.

[0098] As illustrated in [Fig. 2G], at least one electrically conductive pattern designated grid 200a, 200a', 200b, 200b' is then formed on each island 100a, 100b. Each grid 200a, 200a', 200b, 200b' is in contact with the two sources of the same pair. For example, in the figures, the grid bearing the reference 200a is in contact with the sources referenced 120a.

[0099] Electrically conductive contacts, referred to as source contacts 300a, 300a', 300b, 300b', are then formed in contact with the sources 120a, 120a', 120b, 120b' ([Fig. 2H]). As illustrated, a common contact can be formed between sources located in the same doped well. This creates a short circuit between the two sources, thus preventing the formation of a conducting bipolar transistor in parallel with the transistors fabricated 2a, 2b.

[0100] Figures 21 and 2J illustrate the removal of the substrate 10 and any buffer layers 15 and the formation of a drain 400' in contact with the lower face 102a, 102b of the islands 100a, 100b. These steps can be carried out in the same way as described previously with reference to the first embodiment. They can intervene at different times in the process, for example between the formation of the islands 100a, 100b and the formation of the first layer 110a, 110b, between the formation of the first layer 110a, 110b and that of the sources 120a, 120a', 120b, 120b', between the formation of the sources 120a, 120a', 120b, 120b' and that of the grids 200a, 200a', 200b, 200b', between the formation of the grids 200a, 200a', 200b, 200b' and that of the source contacts 300a, 300a', 300b, 300b' or even after the latter.

[0101] Just as in the first embodiment, it is also possible to make metallic interconnections in the substrate 10 and in the buffer layers 15 and to form the drain in contact with the lower face 12 of the substrate 10.

[0102] The process thus makes it possible to form at least one transistor 2a, 2b, each formed of the following elements: - Drain 400, or at least a portion of drain 400, - An island 100a, 100b, comprising layers of GaN with distinct doping levels including the migration layer 130a, 130b and the first layer 110a, 110b (in the form of doped wells), - At least two sources 120a, 120a', 120b, 120b', - At least one grid 200a, 200a', 200b, 200b' electrically connecting the two sources, - Source contacts 300a, 300a', 300b, 300b' contacting the sources.

[0103] Thus, in view of the different embodiments described above, the invention makes it possible to manufacture vertical devices based on GaN, in particular transistors and diodes, without using GaN substrate, which is expensive and often only available in small dimensions.

[0104] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Demands

1. A method for manufacturing at least one microelectronic device (1a, 1b, 2a, 2b) comprising the following steps: • providing a substrate (10) having a top face (H), • performing localized gallium nitride (GaN) epitaxy on the top face (11) of the substrate (10), so as to form at least one GaN-based island (100a, 100b), each island (100a, 100b) having a face, called the bottom face (102a, 102b), facing the top face (11) of the substrate (10), each island (100a, 100b) comprising a GaN-based migration layer (130a, 130b), the migration layer (130a, 130b) having a bottom face (132a, 132b) facing the top face (11) of the substrate (10) and an upper face (131a, 131b) opposite the lower face (132), • at the level of each island (100a, 100b), form a first layer (110a,110b) based on GaN doped with a first type taken from an n-type doping and a p-type doping, the first layer (110a, 110b) forming a plurality of doped wells separated from each other and each extending from the upper face (131a, 131b) of the migration layer (130a, 130b), • forming an electrically conductive layer (400) forming a drain, the drain (400) being electrically connected to the lower face (102a, 102b) of each island (100a, 100b), thus forming at least one vertical transistor (1a, 1b).

2. A manufacturing method according to the preceding claim in which the substrate (10) is silicon-based.

3. A manufacturing method according to any one of the preceding claims wherein each island (100a, 100b) has a height hiOo greater than or equal to 10 pm, preferably greater than or equal to 20 pm, hioo being measured in a direction perpendicular to a plane (XY) in which the upper face (11) of the substrate (10) extends mainly.

4. A manufacturing method according to any one of the preceding claims wherein the drain formation step (400) comprises the following steps: • after forming at least one island (100a, 100b), remove the substrate (10), then • form the drain (400) against the underside (102a, 102b) of at least one island (100a, 100b).

5. A manufacturing method according to any one of claims 1 to 3 wherein the drain (400) formation step comprises the following steps: • for each island (100a, 100b), forming at least one metallic interconnection through the substrate (10) and opening onto said island (100a, 100b), • forming the drain (400) against a lower face (12) of the substrate (10) opposite its upper face (11), the drain (400) being in contact with at least one metallic interconnection.

6. A manufacturing method according to any one of the preceding claims wherein the step of forming the first layer (110a, 110b) comprises the following steps: • at each island (100a, 100b), forming in the migration layer (130a, 130b) at least one opening (20, 20') extending from the upper face (131a, 131b) of the migration layer (130a, 130b), • at each island (100a, 100b), forming the first layer (110a, 110b) in each of the openings (20, 20') in the migration layer (130a, 130b) of the island (100a, 100b), the first layer (110a, 110b) thus forming the plurality of doped wells.

7. A manufacturing method according to any one of claims 1 to 5, wherein the step of forming the first layer (110a, 110b) comprises the following steps: • at each island (100a, 100b), forming on the migration layer (130a, 130b) a continuous layer of doped GaN of the first type, • at the level of each island (100a, 100b), form in the continuous layer of GaN secondary openings separated from each other and crossing entirely said continuous layer of doped GaN, so as to partially update the migration layer (130a, 130b), the remaining portions of the continuous layer forming the first layer (110a, 110b), • at the level of each island (100a, 100b), grow by epitaxy the migration layer (130a, 130b) in the secondary openings.

8. A method for manufacturing at least one vertical transistor (2a, 2b) implementing the method according to any one of the preceding claims, further comprising the following steps: • at each island (100a, 100b), partially implanting the first layer (110a, 110b) so as to form at least one pair of regions, called sources (120a, 120a', 120b, 120b'), doped with the other type of doping, either n-type or p-type doping, the sources of each pair of sources (120a, 120a'; 120b, 120b') being located in separate doped wells, • forming at least one electrically conductive motif called a gate (200a, 200a', 200b, 200b') in contact with the two sources of each pair of sources (120a, 120a' ; 120b, 120b'), • form an electrically conductive contact called source contact (300a, 300a', 300b, 300b') at the contact of each source of the same pair of sources (120a, 120a' ; 120b, 120b').

9. A method according to the preceding claim wherein the first layer (110a, 110b) forms at least three doped wells and wherein at least two pairs of sources (120a, 120a'; 120b, 120b') are formed in these at least three doped wells, two sources belonging to distinct source pairs being formed in the same doped well.

10. A method according to the preceding claim wherein the source contacts (300a, 300a'; 300b, 300b') in contact with the sources (120a, 120a', 120b, 120b') formed in the same doped well are in electrical continuity and form a common source contact for the two transistors (2a, 2b).

11. A manufacturing method according to any one of claims 8 to 10 in their relation to claim 4 wherein the substrate removal step (10) is carried out before the formation of the source contact (300a, 300a', 300b, 300b'), optionally before the formation of the grid (200a, 200a', 200b, 200b'), optionally before the implantation and formation step of the sources (120a, 120a', 120b, 120b').

12. A manufacturing method according to any one of claims 8 to 10 in their relation to claim 4 wherein the substrate removal step (10) is carried out after the implantation and source formation step (120a, 120a', 120b, 120b'), optionally after the grid formation (200a, 200a', 200b, 200b'), optionally after the source contact formation (300a, 300a', 300b, 300b').

13. A method for manufacturing at least one diode (la, 1b) implementing the method according to any one of claims 1 to 7, further comprising the following step: • forming an electrically conductive motif called an anode (500) in contact with at least two doped wells, preferably with all the doped wells.

14. A manufacturing method according to the preceding claim in its relation to claim 4 in which the step of removing the substrate (10) is carried out before the formation of the anode (500).

15. A manufacturing method according to any one of the two preceding claims in their relation to claim 4 wherein the substrate removal step (10) is carried out after the formation of the anode (500).

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