Quantum device and fabrication process

Abstract

Title: Quantum Device and Method of Implementation The invention relates to a quantum device comprising an active region (12A) extending along a longitudinal direction (y), and QD grids (G11, G12) extending along a transverse direction (x), said QD grids (G11, G12) being arranged opposite each other on either side of the active region (12A) to control a quantum dot. Advantageously, the device comprises transverse grids (GT), each arranged on a pair of opposite QD grids (G11, G12), and separated from said QD grids (G11, G12) and the active region (12A) by a grid dielectric (21). Each transverse grid (GT) is configured to control a transverse tunnel barrier between the QD grids (G11, G12). Figure for the abstract: Fig. 8

Description

Title of the invention: Quantum device and method of implementation technical field

[0001] The present invention relates to the field of microelectronics and quantum electronics in particular. For example, it finds a particularly advantageous application in the realization of quantum devices with quantum bits (called quantum bits or qubits), especially spin qubit devices. PRIOR TECHNOLOGY

[0002] A spin-qubit quantum device typically comprises an active region, for example in the form of a nanowire or nanostrip, where the quantum dots are formed, and control grids associated with the quantum dots. The control grids typically confine the elementary charges to the quantum dots, forming an electrostatic potential well in the active region.

[0003] Spin qubit quantum devices are generally based on a bilinear network architecture of quantum dots. Such an architecture allows both the control and state detection of these quantum dots.

[0004] The first row of the quantum dot lattice can be dedicated to defining the qubits themselves, while the second row of the lattice can be used to form quantum dots for reading the qubits. Sub-lattices of a few qubits can also be formed using this bilinear lattice architecture.

[0005] To ensure reliable confinement at each quantum point, control grids for the tunneling coupling between quantum points can be intercalated. So-called longitudinal grids can be intercalated between the quantum points of the same line, to control the tunneling barriers between quantum points along the longitudinal direction, that is to say along the line of quantum points.

[0006] Document FR3120740A1 further discloses a "transverse" grid, which allows for the control of tunneling barriers between quantum dots opposite the two lines of the bilinear lattice, in the transverse direction, i.e., perpendicular to the lines of quantum dots. This transverse grid extends longitudinally above the active region and allows for the decoupling of the first and second lines of quantum dots. This transverse decoupling is not optimal. This can prove problematic for the control of the qubits or for the compensation of local disorder.

[0007] There is therefore a need for new quantum device architectures allowing improved control of qubits, and better management of tunneling coupling.

[0008] One objective of the invention is to meet this need, and to overcome at least partially the disadvantages of known solutions.

[0009] In particular, one object of the invention is a quantum device enabling improved transverse tunneling control. Another object of the invention is a method for implementing such a device.

[0010] The other objects, features and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0011] To achieve this objective, according to one embodiment, a quantum device is provided comprising successively, stacked along a direction z: - a support layer, - an insulating layer and - an active zone extending mainly along a longitudinal direction, - first control grids called QDs, extending mainly in a transverse direction with respect to the active zone, said first QD grids being arranged on either side of the active zone, opposite each other, each first QD grid being configured to control a potential well in the active zone, said potential well defining a quantum point.

[0012] Advantageously, the device further comprises transverse control grids, extending mainly in the transverse direction, each transverse grid being arranged on two first QD grids opposite each other forming a pair of first QD grids, and separated from said first QD grids and the active zone by a first grid dielectric, each transverse grid being configured to control a transverse tunnel barrier between the first QD grids of said pair of first QD grids.

[0013] Thus, the transverse tunneling barrier is controlled locally between two quantum points of each pair of opposite quantum points. The quantum points arranged in a line on one side of the active region are individually decoupled from the quantum points arranged opposite each other on the other side of the active region. The transverse grids, which extend transversely above the first QD grids, advantageously allow local and individual control of the tunneling coupling between two opposite quantum points on either side of the active region.

[0014] Another aspect of the invention relates to a method for making such a device, comprising - A supply of a stack comprising, along the z-direction, a support layer, an insulating layer and a semiconductor layer, - The formation of a first lithography mask on the semiconductor layer, configured to define the active area in the semiconductor layer, - An etching of the semiconductor layer, configured to form the active area, said etching exposing edges of said active area, - The formation of a first dielectric barrier on each exposed edge of the active zone, - A deposit of a first grid layer on either side of the first lithography mask, against the first dielectric barrier bordering the active zone, said first grid layer being interrupted by the first lithography mask and intended to form the first QD grids on either side of the active zone, - Removal of the first lithography mask, - A continuous deposition of a first dielectric material on the first grid layer and above the active zone, intended to form the first grid dielectric, - A deposit of a second grid layer on the first dielectric material, said second grid layer being intended to form the transverse grids, - The formation of a second lithography mask on the second grid layer, configured to define the transverse grids and pairs of first QD grids beneath the transverse grids, - An etching along the z direction of the second grid layer, the first dielectric material, and the first grid layer, so as to form the transverse grids, the first grid dielectric, and the first QD grid pairs under each transverse grid, the transverse grids being self-aligned with the first QD grid pairs they surmount.

[0015] Advantageously, this method allows the transverse grids to be self-aligned with the first QD grids. Each pair of first QD grids facing each other in the transverse direction is surmounted by a self-aligned transverse grid. The width dimensions of the transverse grids are typically identical to the width dimensions of the first QD grids they surmount. This precise dimensional control improves the electrostatic control in the device. quantum. The confinement of charges and / or the decoupling of charges between quantum points is thus improved. BRIEF DESCRIPTION OF THE FIGURES

[0016] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0017] [Fig.1A] Fig.1A schematically illustrates in cross-section a quantum device, according to a first embodiment of the present invention.

[0018] [Fig.1B] Fig.1B schematically illustrates in cross-section a quantum device, according to a variant of the first embodiment of the present invention.

[0019] [Fig.2] Fig.2 schematically illustrates in perspective a manufacturing step of a quantum device, according to an embodiment of the present invention.

[0020] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.6A] [Fig.7A] Figures 3A to 7A schematically illustrate in cross-section the manufacturing steps of a quantum device, according to the first embodiment of the present invention.

[0021] [Fig.3B] [Fig.4B] [Fig.5B] [Fig.6B] [Fig.7B] Figures 3B to 7B schematically illustrate in cross-section the manufacturing steps of a quantum device, according to the variant of the first embodiment of the present invention.

[0022] [Fig.8] [Fig.9] [Fig. 10] Figures 8, 9, 10 schematically illustrate in perspective the manufacturing steps of a quantum device, according to an embodiment of the present invention.

[0023] [Fig. 11 A] [Fig.llB] [Fig.llC] [Fig.llD] Figures 11A, 11B, 11C, 11D illustrate schematically in perspective of the sections of the quantum device illustrated in [Fig. 10], according to an embodiment of the present invention.

[0024] [Fig.12] [Fig.13] [Fig.14] [Fig.15] [Fig.16] [Fig.17] [Fig.l8A] [Fig.l8B] [Fig.19] Figures 12 to 19 schematically illustrate in perspective the manufacturing steps of a quantum device, according to a second embodiment of the present invention.

[0025] [Fig. 20A] [Fig. 20B] Figures 20A and 20B schematically illustrate in perspective sections of the quantum device illustrated in [Fig.19], according to a second embodiment of the present invention.

[0026] The drawings are given as examples and are not limiting of the invention. These are schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the various layers, patterns, and reliefs are not representative of reality. For clarity, all alphanumeric references is not systematically repeated from one figure to another. It is understood that elements already described and referenced, when reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0027] Before proceeding to a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0028] According to one example, each transverse grid is superimposed on the first pair of grids QD, along the z direction.

[0029] According to one example, the first QD grids partially cover the active area. This improves the electrostatic control of the QDs.

[0030] According to an alternative example, the first QD grids do not cover the active area.

[0031] According to one example, each transverse grid has a width dimension substantially equal to the width dimensions of the first QD grids of the pair of first QD grids that it surmounts, the width dimensions of the transverse grid and the first QD grids being taken along the longitudinal direction. The transverse grids are substantially overlapped over at least part of the length of the first QD grids, along the transverse direction. Dimensional control between the first QD grids and the transverse grids is improved. This allows for more precise electrostatic control. The transverse tunnel barriers can be controlled with greater precision.

[0032] According to one example, the device further comprises second QD grids intercalated between the first QD grids in the longitudinal direction y, such that two second QD grids arranged opposite each other on either side of the active area form a pair of second QD grids.

[0033] According to one example, the second grids QD do not cover the active area.

[0034] According to one example, the device further comprises so-called control grids longitudinal grids extending primarily in the transverse direction, each longitudinal grid being sandwiched between a first transverse grid above a first pair of first QD grids, and a second transverse grid above a second pair of first QD grids. Each longitudinal grid is positioned on a pair of second QD grids, and separated from said second QD grids, the transverse grids, and the active zone by a second grid dielectric. Each longitudinal grid is configured to control a longitudinal tunnel barrier and / or diagonal between the first QD grids of the first pair of QD grids and the first QD grids of the second pair of QD grids. The first and second QD grids are typically alternated along the longitudinal direction. The longitudinal grids are arranged on the second pairs of QD grids, typically at a "second floor" of grids. The longitudinal grids of this second floor control, among other things, the diagonal tunnel barriers between the first pairs of QD grids. The second pairs of QD grids, at the "first floor" of grids, control, among other things, the longitudinal tunnel barriers between the first pairs of QD grids.

[0035] According to one example, the transverse grids and the longitudinal grids are arranged alternately along the active area, that is to say in the longitudinal direction.

[0036] According to one example, each longitudinal grid surmounts a pair of opposing second grids QD and is superimposed on said pair of second grids QD, along the z-direction. According to one example, the number of first grids QD is equal to twice the number of transverse grids. According to one example, the number of pairs of first grids QD is equal to the number of transverse grids. According to one example, the number of second grids QD is equal to twice the number of longitudinal grids. According to one example, the number of pairs of second grids QD is equal to the number of longitudinal grids.

[0037] According to one example, each longitudinal grid has a width dimension substantially equal to the width dimensions of the second QD grids of the pair of second QD grids surmounted by said longitudinal grid, the width dimensions of the longitudinal grid and the second QD grids being taken along the longitudinal direction. Dimensional control between the second QD grids and the longitudinal grids is improved. This allows for more precise electrostatic control. The longitudinal tunnel barriers can be controlled with greater precision. The longitudinal grids are substantially overlapped over at least part of the length of the second QD grids, along the transverse direction.

[0038] According to one example, the transverse grids each have a first width dimension and the longitudinal grids each have a second width dimension, said first and second width dimensions being taken along the longitudinal direction, and the second width dimension is different from the first width dimension. For example, the second width dimension is strictly greater than the first width dimension, or vice versa.

[0039] According to one example, the first and second gate dielectrics have first and second thicknesses respectively taken along the z-direction, and the second thickness is different from the first thickness. For example, the second thickness is strictly greater than the first thickness, or vice versa.

[0040] According to one example, each transverse grid has a portion, typically a central portion, relatively thicker, projecting towards the active area, so that said portion is brought closer to the active area.

[0041] According to an example, each transverse grid has a length less than the sum of the lengths of the first QD grids that it covers, the lengths being taken along the transverse direction x.

[0042] According to one example, the transverse grids are shorter than the pairs of first QD grids, along the transverse direction. The transverse grids are typically arranged in a stepped pattern on the pairs of first QD grids. Thus, a portion of each first QD grid forming the pair of first QD grids is not covered by the transverse grid. This allows electrical contact to be made with the first QD grids via a through-via, directly above each first QD grid.

[0043] In one example, the device further comprises at least one charge reservoir connected to the active region, said charges being intended to power the quantum dots of the device. In another example, the device comprises at least two charge reservoirs, arranged on either side of the active region.

[0044] According to one example, the longitudinal grids are shorter than the pairs of second QD grids in the transverse direction. The longitudinal grids are typically arranged in a stepped pattern on the pairs of second QD grids. Thus, a portion of each second QD grid forming the pair of second QD grids is not covered by the longitudinal grid. This allows electrical contact to be made with the second QD grids via a through-through, directly above each second QD grid.

[0045] According to one example, the longitudinal grids do not cover the active area.

[0046] According to one example, the first lithography mask is placed over a layer based on a material with a high dielectric constant. According to another example, the first lithography mask is SiN-based.

[0047] According to one example, before the deposition of the first grid layer, the first lithography mask is partially etched, selectively to the layer based on the high dielectric constant material, so as to expose parts of the layer based on the high dielectric constant material above the active area, so that the first QD grids formed from the first grid layer partially cover the active area.

[0048] According to one example, the method further comprises, after the formation of transverse grids surmounting pairs of first grids QD, - A deposit of a second dielectric barrier covering exposed flanks of the first QD grids and transverse grids, - A deposit of a third grid layer on either side of the active zone, between the first QD grids, said third grid layer being intended to form second QD grids on either side of the active zone, - A deposit of a second dielectric material on the third grid layer, intended to form a second grid dielectric, - A deposit of a fourth grid layer on the second dielectric material, between the transverse grids, said fourth grid layer being intended to form longitudinal grids, each longitudinal grid being arranged on a pair of second QD grids opposite each other, on either side of the active zone, the longitudinal grids being self-aligned with the pairs of second QD grids they surmount.

[0049] Advantageously, the method allows the formation of self-aligned transverse grids on pairs of first QD grids, and self-aligned longitudinal grids on pairs of second QD grids. This provides excellent dimensional control between the different types of grids. The electrostatic control of the quantum device is improved.

[0050] According to one example, the method further comprises, after the formation of the transverse grids and / or longitudinal grids: - A formation of a third lithography mask comprising openings directly above the transverse grids and / or the longitudinal grids on the side of one end of the first QD grids and / or the second QD grids opposite the active area, - A partial removal of the transverse grids and / or longitudinal grids through said openings, so as to expose part of the first QD grids and / or the second QD grids.

[0051] This allows the formation of transverse grids and / or stepped longitudinal grids on the first QD grids and / or the second QD grids, respectively. Electrical contact re-establishment on the first QD grids and / or the second QD grids is facilitated. Typically, through-vias are formed directly above the first QD grids and / or the second QD grids.

[0052] Except in cases of incompatibility, it is understood that all the above optional features can be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example, the device or the method, can be adapted mutatis mutandis to the other aspect of the invention.

[0053] The invention relates generally to a quantum device comprising a plurality of transverse grids, and to a method for manufacturing such a device. The multiplicity of transverse grids allows for the local control of transverse quantum barriers between two QD grids of a pair of opposing QD grids. The control of tunneling coupling between QD grids along the transverse direction is thus performed "individually," and not collectively as is the case in known devices. The device's control capabilities are increased. Preferably, the device also comprises a plurality of longitudinal grids. The multiplicity of longitudinal grids allows for the local control of longitudinal quantum barriers between different pairs of adjacent QD grids. The control of tunneling coupling between QD grids along the longitudinal direction is also performed "individually."The device according to the invention, which typically features a bilinear quantum dot network architecture, can therefore be controlled with greater precision and in an improved manner.

[0054] In the quantum device, the charge carrier distribution is localized at the level of a quantum dot or quantum dot. Quantum dots are typically formed by electrostatic confinement (via the application of a voltage on the gates) and structural confinement (in the thin layer of topSi forming the active region, typically).

[0055] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0056] The term "opposite" grids means grids aligned along the transverse direction, at least partially or totally with each other.

[0057] A substrate, film, or layer "based" on a material A is understood to mean a substrate, film, or layer comprising only that material A or that material A and possibly other materials, for example dopant elements or alloying elements.

[0058] Several embodiments of the invention implementing successive steps of the manufacturing process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, although this is generally preferred, that the steps follow each other immediately; intermediate steps may separate them.

[0059] Furthermore, the term "step" refers to the execution of a part of the process, and can designate a set of sub-steps.

[0060] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may, in particular, be followed by actions related to a different step, and other actions from the first step may be repeated later. Thus, the term "step" does not necessarily imply unitary actions that are inseparable in time and in the sequence of phases of the process.

[0061] Selective etching with respect to or etching with selectivity with respect to means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching speed of material A greater than the etching speed of material B. Selectivity is the ratio of the etching speed of material A to the etching speed of material B. It is denoted SA:B. A selectivity SA:B of 10:1 means that the etching speed of material A is 10 times greater than the etching speed of material B.

[0062] A preferably orthonormal coordinate system, comprising the x, y, and z axes, is shown in the accompanying figures. When only one coordinate system is shown on a single sheet of figures, that system applies to all the figures on that sheet. The transverse direction is oriented along the x-axis. The longitudinal direction is oriented along the y-axis.

[0063] In this patent application, the term thickness will preferably be used for a layer or film, and height for a device or structure. The thickness is measured in a direction normal to the principal plane of extension of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along the z-axis. A grid pattern formed on such a surface layer has a height along the z-axis. The relative terms "on," "above," "under," and "below" refer to positions measured along the z-axis.

[0064] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically on the cross-sectional figures.

[0065] The terms "approximately", "around", "in the order of" mean to the nearest 10%, and preferably to the nearest 5%. Furthermore, the terms "between ... and ..." and equivalents mean that the bounds are inclusive, unless otherwise stated.

[0066] Fig. 1A schematically illustrates in cross-section a quantum device according to a first embodiment.

[0067] This device typically comprises a support portion 10, typically a bulk silicon substrate, an electrically insulating layer 11, typically a buried oxide layer called a "BOX", and an active area 12A, by Example from a silicon layer called topSi. This stack can be formed from a SOI (silicon on insulator) type substrate.

[0068] The active region 12A is intended to accommodate quantum dots QD1, QD2, typically at the boundary of the active region 12A. The active region 12A typically has a thickness on the order of 5 nm to 20 nm. This allows the quantum dots QD1, QD2 to be structurally confined along z.

[0069] The device further comprises grids G11, G12 configured to confine and electrostatically control the quantum dots QD1, QD2, respectively. The grids G11, G12 are typically arranged opposite each other along x, on either side of the active region 12A. They are separated from the active region 12A by a dielectric barrier 14f.

[0070] The device further advantageously comprises a transverse grid GT covering the grids G11, G12, and the active zone 12A. The transverse grid GT is continuous along the x-axis. It typically has a projecting portion GTA near the active zone 12A, separated from the active zone 12A by an oxide layer 14 and by the first dielectric 21. This portion GTA is typically located at the center of the transverse grid GT along the x-axis, substantially vertically above the active zone 12A. The first dielectric 21 also separates the transverse grid GT from the grids G11 and G12.

[0071] By polarizing the transverse grid GT, it is possible to form and control a so-called transverse tunnel barrier between the quantum points QD1, QD2, within the active region 12A. This prevents tunneling coupling from occurring along x, between the quantum points QD1, QD2.

[0072] According to a variant illustrated in [Fig. 1B], the grids G11 and G12 respectively have portions G110 and G120 extending above and partially covering the active region 12A. They are typically separated from the active region 12A by the oxide layer 14. These portions G110 and G120 allow, in particular, for improved electrostatic control of the quantum dots QD1 and QD2. According to this example, the transverse grid GT also includes a projecting portion approaching the active region 12A, between the grids G11 and G12.

[0073] In Figures IA, IB, only a pair of grids G11, G12 and a transverse grid GT are shown. The device typically comprises a plurality of pairs of grids G11, G12 regularly distributed along the longitudinal y direction, and a plurality of transverse grids GT surmounting the pairs of grids G11, G12.

[0074] As illustrated in [Fig. 2], after lithography / etching of a first etching mask 13B defining a pattern including the active area 12A of the device, an anisotropic dry etch along z is performed. The etch is stopped on the insulating layer 11 (BOX). A reactive ion etch (RIE) or an etch Fluorocarbon-based plasma can be used to etch the underlying layers of the stack, down to the BOX.

[0075] Figures 3A and 3B illustrate two variants of the formation of the first etching mask 13B, ultimately enabling the fabrication of the devices shown in Figures IA and 1B, respectively. Preferably, before the formation of the first hard mask 13B and before etching layer 12, thermal oxidation is performed on the surface of layer 12 to form the oxide layer 14. An optional layer 13A, based on a material with a high dielectric constant, is then deposited. The first etching mask 13B is then formed by lithography / etching on the stack of layers 12, 14, and 13A. It may be SiN-based.

[0076] According to the embodiment illustrated in [Fig.3A], after etching layers 13A, 14 and 12 to form the active area 12A, the first etching mask 13B is simply retained.

[0077] According to the embodiment illustrated in [Fig. 3B], after etching layers 13A, 14, and 12 to form the active area 12A, the first etching mask 13B is partially etched. In particular, the first SiN-based etching mask 13B is isotropically etched selectively to the underlying layers 12A, 13A, and 14. This reduces the x- and z-dimensions of the first etching mask 13B.

[0078] After etching, the edges 120 of the active area 12A are exposed. As illustrated in Figures 4A and 4B, thermal oxidation is first carried out to form a first dielectric barrier 14f on each exposed edge 120 of the active area 12A. A first layer of grid G10 is then deposited on either side of the first etching mask 13B, for example by chemical vapor deposition (CVD). This deposit is typically conformal and covers the first etching mask 13B. A planarization step, typically by chemical mechano-polishing (CMP), is then performed. This planarization step aims to remove the first layer of grid G10 over the first etching mask 13B. The CMP polishing is configured to stop at the first etching mask 13B. After deposition and / or planarization, the first grid layer G10 is interrupted by the first etching mask 13B, along the transverse direction x.The first G10 grid layer is preferably made of polycrystalline silicon.

[0079] As illustrated in figures 5A, 5B, after deposition and / or planarization of the first grid layer G10, the first etching mask 13B is selectively removed from layer 13A and from the first grid layer G10.

[0080] As illustrated in Figures 6A, 6B, the first gate dielectric 21 is formed by conformal deposition of a continuous layer based on a first dielectric material onto the first gate layer G10 and onto layer 13A. The first gate dielectric 21 can have a thickness on the order of a few nanometers to a few tens of nanometers. It can be SiO2 based.

[0081] As illustrated in Figures 7A, 7B, a second gate layer G20 is then deposited onto the first gate dielectric 21. The cavity above the active region 12A is thus filled by the second gate layer G20. A planarization step by CMP is preferably also performed. The second gate layer G20 is typically based on polycrystalline silicon.

[0082] As illustrated in [Fig. 8], the stacking of the G10, G21, and G20 layers is then structured conventionally by lithography and etching to form the superimposed G11, G12, and GT grids. The formation of the G11, G12, and GT grids is advantageously achieved through a single etching or series of etchings. This reduces the number of lithography steps. It also results in "self-aligned" G11, G12, and GT grids, exhibiting substantially the same width along the y-axis. Dimensional control is optimized. Electrostatic control via the G11, G12, and GT grids is more precise.

[0083] The grids G11, G12 and the grids GT extend mainly along the x direction, transversely to the active zone 12A, which extends mainly along the y direction. The grids GT are superimposed on the grids G11, G12 and overlap the active zone 12A located between the grids G11, G12. The device advantageously comprises a plurality of grids GT allowing local control of a transverse tunnel barrier between the facing grids G11, G12.

[0084] According to one possibility, source and drain regions, or reservoirs for quantum devices, are formed at each end of the active region 12A, for example by epitaxy on either side of the active region along the x-axis. These source and drain regions can be doped in situ during epitaxy. They can be based on phosphorus-doped silicon (Si:P), for example. The fabrication of the reservoirs and / or the source and drain regions is known to those skilled in the art.

[0085] As illustrated in [Fig. 9], a mask 30 comprising openings 31 is then formed on the GT grids. The openings 31 are located on either side of the active area 12A, at the free ends of the G11, G12 grids. A portion of the GT grids is then etched through the openings 31, so as to expose the underlying G11, G12 grids. This allows for the formation of stepped G11, G12, and GT grids. Contact with the G11, G12 grids is thus facilitated.

[0086] Figure 10 illustrates the device after encapsulation by the encapsulation layer 40 and formation of the various electrical contacts. Vias V11 are formed above the grids G11, on the parts of the grids G11 not covered by the grids GT. Vias VT are formed above the grids GT. Vias VA are formed above the active area 12A, at each end along the y direction. Vias V12 are formed directly above the G12 grids, on the parts of the G12 grids not covered by the GT grids.

[0087] Figures 11A-11D show various cross-sections, along xz planes, and longitudinal sections, along zy planes, of the device illustrated in [Fig. 10]. The stepped grids G11, G12, and GT, and the respective vias VI1, V12, and VT are visible (in particular [Fig. 1IA]). The vias VA contacting the active zone 12A are also visible (in particular [Fig. 11C]).

[0088] Figures 12 to 18A illustrate different stages of the device's realization, according to a second embodiment. The stages illustrated in these Figures 12 to 18A are typically carried out after etching and defining the grids G11, G12, and GT, as illustrated in [Fig. 8]. They aim to form interleaving grids between each set of superimposed G11, G12, and GT grids, along the longitudinal direction y. These additional interleaving grids are specifically designed to control tunneling coupling between G11 grids, and / or between G12 grids, and / or between GT grids, along the longitudinal direction y.

[0089] As illustrated in [Fig. 12], the oxide layer 14 is preserved or reformed on the active area 12A. The grid patterns M1 comprising the grids G11, G12, GT extend along x. The pattern MA comprising the active area 12A extends along y.

[0090] As illustrated in [Fig.13], an oxide layer 15 is deposited to form a dielectric barrier on the exposed parts of the grids G11, G12, GT, in particular on the sides of the grids G11, G12, GT and on the tops of the grids GT.

[0091] As illustrated in [Fig. 14], a third G30 gate layer is then deposited onto the oxide layer 15. To expose the M1, MA motifs, a CMP planarization step can first be performed. Partial etching of the third G30 gate layer can also be carried out. The third G30 gate layer can be based on polycrystalline silicon. Optionally, re-epitaxial etching can be performed after the partial etching to adjust the overlap of the edges of the active area 12A by the third G30 gate layer. Following these steps, the third G30 gate layer is interrupted by the M1, MA motifs, which are partially exposed.

[0092] As illustrated in [Fig. 15], the second gate dielectric 22 is formed by conformal deposition of a continuous layer based on a second dielectric material on the third gate layer G30 and on the motifs M1, MA.

[0093] As illustrated in [Fig. 16], a fourth gate layer G40 is then deposited onto the second gate dielectric 22. The fourth gate layer G40 is typically based on polycrystalline silicon. A CMP planarization step is preferably performed to expose the vertices of the ML A motifs As a result of these steps, the fourth layer of grid G40 is interrupted by the Ml patterns.

[0094] As illustrated in [Fig. 17], the stacking of layers G40, 22, G30 is then structured conventionally by lithography and etching to form the grids G21, G22 and the superimposed GL grids. The grids G21, G22, GL are advantageously formed between the grids G11, G12, GT, along the y direction. The grid spacing along y can thus be halved.

[0095] The formation of the G21, G22, and GL grids is advantageously achieved by a single etching or series of etches around the mask 23. This reduces the number of lithography steps. It also allows for the production of "self-aligned" G21, G22, and GL grids, exhibiting substantially the same width along the y-axis. Dimensional control is optimized. Electrostatic control via the G21, G22, and GL grids is more precise.

[0096] The device obtained after removal of the mask 23 is illustrated in [Fig. 18A]. The grids G21, G22, GL do not necessarily have the same width along y as the grids G11, G12, GT. The heights along z of the different grids G11, G12, GT, G21, G22, GL are not necessarily identical. The relative positioning along z of the grids G11, G12, GT and of the grids G21, G22, GL may vary. The thicknesses of the first and second grid dielectrics 21, 22 are not necessarily identical. Typically, the sum of the thicknesses of the grids or layers G12, 21, GT, 15, 22 is equal to the sum of the thicknesses of the grids or layers 15, G22, 22, GL.

[0097] Each set of superimposed G21, G22, GL grids extends primarily along the x-direction between two sets of superimposed G11, G12, GT grids. The device advantageously comprises a plurality of GL grids enabling local control of a longitudinal and / or diagonal tunnel barrier between two adjacent sets of superimposed G11, G12, GT grids. Similar to the GT grids, the GL grids typically have a projecting GLA portion near the active zone 12A, separated from the active zone 12A by the oxide layer 14 and the second dielectric 22. This GLA portion is typically located at the center of each transverse GL grid along the x-direction, substantially vertically above the active zone 12A.

[0098] As illustrated in [Fig.18B], according to a particular operating possibility, the GTA portions of the transverse grids GT control transverse tunnel barriers (represented by vertical arrows on [Fig.18B]) between the first facing grids, here between grids G11 and G12 and between grids G11' and G12'. The second grids G21 and G22 control longitudinal tunnel barriers (represented by horizontal arrows in [Fig. 18B]) between the first side-by-side grids, here between grids G11 and G11' and between grids G12 and G12'. The GLA portion of the longitudinal grid GL controls diagonal tunnel barriers. (represented by diagonal arrows in [Fig. 18B]) between the first grids, here between grids G11 and G12' and between grids G12 and GH'. The individual electrostatic control of the quantum points QD1, QD2, QD1', QD2' is thus advantageously improved.

[0099] At this stage, source and drain regions and / or charge reservoirs can be formed at the ends of the active zone. The GL and GT grids are preferably structured in a stepped fashion, as before. This structuring is advantageously achieved through a single mask, simultaneously for both the GL and GT grids.

[0100] Figure 19 illustrates the device after encapsulation by the encapsulation layer 40 and the formation of the various electrical contacts. Vias V11 are formed directly above the grids G11, on the portions of the G11 grids not covered by the GT grids, as before. Vias V21 are formed directly above the grids G21, on the portions of the G21 grids not covered by the GL grids. Vias VT are formed directly above the GT grids. Vias VA are formed directly above the active area 12A, at each end along the y direction. Vias VL are formed directly above the GL grids. Vias V12 are formed directly above the grids G12, on the portions of the G12 grids not covered by the GT grids, as before. V22 vias are formed directly above the G22 grids, on the parts of the G22 grids not covered by the GL grids.

[0101] Figures 20A and 20B show various cross-sections, along xz planes, and longitudinal sections, along zy planes, of the device illustrated in [Fig. 19]. The stepped grids G21, G22, and GL, and the respective vias V21, V22, and VL are visible ([Fig. 20A]). The alternation of grids G11 and G21 along y is also visible ([Fig. 20B]).

[0102] In view of the preceding description, it is clear that the proposed device and method offer a particularly efficient and versatile solution for controlling transverse and longitudinal tunneling coupling for a bilinear lattice quantum device. The invention is not limited to the embodiments described above. Other arrangements of quantum dots and / or tunnel barriers are possible, taking advantage of the functionalization of the different grids described above. The different grids are not necessarily perpendicular to the active region. The second grids are not necessarily present. The GL grids can extend substantially over the entire height of the first grids and the transverse grids. The GL grids can extend over the first and second grid layers, for example.

Claims

Demands

1. A quantum device comprising successively, stacked along a z-direction, • a support layer (10), • an insulating layer (11), and • an active zone (12A) extending mainly along a longitudinal direction (y), the device further comprising: • first control grids called QDs (G11, G12), extending mainly along a transverse direction (x) with respect to the active zone (12A), said first QD grids (G11, G12) being arranged on either side of the active zone (12A), opposite each other, each first QD grid being configured to control a potential well in the active zone (12A), said potential well defining a quantum point, the device being characterized in that it comprises • at least one control grid called transverse (GT), extending mainly along the transverse direction (x),at least one transverse grid (GT) being arranged on two opposing first QD grids forming a pair of first QD grids (G11, G12), and separated from said first QD grids (G11, G12) and the active zone (12A) by a first grid dielectric (21), each transverse grid (GT) being configured to control a transverse tunnel barrier between the first QD grids (G11, G12) of said pair of first QD grids.

2. Device according to the preceding claim in which the first QD grids (G11, G12) do not cover the active area (12A).

3. A device according to any one of the preceding claims, wherein each transverse grid (GT) has a width dimension substantially equal to the width dimensions of the first QD grids (G11, G12) of the pair of first QD grids surmounted by said transverse grid (GT), the width dimensions of the transverse grid (GT) and the first QD grids (G11, G12) being taken along the longitudinal direction (y).

4. Device according to any one of the preceding claims wherein each transverse grid (GT) has a portion (GTA), typically a central portion, relatively thicker protruding towards the active zone (12A), so that said portion (GTA) is brought closer to the active zone (12A).

5. Device according to any one of the preceding claims further comprising second QD grids (G21, G22) interposed between the first QD grids (G11, G12) in the longitudinal direction (y), such that two second QD grids arranged opposite each other on either side of the active area (12A) form a pair of second QD grids.

6. Device according to the preceding claim in which the second QD grids (G21, G22) do not cover the active area (12A).

7. A device according to any one of the two preceding claims further comprising longitudinal control grids (GL) extending principally in the transverse direction (x), each longitudinal grid (GL) being interposed between a first transverse grid (GT) surmounting a first pair of first QD grids (G11, G12), and a second transverse grid (GT) surmounting a second pair of first QD grids (G11, G12), each longitudinal grid (GL) being disposed at least partially on a pair of second QD grids (G21, G22), and separated from said second QD grids (G21, G22), the transverse grids (GT), and the active zone (12A) by a second grid dielectric (22), each longitudinal grid (GL) being configured to control a longitudinal and / or diagonal tunnel barrier between the first QD grids (G11, G12) of the first pair and the first QD grids (G11, G12). 11, G12) of the second pair.

8. Device according to the preceding claim in which the transverse grids (GT) and the longitudinal grids (GL) are arranged alternately along the active area (12A), i.e. in the longitudinal direction (y).

9. Device according to any one of claims 7 to 8 wherein each longitudinal grid (GL) has a width dimension substantially equal to the width dimensions of the second grids QD (G21, G22) of the pair of second grids QD which surmounts said longitudinal grid (GL), the width dimensions of the longitudinal grid (GL) and of the second grids QD (G21, G22) being taken along the longitudinal direction (y).

10. Device according to any one of claims 7 to 9 wherein the transverse grids (GT) each have a first width dimension and the longitudinal grids (GL) each have a second width dimension, said first and second width dimensions being taken along the longitudinal direction (y), and wherein the second width dimension is different from the first width dimension.

11. Device according to any one of claims 7 to 10 wherein the first and second grid dielectrics (21, 22) respectively have first and second thicknesses taken along the z direction, and wherein the second thickness is different from the first thickness.

12. Device according to any one of the preceding claims further comprising at least one charge reservoir connected to the active area (12A), said charges being intended to power the quantum dots of the device.

13. A method for implementing a quantum device according to any one of the preceding claims, said method comprising: • Providing a stack comprising, along the z-direction, a support layer (10), an insulating layer (11), and a semiconductor layer (12), • Forming a first lithography mask (13) on the semiconductor layer (12), configured to define the active region (12A) in the semiconductor layer (12), • Etching the semiconductor layer (12), configured to form the active region (12A), said etching exposing edges (120) of said active region (12A), • Forming a first dielectric barrier (14f) on each exposed edge (120) of the active region (12A),

14. • A deposit of a first grid layer (G 10) on one side and on the other side of the first lithography mask (13B), against the first dielectric barrier (141) bordering the active zone (12A), said first grid layer (G10) being interrupted by the first lithography mask (13B) and intended to form the first QD grids (G11, G12) on either side of the active zone (12A), • Removal of the first lithography mask (13B), • A continuous deposition of a first dielectric material on the first grid layer (G 10) and above the active area (12A), intended to form the first grid dielectric (21), • A deposit of a second grid layer (G20) on the first dielectric material, said second grid layer (G20) being intended to form the transverse grids (GT), • Formation of a second lithography mask on the second grid layer (G20), configured to define the transverse grids (GT) and pairs of first QD grids (G11, G12) under the transverse grids (GT), • An etching along the z direction of the second grid layer (G20), the first dielectric material, and the first grid layer (G10), so as to form the transverse grids (GT), the first grid dielectric (21) and the pairs of first QD grids (G11, G12) under each transverse grid (GT), the transverse grids (GT) being self-aligned with the pairs of first QD grids (G11, G12) that they surmount. A method according to the preceding claim, wherein the first lithography mask (13B) is placed on top of a layer (13A) based on a high dielectric constant material, and wherein, before the deposition of the first grid layer (G 10), the first lithography mask (13B) is partially etched, selectively, into the layer (13A) based on the high dielectric constant material, so as to expose portions of the layer (13A) based on the high dielectric constant material above the active area (12A), such that

15. The first QD grids (G11, G12) formed from the first grid layer (G10) partially cover the active zone (12A). A method according to any one of claims 13 to 14 further comprising, after the formation of transverse grids (GT) overlying pairs of first QD grids (G11, G12), • A deposit of a second dielectric barrier (15) covering exposed flanks of the first QD grids (G11, G12) and transverse grids (GT), • A deposit of a third grid layer (G30) on either side of the active zone (12A), between the first QD grids (G11, G12), said third grid layer (G30) being intended to form second QD grids (G21, G22) on either side of the active zone (12A), • A deposit of a second dielectric material on the third grid layer (G30), intended to form a second grid dielectric (22), • A deposit of a fourth grid layer (G40) on the second dielectric material, between the transverse grids (GT), said fourth grid layer (G40) being intended to form longitudinal grids (GL), each longitudinal grid (GL) being arranged on a pair of second QD grids (G21, G22) opposite each other, on either side of the active area (12A), the longitudinal grids (GL) being self-aligned with the pairs of second QD grids (G21, G22) that they surmount.