INTEGRATED CIRCUIT FOR "CAN" COMMUNICATION

Abstract

According to one aspect, an integrated circuit is proposed comprising: - a digital processing unit (MCU), - a transceiver circuit (TRC) configured to transmit data between the digital processing unit (MCU) and a Controller Area Network (CAN) data bus, the transceiver circuit (TRC) being configured to deliver differential signals, called CANH and CANL, in a dominant and a recessive mode, each transition of the differential signals CANH and CANL between the dominant and recessive modes being synchronized based on adaptation bits received by the transceiver circuit, - an adjustment circuit (ADPC) with at least one adaptation bit based on at least one comparison between the common mode of the differential signals CANH and CANL and at least one threshold voltage. Figure for the abstract: Figure 1

Description

Title of the invention: INTEGRATED CIRCUIT FOR "CAN" COMMUNICATION

[0001] Some embodiments and implementation methods relate to communication by “CAN” bus, abbreviation for the English “Controller Area Network”.

[0002] The CAN protocol is commonly used in motor vehicles for managing communications between various electronic devices, such as sensors, actuators, and control units. A CAN network is thus defined between these different electronic devices, which are connected to each other by a CAN bus. Each electronic device then forms a node of the CAN network.

[0003] A “CAN” bus has two wires configured to carry two signals, “CANH” (“CAN High”) and “CANL” (“CAN Low”), between nodes of the “CAN” network. The “CANH” and “CANL” signals are generated by a transmitter / receiver circuit of the various electronic devices of the “CAN” network.

[0004] A “CAN” bus can operate in a dominant mode or in a recessive mode.

[0005] In dominant mode, the potential difference between the "CANH" signal and the signal “CANL” is high. In particular, the “CANH” signal reaches a high level, on the order of 3.5V, and the “CANL” signal a low level, on the order of 1.5V.

[0006] In recessive mode, the levels of the “CANH” and “CANL” signals converge around 2.5V, thus reducing the potential difference.

[0007] However, a time lag may occur between the “CANH” and “CANL” signals during a change of operating mode.

[0008] This time lag can cause brief pulses (which may be referred to by the English term "glitches") on the common mode of the "CANH" and "CANL" signals. The common mode of the "CANH" and "CANL" signals corresponds to the voltage component common to the two signal lines with respect to a common reference point, for example, with respect to ground. The common mode can thus correspond to the average of the voltages of the "CANH" and "CANL" signals.

[0009] These brief pulses can cause disturbances in the operation of the CAN bus. For example, these disturbances can increase unwanted electromagnetic emissions (“EMI”) from the CAN bus. These electromagnetic emissions can affect nearby electronic circuits. Furthermore, these disturbances can be amplified by temperature.

[0010] There is therefore a need to propose a solution to improve communication in a "CAN" network by reducing disturbances which can in particular lead to undesirable electromagnetic emissions.

[0011] According to one aspect, an integrated circuit comprising: - a digital processing unit - specifically a microcontroller-, - a transmitter / receiver circuit configured to transmit data between the digital processing unit and a "Controller Area Network" data bus, "CAN", the transmitter / receiver circuit being configured to deliver differential signals, called "CANH" and "CANL", according to a dominant mode and a recessive mode, each transition of the differential signals "CANH" and "CANL" between the dominant mode and the recessive mode being synchronized from adaptation bits received by the transmitter / receiver circuit, - an adjustment circuit of at least one adaptation bit based on at least one comparison between the common mode of the differential signals "CANH" and "CANL" and at least one threshold voltage.

[0012] Such an adjustment circuit makes it possible to reduce common-mode interference between the "CANH" and "CANL" signals by adjusting the adaptation bits to better synchronize the "CANH" and "CANL" signals. Such an adjustment circuit thus makes it possible to limit unwanted electromagnetic ("EMI") emissions from the "CAN" bus resulting from common-mode interference between the "CANH" and "CANL" signals.

[0013] Furthermore, such an adjustment circuit has the advantage of not being affected by temperature changes. Indeed, such an adjustment circuit automatically adjusts itself during temperature drifts due to monitoring the common mode of the "CANL" and "CANH" signals.

[0014] In an advantageous embodiment, the adjustment circuit comprises: - a detection circuit configured to detect disturbances on the common mode of the differential signals "CANH" and "CANL", and - a processing circuit configured to adjust at least one adaptation bit when a common-mode disturbance is detected by the detection circuit.

[0015] Advantageously, the digital processing unit is configured to deliver a control signal indicating the mode of the "CANL" and "CANH" signals. The processing circuit is then configured to receive the control signal in order to adapt at least one adaptation bit associated with the transition to the mode of the "CANL" and "CANH" signals corresponding to the mode indicated by the control signal when a disturbance is detected by the detection circuit.

[0016] Preferably, the detection circuit is configured to receive the "CANH" and "CANL" signals and includes: - a first resistive element and a second resistive element connected in series and configured to receive the "CANL" and "CANH" signals in order to obtain the common mode of these signals "CANL" and "CANH" on a common node between the first resistive element and the second resistive element, - a third resistive element, a fourth resistive element and a current source connected in series between the common node of the first resistive element and the second resistive element and a reference node, in particular to ground, - a low-pass filter having an input connected to a common node between the third resistive element and the fourth resistive element so as to generate at the output a threshold voltage to monitor the common mode of the "CANH" and "CANL" signals, - a first comparator with a first input connected to the common node between the first resistive element and the second resistive element, and a second input connected to the output of the low-pass filter, - a second comparator with a first input connected to a common node between the fourth resistive element and the current source, and a second input connected to the output of the low-pass filter, - an adder circuit having two inputs connected respectively to the outputs of the first and second comparators, and one output connected to the processing circuit.

[0017] Such a detection circuit is simple and occupies little space in the integrated circuit.

[0018] Advantageously, the processing circuit comprises: - a first counter configured to be incremented each time disturbances are detected in the common mode by the detection circuit during a transition to the dominant mode, the value of the first counter defining at least one adaptation bit for the transition to the dominant mode, - a second counter configured to be incremented at each detection of disturbances on the common mode by the detection circuit during a transition to the recessive mode, the value of the second counter defining at least one adaptation bit for the transition to the recessive mode.

[0019] In an advantageous embodiment, the processing circuit includes an event monitoring circuit connected to the output of the detection circuit and configured to increment, at each disturbance detection, the first counter or the second counter according to the mode of the “CANH” and “CANL” signals indicated by the control signal delivered by the digital processing unit.

[0020] According to another aspect, an electronic device comprising an integrated circuit as described above is proposed. Such an electronic device can then be integrated into a CAN network.

[0021] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which:

[0022] [Fig.l] ;

[0023] [Fig.2] ;

[0024] [Fig.3] ;

[0025] [Fig.4] ;

[0026] [Fig.5] ; and

[0027] [Fig.6] illustrate embodiments and implementations of the invention.

[0028] Figure 1 illustrates an electronic device DIS configured to operate in a CAN network (short for Controller Area Network). The electronic device DIS can thus form a node of the CAN network. The electronic device DIS can, for example, be a component of an automobile (ECU, ABS unit, dashboard, etc.).

[0029] The electronic device DIS comprises an integrated circuit (IC). The integrated circuit includes a digital processing unit (MCU), for example a microcontroller (MCU), and a transceiver circuit (TRC) for performing CAN communication. In particular, the transceiver circuit (TRC) is configured to be connected to a CAN bus linking the various nodes of the CAN network.

[0030] In particular, the TRC transceiver circuit can operate in transmit mode. In this case, the transceiver circuit is configured to receive DAT data provided by the MCU digital processing unit in order to transmit it to the "CAN" bus.

[0031] The TRC transceiver circuit can operate in receive mode. In this case, the TRC transceiver circuit is configured to receive data from the "CAN" bus in order to transmit it to the MCU digital processing unit.

[0032] The TRC transceiver circuit is configured to control the "CANH" and "CANL" signals in either a dominant or recessive mode. The dominant and recessive modes are defined by the MCU digital processing unit, notably via a TX control signal.

[0033] Figure 2 illustrates the CANH and CANL signals in dominant mode D_M0D and recessive mode R_M0D. A shift in the CANH and CANL signals can cause disturbances in the common mode of the CANH and CANL signals. This shift can occur during the T_D, T_R transitions between dominant mode D_M0D and recessive mode R_M0D. These disturbances can cause unwanted electromagnetic emissions on the CAN bus.

[0034] The common mode of the “CANH” and “CANL” signals corresponds to the voltage component common to the two signal lines with respect to a reference point common, for example with respect to ground. The common mode can thus correspond to the average of the voltages of the "CANH" and "CANL" signals.

[0035] In order to define delays for the transitions of the "CANH" and "CANL" signals between dominant and recessive modes, the TRC transmitter / receiver circuit is configured to receive at least one TRM_R, TRM_D digital adaptation signal to adjust the transitions of the "CANH" and "CANL" signals. Specifically, a TRM_R digital signal can be used for the transitions of the "CANH" and "CANL" signals to recessive mode, and a TRM_D digital signal can be used for the transitions of the "CANH" and "CANL" signals to dominant mode. Each TRM_R, TRM_D digital adaptation signal can be delivered by the MCU digital processing unit. Each TRM_R, TRM_D digital adaptation signal has several adaptation bits. These adaptation bits can also be referred to as "trimming bits."These adaptation bits are used to adjust the edges of the "CANH" and "CANL" signals for transitions between dominant and recessive modes.

[0036] Each digital adaptation signal is taken into account by the transmitter-receiver circuit to make adjustments to the "CANH" and "CANL" signals in order to synchronize the voltage level transitions of the "CANH" and "CANL" signals. This adjustment can, for example, be performed by a timing circuit of the TRC transmitter / receiver circuit, configurable by the adaptation bits.

[0037] In particular, the integrated circuit also includes an ADPC bit-adjustment circuit.

[0038] The ADPC matching bit adjustment circuit is configured to adjust at least one matching bit, or more than one matching bit, to maintain the common mode of the CANH and CANL signals within an envelope. For example, the ADPC adjustment circuit is configured to adjust BTS_R matching bits of the TRM_R digital adjustment signal, and to adjust BTS_D matching bits of the TRM_D digital adjustment signal. The BTS_R matching bits can correspond to N least significant bits of the TRM_R digital adjustment signal. The BTS_D matching bits can correspond to N least significant bits of the TRM_D digital adjustment signal. The BTS_R and BTS_D matching bits can be transmitted to the digital processing unit, as illustrated, to modify the TRM_R and TRM_D digital adjustment signals. Alternatively, the matching bits can be transmitted directly to the TRC transmitter / receiver circuit.In this case, the digital processing unit can simply transmit K most significant bits of the TRM_D and TRM_R signals to the TRC transmitter / receiver circuit, K being equal to MN where M is the total number of adaptation bits of the TRM_R or TRM_D adaptation signal. These K bits. Adaptation values ​​can be stored in a non-volatile NVM memory that can be read by the MCU. In this case, the MCU can only transmit these K most significant bits to the TRC transmitter / receiver circuit, which combines them with the N least significant bits to form the TRM_R or TRM_D digital adaptation signal.

[0039] As illustrated in [Fig.3], in order to adjust the adaptation bits, the ADPC adjustment circuit includes a DETC disturbance detection circuit and a PRC processing circuit.

[0040] The DETC disturbance detection circuit is configured to receive as input the "CANH" and "CANL" signals delivered by the TRC transceiver circuit and to determine whether a timing adjustment is necessary by monitoring the common mode of the "CANH" and "CANL" signals. In particular, the ADPC disturbance detection circuit is configured to detect disturbances, including "glitches" in the common mode of the "CANH" and "CANL" signals.

[0041] The PRC processing circuit is configured to adjust the value of at least one adaptation bit when a correction of the synchronization of the "CANL" and "CANH" signals is required. More specifically, the PRC processing circuit is configured to adjust the adaptation bits when a disturbance is detected on the common mode of the "CANH" and "CANL" signals.

[0042] The PRC processing circuit is configured to determine whether it is necessary to correct for dominant or recessive mode. To do this, the PRC processing circuit is configured to receive the TX control signal. As previously mentioned, this TX control signal indicates whether the DIS electronic device is in dominant or recessive mode. This TX control signal is generated by the digital processing unit. For example, when TX is '0', the DIS electronic device is in dominant mode, and when TX is '1', the DIS electronic device is in recessive mode.

[0043] Thus, when the PRC processing circuit detects that a synchronization correction is required when the TX control signal indicates that the DIS electronic device is in a dominant mode, then this means that the synchronization correction of the “CANL” and “CANH” signals is required for the dominant mode.

[0044] Similarly, when the PRC processing circuit detects that a synchronization correction is required when the TX information signal indicates that the DIS electronic device is in a recessive mode, then this means that the synchronization correction of the “CANL” and “CANH” signals is required for the recessive mode.

[0045] Such an ADPC adjustment circuit makes it possible to reduce the disturbances on the common mode of the "CANH" and "CANL" signals by adjusting the adaptation bits in order to to better synchronize the "CANH" and "CANL" signals. The ADPC adjustment circuit thus makes it possible to limit unwanted electromagnetic ("EMI") emissions from the "CAN" bus resulting from disturbances on the common mode of the "CANH" and "CANL" signals.

[0046] Furthermore, the ADPC adjustment circuit has the advantage of not being affected by temperature changes. Indeed, the ADPC adjustment circuit adjusts itself automatically during temperature drifts due to monitoring the common mode of the "CANL" and "CANH" signals.

[0047] Fig. 4 illustrates a first embodiment of a DETC disturbance detection circuit.

[0048] The DETC disturbance detection circuit includes a first resistive element RI having a first terminal configured to receive the "CANL" signal.

[0049] The DETC disturbance detection circuit also includes a second resistive element R2 having a first terminal configured to receive the “CANH” signal.

[0050] The first resistive element RI and the second resistive element R2 each have a second terminal connected to a common node of the adjustment circuit.

[0051] Advantageously, the first resistive element RI and the second resistive element R2 have the same ohmic value. This makes it possible to obtain a voltage across the common node, between the first resistive element RI and the second resistive element R2, corresponding to the common-mode voltage. Preferably, the value of the first resistive element RI and the second resistive element R2 is chosen to avoid interfering with CAN communication. In particular, this value is chosen to be an order of magnitude greater than the differential resistance of the CAN bus in recessive mode.

[0052] The DETC disturbance detection circuit also includes a third resistive element R3 having a first terminal connected to the common node between the first resistive element RI and the second resistive element R2.

[0053] The DETC disturbance detection circuit also includes a fourth resistive element R4. This fourth resistive element R4 has a first terminal connected to a second terminal of the third resistive element R3.

[0054] The DETC disturbance detection circuit also includes a current source CS having a first terminal connected to a second terminal of the fourth resistive element R4, and a second terminal connected to a reference node. This reference node may, in particular, be connected to ground. Preferably, the current defined by the current source is relatively low in order to avoid drawing too much current on the "CANL" and "CANH" signals, which could impact CAN communication.

[0055] Thus, the third resistive element R3, the fourth resistive element R4 and the current source CS are arranged in series between the common node between the first resistive element RI and the second resistive element R2, and the reference node to which the second terminal of the current source CS is connected.

[0056] The value of the third resistive element R3 and the value of the fourth resistive element R4 are defined according to the desired envelope for detecting disturbances on the common mode of the "CANL" and "CANH" signals. These values ​​may be equal or different from each other.

[0057] In particular, the third resistive element R3 and the fourth resistive element R4 make it possible to define a voltage VMID on the first terminal of the third resistive element R3 and a voltage VB on the second terminal of the fourth resistive element R4.

[0058] The VMID voltage corresponds to the common mode voltage.

[0059] The voltage VB corresponding to the common-mode voltage less a threshold voltage, for example, 200 millivolts.

[0060] The disturbance detection circuit includes a low-pass filter (LPF). The low-pass filter (LPF) has an input connected to the second terminal of the third resistive element R3 and to the first terminal of the fourth resistive element R4.

[0061] The LPF low-pass filter has an output configured to deliver a voltage VA. The voltage VA corresponds to the common-mode voltage less a threshold voltage, for example 100 millivolts.

[0062] The output of the LPF low-pass filter is connected to two comparators CMP1, CMP2 in order to generate an inverse envelope used to monitor the common mode of the “CANL” and “CANH” signals.

[0063] In particular, the DETC disturbance detection circuit includes a first voltage comparator CMP1. This first comparator CMP1 has a first input, specifically an inverting input, connected to the first terminal of the third resistive element R3 in order to receive the VMID voltage.

[0064] The first comparator CMP1 also has a second input, in particular a non-inverting input, connected to the output of the low-pass filter LPF, more particularly to the output of the low-pass filter LPF, so as to receive the voltage VA.

[0065] The first comparator CMP1 has an output configured to deliver a voltage corresponding to the difference between the voltage VA and the voltage VMID.

[0066] The DETC disturbance detection circuit also includes a second voltage comparator CMP2. This second comparator CMP2 has a first input, in particular an inverting input, connected to the output of the low-pass filter LPF, more specifically to the output of the low-pass filter LPF, so as to receive the voltage VA.

[0067] The second comparator CMP2 also has a second input, in particular a non-inverting input, connected to the second terminal of the fourth resistive element R4 and to the first terminal of the current source CS, in order to receive the voltage VB.

[0068] The second comparator CMP2 has an output configured to deliver a voltage corresponding to the difference between the VA voltage and the VMID voltage.

[0069] The first comparator CMP1 and the second comparator CMP2 allow the common mode of the signals "CANH" and "CANL" to be compared to the defined inverse envelope. Advantageously, comparators CMP1 and CMP2 are implemented in the integrated circuit IC so as to be sufficiently fast to detect transitions between dominant and recessive modes.

[0070] The DETC disturbance detection circuit also includes an ADD adder circuit configured to sum the output signal of the first comparator CMP1 and the output signal of the second comparator CMP2. In particular, the ADD adder circuit has a first input connected to the output of the first comparator CMP1 and a second CMP2 input connected to the output of the second comparator.

[0071] This ADD adder circuit allows the detection of "glitches," that is, brief pulses (positive or negative) on the common mode outside the defined envelope. Thus, the ADD adder circuit makes it possible to detect whether a correction of the synchronization of the "CANL" and "CANH" signals is required. Figure 2 illustrates an example of a signal that can be obtained at the output of the ADD adder circuit.

[0072] Figure 5 illustrates a second embodiment of a DETC disturbance detection circuit.

[0073] This second embodiment differs from the first embodiment in that it allows the definition of an envelope rather than an inverse envelope. Indeed, instead of defining an inverse envelope using a single low-pass filter LPF, two low-pass filters LPF1 and LPF2 are used to define the envelope for monitoring the common mode of the "CANH" and "CANL" signals.

[0074] Thus, a first low-pass filter LPF1 has an input connected to the first terminal of the third resistive element R3 and an output connected to an input of the first comparator CMP1. This first low-pass filter LPF1 allows a first envelope voltage threshold to be defined.

[0075] The second low-pass filter LPF2 has an input connected to the second terminal of the fourth resistive element R4 and an output connected to an input of the second comparator CMP2. This second low-pass filter LPF2 allows a second envelope voltage threshold to be defined.

[0076] The first comparator CMP1 and the second comparator CMP2 are then configured to receive the common mode of the “CANH” and “CANL” signals by being connected to the second terminal of the third resistive element R3 and to the first terminal of the fourth resistive element R4.

[0077] Compared to this second embodiment, the first embodiment of the DETC disturbance detection circuit illustrated in [Fig.4] has the advantage of occupying less space in the integrated circuit due to the use of a single low-pass filter LPF instead of two low-pass filters LPF1, LPF2.

[0078] Figure 6 illustrates an embodiment of a PRC processing circuit. This PRC processing circuit includes an EVTD event monitoring circuit and two counters CNT_R, CNT_D.

[0079] The EVTD event monitoring circuit is connected to the output of the ADD adder circuit in order to detect whether the value of the adjustment bits needs to be adjusted according to the value at the output of the adder circuit.

[0080] The EVTD event monitoring circuit may, for example, include a flip-flop configured to be reset at each transition to dominant mode as well as at each transition to recessive mode from the TX control signal.

[0081] Depending on the mode of the “CANH” and “CANL” signals indicated by the TX control signal, the CNT_R counter or the CNT_D counter can be incremented by the EVTD event monitoring circuit when the value of the adjustment bits needs to be adjusted when a synchronization correction is required.

[0082] In particular, the CNT_D counter is used to adjust the adaptation bits for the dominant mode, and the CNT_R counter is used to adjust the adaptation bits for the recessive mode.

[0083] The value of each counter CNT_R, CNT_D allows the adaptation bits to be adjusted to be defined.

[0084] For example, each digital adaptation signal TMR_R, TMR_D comprises M adaptation bits. Each counter CNT_R, CNT_D can then be an N-bit counter allowing the adaptation of N least significant bits of the digital adaptation signal TMR_R or TMR_D, N being less than M. Each adaptation signal TMR_R, TMR_D can also comprise K most significant bits stored in non-volatile memory, K being equal to MN.

[0085] The value of the CNT_D counter associated with the dominant mode can be incremented when a disturbance is detected on the common mode of the “CANH” and “CANL” signals, in particular during a transition to the dominant mode.

[0086] The value of the CNT_R counter associated with the recessive mode can be incremented when a disturbance is detected on the common mode of the “CANH” and “CANL” signals, in particular during a transition to the recessive mode.

[0087] Such a PRC processing circuit allows the adaptation bits to be adjusted simply.

Claims

Demands

1. Integrated circuit comprising: - a digital processing unit (MCU), - a transmitter / receiver circuit (TRC) configured to transmit data between the digital processing unit (MCU) and a "Controller Area Network", "CAN" data bus, the transmitter / receiver circuit (TRC) being configured to deliver differential signals, called "CANH" and "CANL", according to a dominant mode and a recessive mode, each transition of the differential signals "CANH" and "CANL" between the dominant mode and the recessive mode being synchronized from adaptation bits received by the transmitter / receiver circuit, - an adjustment circuit (ADPC) of at least one adaptation bit based on at least one comparison between the common mode of the differential signals "CANH" and "CANL" and at least one threshold voltage.

2. Integrated circuit according to claim 1, wherein the adjustment circuit (ADPC) comprises: - a detection circuit (DETC) configured to detect disturbances on the common mode of the differential signals "CANH" and "CANL", and - a processing circuit (PRC) configured to adjust at least one adaptation bit when a disturbance on the common mode is detected by the detection circuit (DETC).

3. Integrated circuit according to claim 2, wherein the digital processing unit (MCU) is configured to deliver a control signal (TX) indicating the mode of the "CANL" and "CANH" signals, and wherein the processing circuit (PRC) is configured to receive the control signal (TX) in order to adapt at least one adaptation bit associated with the transition to the mode of the "CANL" and "CANH" signals corresponding to the mode indicated by the control signal (TX) when a disturbance is detected by the detection circuit (DETC).

4. Integrated circuit according to claim 3, wherein the detection circuit (DETC) is configured to receive the "CANH" and "CANL" signals and comprises: - a first resistive element (RI) and a second resistive element (R2) connected in series and configured to receive the "CANL" and "CANH" signals so as to obtain the common mode of these "CANL" and "CANH" signals at a common node between the first resistive element (RI) and the second resistive element (R2), - a third resistive element (R3), a fourth resistive element (R4) and a current source (CS) connected in series between the common node of the first resistive element (RI) and the second resistive element (R2) and a reference node, - a low-pass filter (LPF) with an input connected to a common node between the third resistive element (R3) and the fourth resistive element (R4) so ​​as to generate an output threshold voltage to monitor the common mode of the "CANH" and "CANL" signals, - a first comparator (CMP1) with a first input connected to the common node between the first resistive element (RI) and the second element resistive (R2),and a second input connected to the output of the low-pass filter (LPF), - a second comparator (CMP2) having a first input connected to a common node between the fourth resistive element (R4) and the current source (CS), and a second input connected to the output of the low-pass filter (LPF), - an adder circuit (ADD) having two inputs connected respectively to the outputs of the first and second comparators (CMP1, CMP2), and an output connected to the processing circuit (PRC).

5. Integrated circuit according to any one of claims 2 to 4, wherein the processing circuit comprises: - a first counter (CNT_D) configured to be incremented at each detection of disturbances on the common mode by the detection circuit (DETC) during a transition to the dominant mode, the value of the first counter (CNT_D) defining at least one adaptation bit for the transition to the dominant mode, - a second counter (CNT_R) configured to be incremented at each detection of disturbances on the common mode by the detection circuit (DETC) during a transition to the recessive mode, the value of the second counter (CNT_R) defining at least one adaptation bit for the transition to the recessive mode.

6. Integrated circuit according to claim 5, wherein the processing circuit includes an event monitoring circuit (EVTD) connected to the output of the detection circuit (DETC) and configured to increment, at each disturbance detection, the first counter (CNT_D) or the second counter (CNT_R) according to the mode of the “CANH” and “CANL” signals indicated by the control signal (TX) delivered by the digital processing unit (MCU).

7. Electronic device comprising an integrated circuit (IC) according to any one of claims 1 to 6.

Images