Method for countermeasuring against side-channel attack

Abstract

The invention relates to a method of protecting a circuit against attacks by auxiliary channels based on the analysis of variations in a supply voltage of the circuit to be protected (SPR), the method comprising steps consisting of: supplying the circuit to be protected by a DC voltage converter (VCV) receiving a DC external voltage (Vin); controlling a switching cell (VCT) of the voltage converter according to a first part of the switching period during which a capacitor (C1) of the voltage converter is charged and the circuit to be protected receives the external voltage, followed by a second complementary part of the switching period during which the circuit to be protected is supplied by discharging the capacitor, the capacitor having a capacitance varying according to a switching frequency of the voltage converter;and vary the duration of the switching period randomly in order to vary the supply voltage (Vo) of the circuit to be protected. Figure 1;

Description

Title of the invention: Countermeasure method against side-channel attack technical field

[0001] The present invention relates to methods for protecting a circuit against side-channel analysis aimed at discovering secret data manipulated by the circuit, and in particular secret data used by an encryption or decryption algorithm. The present invention is particularly applicable to smart card microcircuits, integrated-chip systems, ASICs (Application-Specific Integrated Circuits), and hardware cryptographic components integrated into other equipment such as computer motherboards, smartphones, video decoders, and game consoles. State of the art

[0002] The hardware security of systems plays a crucial role in protecting sensitive information against eavesdropping attacks. These attacks, known as side-channel attacks (SCAs), rely on a statistical analysis of the power consumption of a microcircuit, aiming to reveal secret data manipulated by the microcircuit.

[0003] Current solutions to counter such threats focus on different methods. Some techniques aim to inject noise, particularly during the execution of sensitive operations, in an attempt to decouple the microcircuit's energy consumption from the processing involved in manipulating sensitive data. Other techniques perform masking, ranging from order 1 to n, to reduce the link between the manipulated data and the microcircuit's power consumption. These techniques thus complicate the task of hackers seeking to discover the sensitive data manipulated by the microcircuit.

[0004] Recent research has explored innovative power management methods to enhance the security of integrated systems. Some of these methods propose using a linear current regulator to stabilize the externally visible current and precisely control the energy levels used by the microcircuit. In this way, the probability of successful current-based attacks is reduced. Although fully integrated, linear regulators prove insufficient as a countermeasure, thus requiring designers to implement other specific solutions, including the use of dedicated sources to generate noise in order to mask the power consumption of the microcircuit being protected.

[0005] Other methods propose to strengthen the protection of sensitive data handled using a DC / DC converter made with non-integrated components such as an inductor. However, the use of such non-integrated components may present a vulnerability to peering attacks, since the current analysis in the inductor is proportional to the microcircuit's power consumption. Furthermore, such non-integrated components occupy a very large microcircuit area.

[0006] In summary, the proposed methods contribute to significantly increasing the consumption and / or surface area of ​​the microcircuit, without providing a truly effective countermeasure solution, requiring the implementation of additional measures, which can lead to overconsumption of energy.

[0007] It is therefore desirable to be able to propose a countermeasure that is effective and has a limited impact on energy consumption and the surface area occupied by the microcircuit. Summary

[0008] Embodiments relate to a method of protecting a circuit against attacks by auxiliary channels based on the analysis of variations in a supply voltage of the circuit to be protected, the method comprising steps consisting of: supplying the circuit to be protected by a DC voltage converter receiving an external DC voltage; controlling a switching cell of the voltage converter according to a first part of a switching period during which a capacitor of the voltage converter is charged and the circuit to be protected receives the external voltage, followed by a second complementary part of the switching period during which the circuit to be protected is supplied by discharging the capacitor, the capacitor having a capacitance varying according to a switching frequency of the voltage converter;and vary the duration of the switching period randomly in order to vary the supply voltage of the circuit to be protected.

[0009] Thanks to these arrangements, fluctuations in the supply voltage to the circuit to be protected are mixed with fluctuations produced by the converter, and in particular by random variations in the converter's switching frequency and the presence of a capacitor with variable capacitance depending on the switching frequency. This measure has a limited impact on energy consumption and the microcircuit area occupied due to the reduced number of additional components required. Furthermore, if the capacitor is a solid-state capacitor, it can be integrated without occupying a large microcircuit area while exhibiting a high capacitance value at low frequencies. switching frequencies. In addition, if the capacitor is integrated, it is more difficult to observe the voltage variations across its terminals.

[0010] According to one embodiment, the switching cell is controlled so as to trigger switching frequency jumps synchronous with the switching period.

[0011] According to one embodiment, the switching cell is controlled so as to trigger switching frequency jumps at random times.

[0012] According to one embodiment: the capacitor is of the solid electrolyte supercapacitor type, formed in three dimensions, or the capacitor is made by a capacitive circuit behaving like a capacitor with variable capacitance depending on the frequency of a signal passing through the capacitive circuit.

[0013] According to one embodiment, an average supply voltage supplied to the circuit to be protected by the voltage converter is an integer fraction of the external supply voltage.

[0014] According to one embodiment, the capacitance of the capacitor varies with frequency in a ratio of 1 to 20.

[0015] According to one embodiment, the circuit to be protected is supplied by several DC voltage converters in parallel, receiving the external DC voltage, each converter comprising a switching cell controlled according to a first half of the switching period during which a capacitor of the voltage converter is charged and the circuit to be protected receives the external voltage, followed by a second half of the switching period during which the circuit to be protected is supplied by discharging the first capacitor, the capacitor of each voltage converter having a capacitance varying according to a switching frequency of the voltage converter, the duration of the switching period of each converter varying randomly.

[0016] According to one embodiment, the method includes steps consisting of measuring the current or voltage supplied to the circuit to be protected and adjusting the duration of the switching period so that the supply voltage supplied to the circuit to be protected remains above a minimum supply voltage value to maintain the circuit to be protected functional.

[0017] Embodiments may also relate to a power supply circuit for a circuit to be protected, comprising a DC voltage converter that receives an external DC voltage and supplies a supply voltage to the circuit to be protected, the DC voltage converter comprising: a switching cell, a first capacitor having a capacitance that varies according to a switching frequency of the voltage converter, and a control circuit for the cell. switching, the control circuit being configured to implement the previously defined process.

[0018] According to one embodiment, the first capacitor is of the solid electrolyte supercapacitor type, formed in three dimensions, or the first capacitor is made by a capacitive circuit behaving like a capacitor with variable capacitance depending on the frequency of a signal passing through the capacitive circuit.

[0019] According to one embodiment, an output of the converter connected to the circuit to be protected is connected to ground via an external capacitor, the external capacitor being of the solid electrolyte supercapacitor type, formed in three dimensions.

[0020] According to one embodiment, the first capacitor is of the solid electrolyte supercapacitor type, is formed in three dimensions above the circuit to be protected so as to form a screen blocking electromagnetic radiation.

[0021] According to one embodiment, the control circuit includes an oscillator providing a signal at the switching frequency to control the switching cell, the oscillator being voltage controlled by a random or pseudo-random voltage generator.

[0022] According to one embodiment, the switching cell includes a second capacitor of the same type as the first capacitor, the switching cell being configured so that the first and second capacitors are charged in series during the first half of the switching period and are connected in parallel during the second half of the switching period to supply the circuit to be protected. Brief description of the figures

[0023] The present invention will be better understood with the aid of the following description of exemplary embodiments with reference to the accompanying figures, in which identical reference signs correspond to structurally and / or functionally identical or similar elements.

[0024] [Fig. 1] Figure 1 schematically represents a DC-DC converter supplying a circuit to be protected, according to one embodiment,

[0025] [Fig.2] Figure 2 shows a curve of variation of the capacitance of a solid supercapacitor as a function of the frequency of variation of the current or voltage applied across the terminals of the capacitor,

[0026] [Fig.3] Figure 3 schematically represents a circuit having a capacitance that varies with frequency in a manner similar to that of a solid supercapacitor,

[0027] [Fig.4] Figure 4 shows, in the form of timing diagrams, an example of converter control signals, according to one embodiment,

[0028] [Fig. 5] Figure 5 represents, in the form of a timing diagram, an example of a frequency variation control signal, according to one embodiment,

[0029] [Fig. 6] Figure 6 illustrates, in the form of timing diagrams, the operation of the converter, according to one embodiment,

[0030] [Fig.7] Figure 7 schematically represents a DC-DC converter supplying a circuit to be protected, according to another embodiment,

[0031] [Fig.8] Figure 8 schematically represents a DC-DC converter supplying a circuit to be protected, according to another embodiment,

[0032] [Fig.9] Figure 9 schematically represents a DC-DC converter supplying a circuit to be protected, according to another embodiment. Detailed description

[0033] In patent application EP 4 383 543 (or US 2024 / 0186897), the Applicant proposed using a solid supercapacitor to adjust the operating mode of a capacitive DC-DC converter according to the current drawn by a load powered by the converter. This converter includes a feedback loop configured to lower the converter's operating frequency when the load current is low and to raise it when the current is high, while regulating its output voltage relative to a reference voltage.

[0034] In one embodiment, it is proposed to use the nonlinear characteristic of the solid supercapacitor to vary the output voltage of the converter randomly, thereby changing the power consumption of the microcircuit as seen from outside the device. To this end, the microcircuit to be protected, or its sensitive circuits, are powered by a capacitive DC-DC converter incorporating a nonlinear supercapacitor. The converter is controlled by a random or pseudo-random frequency generator. The frequency generator allows the converter's regulation frequency, and therefore the power consumption observed at its input, to be changed randomly without disrupting the operation being protected by the microcircuit.

[0035] Figure 1 shows a DC-DC voltage converter VCV providing a supply voltage Vo to a circuit to be protected SPR, according to one embodiment. The SPR circuit can be alone or assembled with other circuits on a semiconductor substrate. The VCV converter includes a voltage conversion circuit VCT and a control circuit CCT for the conversion circuit. The conversion circuit VCT includes a first solid electrolyte capacitor Cl and at least one switching cell with four switches SI, S2, S3, S4 is controlled by two control signals, PI and P2. The switching cell allows the capacitor Cl to be connected between the input Vin and a DC voltage output node N3 of the conversion circuit when the PI control signal is high and the P2 signal is low, and to be connected between a reference voltage source, for example, ground, and the output node N3 when the PI control signal is low and the P2 control signal is high. For this purpose, switch S1 connects a DC voltage input Vin to be converted to a node NI connected to the first electrode of capacitor Cl. Switch S2 connects the reference voltage source to a node N2 connected to the second electrode of capacitor Cl. Switch S3 connects node NI to the output node N3. Switch S4 connects node N2 to the output node N3, the latter being connected to the SPR circuit.The output node N3 can also be connected to ground via a capacitor Co.

[0036] The CCT control circuit comprises a PGN pulse generator providing two output signals PI, P2, an OSC oscillator controlled, for example, by voltage, and providing a signal having a frequency Fsw to the PGN pulse generator, and a random or pseudo-random RVG voltage generator providing a control voltage Vfq to the OSC oscillator. The PI output signal of the PGN pulse generator controls switches S1 and S4, and the P2 output signal controls switches S2 and S3.

[0037] The capacitor Cl can be of the solid electrolyte supercapacitor type. This designation results from the high surface capacitance (in the plane of an integrated circuit where the capacitor can be formed) of the capacitor. Such capacitors offer a greater charge storage capacity than an electrostatic capacitance due to their ionic operation. In particular, solid electrolyte supercapacitors exhibit capacitance values ​​on the order of ten times greater than those of trench capacitors in silicon substrates and on the order of a thousand times greater than those of surface capacitors.

[0038] Solid electrolyte capacitors comprise at least two electrodes made of conductive material, separated by a dielectric and ionically conductive material in the solid state, commonly called a solid electrolyte. Several families of materials are considered to fulfill this role, such as amorphous glasses, for example LiPON ("Lithium Phosphorus Oxynitride"), crystalline oxides of the perovskite and garnet family LLTO ("Lithium Lanthanum Titanate Oxide"), LLZO ("Lithium Lanthanum Zircon Oxide"), LATP (Lii .3Al0.3Tii 7(PO4)3), and lithium sulfides LGPS (Li10GeP2Si2) or LPS (Li3PS4).

[0039] Solid electrolyte capacitors are characterized by a dual capacitive response, namely a first response in a low-frequency range, linked to the The formation of an electrochemical double layer at the electrode / electrolyte interfaces, and a second response related to the dielectric polarization of the solid electrolyte. This specificity is characteristic of ionic capacitances using a solid electrolyte.

[0040] However, solid electrolyte supercapacitors lose their efficiency at high frequencies due to the lower mobility of the ions on which their operating principle is based compared to the electrons used by electrostatic capacitors.

[0041] Figure 2 shows the evolution of the capacitance C per unit area of ​​a solid electrolyte supercapacitor. At frequencies below a certain frequency FL, the capacitance C is that CH of a solid electrolyte capacitor in ionic operating mode. However, above the frequency FL, the surface capacitance C decreases, as the solid electrolyte capacitor ceases to operate in ionic mode. Above a frequency FH ​​higher than the frequency FL, the surface capacitance C becomes of the same order of magnitude as the capacitance CL of an electrostatic capacitor formed in the form of trenches. Thus, a solid electrolyte capacitor exhibits ionic operating mode up to a certain switching frequency FL and electrostatic operating mode beyond that point. The electrostatic operating mode is said to be stabilized above the frequency FH.

[0042] Figure 3 shows an SM circuit forming a component with behavior close to that of a solid electrolyte supercapacitor, and in particular a capacitance that varies according to the curve in Figure 2, depending on the frequency of the voltage applied between terminals B1 and B2 of the circuit. The SM circuit includes a resistor RI1 connected in series with a capacitor C12 between terminal B1 of the component and node NI1. The SM circuit also includes a resistor R12 connected in parallel with a capacitor C12 between node NI1 and terminal B2 of the SM circuit. The capacitances of capacitors C11 and C12 are respectively equal to CH and CL, which may have a ratio of 20, for example, 10 pF and 0.5 pF respectively. The resistors RI1 and R12 represent nonlinear capacitance resistors and may be fixed, for example, to 0.1 and 20 Ω, respectively.The frequencies FL and FH reached by the SM circuit are respectively equal to 10 kHz and 1 MHz, given the values ​​of the resistances R11, R12 and the capacitances of the capacitors C11, C12, indicated above.

[0043] According to one embodiment, the capacitor Cl of the VCT conversion circuit is implemented by the SM circuit.

[0044] According to another embodiment, the capacitor Cl is a solid electrolyte supercapacitor, formed in three dimensions on the semiconductor substrate where the circuit to be protected (SPR) is formed. In this configuration, the capacitor Cl forms a shield against electromagnetic radiation, and thus prevents attacks via auxiliary channels exploiting the electromagnetic radiation of the circuit.

[0045] Figure 4 shows, in timing diagram form, the PI, P2 control signals for switches SI to S4, generated by the PGN pulse generator. The PGN pulse generator is configured so that the PI, P2 signals it generates are square waves, out of phase, so that switches SI, S4 on the one hand, and switches S2, S3 on the other, are never closed simultaneously. The time during which switches SI to S4 are simultaneously closed is reduced or preferably zero. In one embodiment, switches SI, S4 are closed and switches S2, S3 are open during a first part T1 of a switching period Tsw, and switches SI, S4 are open and switches S2, S3 are closed during a second part T2 complementary to the switching period Tsw.In the embodiment illustrated by Figure 4, the first and second parts of the switching period have a duration equal to Tsw / 2.

[0046] Figure 5 shows, in the form of a timing diagram, an example of the variation of the frequency Fsw of the output signal of the OSC oscillator. In this example, the random voltage generator RVG is configured so that the OSC oscillator provides a signal that can randomly take one of four predefined frequencies F0, F1, F2, F3, each frequency being maintained for a period Ts.

[0047] According to one embodiment, the period Ts is fixed at an integer multiple of the period Tsw of the control signals PI, P2, and the frequency jump times are synchronous with a period start of the signal PI or P2. The period Ts can also be changed randomly at random times, while remaining equal to a multiple of the period Tsw.

[0048] According to another embodiment, the period Ts is not equal to an integer multiple of the period Tsw and can be changed randomly at random times.

[0049] Figure 6 illustrates, in the form of timing diagrams, the operation of the VCV converter according to one embodiment. Figure 6 shows an example of the variation of the output voltage Vfq of the voltage generator RVG, the signals Fsw and PI, and the output voltage Vo of the conversion circuit VCT, when the capacitor Cl of the conversion circuit VCT is of the electrostatic type with a fixed capacitance equal to CL, and when the capacitor Cl has a capacitance that varies according to the switching frequency, for example, when the capacitor Cl is of the solid electrolyte ionic capacitance type. Before a time tl, between the time tl and a At time t2, and between time t2 and time t3, the voltage Vfq controls the output of a signal by the oscillator OSC at frequencies Fsw = F3, F2, and Fl (for example, those shown in Figure 5), which are higher than the frequency FH. The capacitor Cl is therefore in an electrostatic operating mode, having a capacitance equal to CL. The oscillations observed in the output voltage Vo increase as the frequency Fsw decreases. Between time t3 and time t4, the frequency Fsw of the OSC output signal drops to the frequency FO, which is lower than the frequency FL. Between time t4 and time t5, and after time t5, the frequency Fsw of the oscillator output signal returns to the frequency Fl, and then to the frequency F2.

[0050] In the case where the capacitor Cl of the conversion circuit has a capacitance CL, the oscillations observed in the output voltage Vo between times t3 and t4 fall outside the supply voltage range between Vmx and Vmn, which is permissible for the SPR circuit to be protected. In the example of [Fig. 6], the lower peaks of these oscillations fall below the minimum permissible voltage Vmn. Conversely, when the capacitor Cl is of the ionic capacitance type, it switches to ionic operating mode between times t3 and t4, because the frequency Fsw is lower than the frequency FL (Figure 3), and takes on the capacitance value CH. Implementing a high-capacitance capacitor such as CH makes it possible to maintain the oscillations of the output voltage Vo within the permissible range of values ​​Vmn-Vmx, and in particular above the minimum permissible voltage Vmn, especially when the frequency Fsw is low.

[0051] According to one embodiment, the capacitor Co is also of the ionic capacitance type like the capacitor Cl of the VCT conversion circuit. This arrangement makes it possible to widen the switching frequency variation range Fsw without impacting the supply voltage Vo of the SPR circuit to be protected, in particular by keeping this voltage within the permissible range, between Vmin and Vmx.

[0052] The VCT conversion circuit of Figure 1 provides an output voltage Vo equal to half the input voltage Vin when the two considered parts T1, T2 of the switching period Tsw are equal to Tsw / 2, as illustrated in Figure 4. The conversion circuit can divide the input voltage according to other ratios, for example by 3 or 4, by changing the respective durations of the considered parts of the switching period or by the architecture of the switching cell. Thus, Figure 7 shows a VCT1 conversion circuit providing an output voltage Vo equal to one-third of the input voltage Vin of the conversion circuit, according to one embodiment. The VCT1 conversion circuit differs from the VCT conversion circuit in that it includes a switching cell with Seven switches, S1 to S4 (already described) and S5 to S7, are controlled by the two control signals PI and P2, and a second capacitor C2, which can have the same characteristics as capacitor C1. The switching cell allows capacitors C1 and C2 to be connected in series between the input Vin and the output node N3 of the conversion circuit VCT1 when the control signal PI is high and the signal P2 is low. It also connects these capacitors in parallel between a reference voltage source, such as ground, and the output node N3 when the control signal PI is low and the control signal P2 is high. To achieve this, switch S1 connects the input Vin of the conversion circuit VCT1 to node N1, which is connected to the first electrode of capacitor C1. Switch S2 connects the reference voltage source to node N2, which is connected to a second electrode of capacitor C2. Switch S3 connects node N1 to the output node N3.Switch S4 connects node N2 to output node N3, which is connected to the SPR circuit. Switch S5 connects the second electrode of capacitor C1 to the reference voltage source. Switch S6 connects the second electrode of capacitor C1 to the first electrode of capacitor C2. Switch S7 connects the first electrode of capacitor C2 to node N3. Switches S1, S4, and S6 are controlled by the PI signal, and switches S2, S3, S5, and S7 are controlled by the P2 signal. As before, output node N3 can be connected to ground via capacitor C0. The control circuit for switches S1-S7 of the VCT1 conversion circuit can be the CCT control circuit shown in Figure 1.

[0053] According to an embodiment illustrated in Figure 8, several voltage converters VCV1, VCV2, VCV3 are connected in parallel between the voltage source Vin and the SPR circuit to be protected. Each converter VCV1, VCV2, VCV3 comprises a conversion circuit such as the conversion circuit VCT or VCT1, controlled by a respective control circuit such as the control circuit CCT. In this way, the SPR circuit to be protected receives voltages from several sources formed by the different converters VCV1-VCV3 in parallel, the received voltages each varying randomly and independently. In this way, the masking of current variations in the SPR circuit can be even more effective.

[0054] According to an embodiment illustrated in Figure 9, the VCV4 converter comprises the conversion circuit VCT or VCT1 and a control circuit CCT1. The control circuit CCT1 differs from the control circuit CCT in that it implements a closed-loop voltage regulation circuit that receives at its input a measurement signal CS of the current or voltage supplied to the circuit to be protected SPR. For this purpose, the converter includes a current sensor IS1 disposed on the output link. from the output node N3, and the CCT1 circuit includes an SMX circuit for generating the control signal Vfq of the OSC oscillator, based on the signal from the random voltage generator RVG and a signal generated by a control circuit CCO of the OSC oscillator receiving the measurement signal CS as input. For example, the SMX circuit can be configured to ensure that the circuit to be protected SPR always receives an appropriate voltage, between Vmx and Vmn.

[0055] It will be evident to those skilled in the art that the present invention is susceptible to various embodiments and applications. In particular, the invention is not limited to the implementation of a single capacitor coupled to the switching cell. Indeed, several capacitors arranged in series and / or in parallel can be coupled to the switching cell. In the case where several switching cells are implemented, the capacitors coupled to these switching cells are not necessarily in the same ionic / electrostatic operating mode.

Claims

Demands

1. 1. A method for protecting a circuit against side-channel attacks based on the analysis of variations in a supply voltage of the circuit to be protected (SPR), the method comprising steps of: supplying the circuit to be protected by a DC voltage converter (VCV) receiving a DC external voltage (Vin); controlling a switching cell (VCT) of the voltage converter according to a first part (T1) of a switching period (Tsw) during which a capacitor (Cl) of the voltage converter is charged and the circuit to be protected receives the external voltage, followed by a second part (T2) complementary to the switching period during which the circuit to be protected is supplied by discharging the capacitor, the capacitor having a capacitance (CH, CL) varying according to a switching frequency (Fsw) of the voltage converter;and vary the duration of the switching period in a random manner in order to vary the supply voltage (Vo) of the circuit to be protected.

2. 2. Method according to claim 1, wherein the switching cell (VCT) is controlled so as to trigger synchronous switching frequency jumps of the switching period (Tsw).

3. 3. Method according to claim 1, wherein the switching cell (VCT) is controlled so as to trigger switching frequency jumps at random times.

4. 4. A method according to any one of claims 1 to 3, wherein: the capacitor (Cl) is of the solid electrolyte supercapacitor type, formed in three dimensions, or the capacitor (Cl) is made by a capacitive circuit (SM) behaving as a capacitor with variable capacitance depending on the frequency of a signal passing through the capacitive circuit.

5. 5. A method according to any one of claims 1 to 4, wherein an average supply voltage supplied to the circuit to be protected (SPR) by the voltage converter (VCV) is an integer fraction of the external supply voltage (Vin).

6. 6. Method according to claim 5, wherein the capacitance of the capacitor (Cl) varies with frequency in a ratio of 1 to 20.

7. 7. A method according to any one of claims 1 to 6, wherein the circuit to be protected is supplied by several parallel DC voltage converters (VCV1, VCV2, VCV3), receiving the external DC voltage (Vin), each converter comprising a switching cell (VCT) controlled according to a first half of the switching period (Tsw) during which a capacitor of the voltage converter is charged and the circuit to be protected receives the external voltage, followed by a second half of the switching period during which the circuit to be protected is supplied by discharging the first capacitor, the capacitor of each voltage converter having a capacitance varying according to a switching frequency (Fsw) of the voltage converter, the duration of the switching period of each converter varying randomly.

8. 8. A method according to any one of claims 1 to 7, comprising steps of measuring the current or voltage (Vo) supplied to the circuit to be protected (SPR) and adjusting the duration of the switching period (Tsw) so that the supply voltage supplied to the circuit to be protected remains above a minimum supply voltage value (Vmn) to maintain the circuit to be protected functional.

9. 9. Power supply circuit of a circuit to be protected comprising a DC voltage converter (VCV) receiving an external DC voltage (Vin) and supplying a supply voltage (Vo) to the circuit to be protected (SPR), the DC voltage converter comprising: a switching cell (VCT), a first capacitor (Cl) having a capacitance (CH, CL) varying according to a switching frequency (Fsw) of the voltage converter, and a control circuit (CCT) of the switching cell, the control circuit being configured to implement the method according to any one of claims 1 to 8.

10. 10. Power supply circuit according to claim 9, wherein: the first capacitor (Cl) is of the solid electrolyte supercapacitor type, formed in three dimensions, or the first capacitor (Cl) is made by a capacitive circuit (SM) behaving like a capacitor with variable capacitance depending on the frequency of a signal passing through the capacitive circuit.

11. 11. Power supply circuit according to claim 9 or 10, wherein an output (Vo) of the converter (VSV) connected to the circuit to be protected is connected to ground via an external capacitor (Co), the external capacitor being of the solid electrolyte supercapacitor type, formed in three dimensions.

12. 12. Power supply circuit according to any one of claims 9 to 11, wherein the first capacitor (Cl) is of the solid electrolyte supercapacitor type, is formed in three dimensions above the circuit to be protected so as to form a screen blocking electromagnetic radiation.

13. 13. Power supply circuit according to any one of claims 9 to 12, wherein the control circuit (CCT) comprises an oscillator (OSC) providing a signal at the switching frequency (Fsw) to control the switching cell (VCT), the oscillator being voltage controlled by a random or pseudo-random voltage generator.

14. 14. Power supply circuit according to any one of claims 9 to 13, wherein the switching cell (VCT1) comprises a second capacitor (C2) of the same type as the first capacitor (Cl), the switching cell being configured so that the first and second capacitors are charged in series during the first half of the switching period (Tsw) and are connected in parallel during the second half of the switching period to supply the circuit to be protected.

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