Pixel

Abstract

Pixel This description concerns a logarithmic response pixel having a photosensitive element (D1) connected to at least one bipolar junction transistor configured as a diode. Figure for the abbreviation: Fig. 2

Description

Title of the invention: Pixel technical field

[0001] This description relates generally to pixels, electronic sensors comprising these pixels, as well as image acquisition devices comprising these sensors and their operating methods. Previous technique

[0002] Current image acquisition devices use optoelectronic sensors comprising pixels whose operation is based on the detection of temporal variations to deduce object contours in the acquired images. However, this involves the implementation of numerous transistors, and the performance obtained in the presence of significant light variations is limited. Summary of the invention

[0003] There is a need to provide optoelectronic pixels and sensors enabling the detection of object contours, including in the presence of significant light variations, while reducing the number of transistors involved.

[0004] An embodiment overcomes all or part of the disadvantages of known pixels and sensors.

[0005] One embodiment provides for a logarithmic response pixel having a photosensitive element connected to at least one bipolar junction transistor mounted as a diode.

[0006] One embodiment provides for a method of operating a pixel comprising the generation of a logarithmic response of a bipolar junction transistor, mounted as a diode and connected to a photosensitive element, following the light excitation of the photosensitive element.

[0007] According to one embodiment, the base and a conduction node of the bipolar junction transistor are connected.

[0008] According to one embodiment, the photosensitive element is connected in series to the bipolar junction transistor between a first terminal and a second terminal, the second terminal being connected to an application terminal of a first reference voltage.

[0009] According to one embodiment, the first terminal is connected to an application terminal of a second reference voltage different from the first reference voltage.

[0010] According to one embodiment, the pixel comprises a first transistor, of the MOS type, connecting the application terminal of the second reference voltage and a first node connected to a current source, a control node of the first transistor being connected to the midpoint of the photosensitive element and the bipolar junction transistor; the pixel preferably comprising a second transistor, of the MOS type, connecting the first node to the current source, the current source being preferably connected to a column of an optoelectronic sensor.

[0011] According to one embodiment, the pixel comprises: a first transistor, of the MOS type, connecting the application terminal of the second reference voltage and a first node, a second transistor, of the MOS type, connecting the first transistor to a current source, and a third transistor in series with a storage capacitor between the first terminal and the second terminal, a control node of the third transistor being connected to the midpoint of the photosensitive element and the bipolar junction transistor, a control node of the first transistor being connected to the midpoint of the third transistor and the storage capacitor, a fourth transistor connecting the midpoint of the third transistor and the storage capacitor to the second terminal.

[0012] According to one embodiment, the pixel includes a transimpedance capacitive amplification stage connecting an event detection stage and the first node, the event detection stage being configured to modify a value of a storage bit as a function of the voltage present at the output of the transimpedance capacitive amplification stage.

[0013] According to one embodiment, the event detection stage includes at least one comparator circuit configured to detect a variation in the output voltage of the transimpedance capacitive amplification stage relative to a threshold or voltage range and to reset the capacitive amplification stage according to this variation.

[0014] According to one embodiment: - the photosensitive element is configured to photogenerate holes and is connected in series to the bipolar junction transistor between a first terminal and a second terminal, the second terminal being connected to an application terminal of a first reference voltage; - The bipolar junction transistor is a PNP type transistor; and - The base and emitter of the bipolar junction transistor are connected together at the second terminal, the photosensitive element being, preferably, connected to the first terminal and the first reference voltage being -VDD.

[0015] One embodiment provides an optoelectronic sensor comprising a pixel matrix having linear response pixels, for example of type 3T, 4T or 5T, and logarithmic response pixels as described above.

[0016] According to one embodiment, the logarithmic response pixels are arranged along the diagonals of the matrix.

[0017] According to one embodiment, the sensor comprises: - at least one subtractor block configured to perform a first subtraction of a voltage, present on the midpoint of the photosensitive element and the junction bipolar transistor of a first pixel with logarithmic response of the matrix, with a voltage present on the midpoint of the photosensitive element and the junction bipolar transistor of a second pixel with logarithmic response of the matrix; - a comparator block configured to compare the result of the first subtraction to a first and a second threshold; and - an event-based reading circuit connected to the comparator block.

[0018] According to one embodiment, the sensor comprises: - at least one subtractor block configured to perform a first subtraction of a voltage, present on the first node of a first pixel with logarithmic response of the matrix, with a voltage present on the first node of a second pixel with logarithmic response of the matrix; - a comparator block configured to compare the result of the first subtraction to a first and a second threshold; and - an event-based reading circuit connected to the comparator block.

[0019] According to one embodiment: - the subtractor block is further configured to perform a second subtraction of the voltage present on the midpoint of the photosensitive element and the junction bipolar transistor of the second logarithmic response pixel of the matrix, with a voltage present on the midpoint of the photosensitive element and the junction bipolar transistor of a third logarithmic response pixel of the matrix; - the comparator block being configured to compare the result of the second subtraction with said first threshold and said second threshold.

[0020] According to one embodiment: - the subtractor block is further configured to perform a second subtraction of the voltage present on the first node of the second pixel with logarithmic response of the matrix, with a voltage present on the first node of a third pixel with logarithmic response of the matrix; - the comparator block being configured to compare the result of the second subtraction with said first threshold and said second threshold.

[0021] According to one embodiment, the subtractor block comprises at least one differential amplifier of which: - an output is connected to the first terminal of the first pixel; - an inverting input is connected to the midpoint of the photosensitive element and the bipolar junction transistor of the first pixel (812); - a non-inverting input is connected to the midpoint of the photosensitive element and the bipolar junction transistor of the second pixel.

[0022] According to one embodiment, the subtractor block comprises at least one differential amplifier of which: - an output is connected to the first node of the first pixel via a first resistor; - an inverting input is connected to the first node of the first pixel; and - a non-inverting input is connected to the first node of the second pixel and to an application terminal of a third reference voltage via a second resistor. Brief description of the drawings

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0024] [Fig.1] represents an optoelectronic sensor in block form;

[0025] [Fig.2] represents a pixel of the sensor of [Fig.1] according to one embodiment;

[0026] [Fig.3] represents a pixel of the sensor of [Fig.1] according to one embodiment;

[0027] [Fig.4] represents a pixel of the sensor of [Fig.1] according to one embodiment;

[0028] [Fig.5] represents a pixel of the sensor of [Fig.1] according to one embodiment;

[0029] [Fig.6] illustrates a cross-sectional view of one-pixel elements of figures 2 to 4 according to one embodiment;

[0030] [Fig.7] represents a pixel of the sensor of [Fig.1] according to one embodiment;

[0031] [Fig. 8] represents an exploded view of an optoelectronic device according to a mode of realization;

[0032] [Fig.9] represents an optoelectronic sensor according to one embodiment;

[0033] [Fig. 10] represents an optoelectronic sensor according to one embodiment;

[0034] [Fig.1 1] represents an optoelectronic sensor according to one embodiment;

[0035] [Fig. 12] represents an optoelectronic sensor according to one embodiment;

[0036] [Fig. 13] represents a pixel of the sensor of [Fig. 1] according to one embodiment;

[0037] [Fig. 14] represents an optoelectronic sensor according to one embodiment;

[0038] Figures 15A to 15E represent an optoelectronic sensor according to one embodiment; and

[0039] Fig. 16 represents an optoelectronic sensor according to one embodiment. Description of the implementation methods

[0040] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0041] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0042] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0043] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0044] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0045] Fig. 1 represents an optoelectronic sensor 100 in block form.

[0046] In the example shown, the optoelectronic sensor 100 comprises pixels arranged in a matrix of four rows and three columns. This number of rows and columns is presented for illustrative purposes only, and in reality, the number of rows and columns is several thousand or even several hundred thousand. Pixels 110i, 110ii, 110iii are arranged in a first row and connected, preferably connected, to a first horizontal track 112i of the matrix. Pixels 120i, 120ii, 120iii are arranged in a second row and connected, preferably connected, to a second horizontal track 112ii of the matrix. Pixels 130i, 130ii, 130iii are arranged in a third row and connected, preferably connected, to a third horizontal track 112iii of the matrix.Pixels 140i, 140ii, and 140iii are arranged in a fourth row and connected, preferably connected, to a fourth horizontal row 112iiii of the matrix. Pixels with the index "i" are arranged in the same first column and connected to at least one vertical track from among two distinct tracks 113i and 114i. Pixels with the index "ii" are arranged in a second column and connected to at least one vertical track from among two distinct tracks 113ii and 114ii. Pixels with the index "iii" are arranged in a third column and connected to at least one vertical track from among two distinct tracks 113iii and 114iii. The output signals of each pixel are transmitted to the input of a... A network of analog / digital circuits (not shown) with electrical functions such as signal amplification, noise correction, signal filtering, and analog-to-digital conversion (ADC). Once the data is acquired, an image must then be reconstructed for storage, processing, and / or display, depending on the application system.

[0047] All or part of the matrix pixels may implement event-based operation ("event-based pixel") such as changes in light intensity. The matrix pixels may also be active image pixels (APS).

[0048] The architecture of the active pixels can be, for example, a 3T, 4T, or 5T pixel architecture, which uses three, four, and five transistors, respectively. This architecture allows for a linear response, meaning that it provides a physical value, such as a voltage or current, at the pixel output that varies linearly with illumination as long as there is no saturation.

[0049] To increase the dynamic range of sensors, i.e., the range of maximum light intensity before saturation, it is possible to use a pixel architecture implementing a logarithmic response. In practice, such a pixel is obtained with a photodiode, biased at a voltage VDD, and connected to a MOS transistor biased below its threshold voltage. This allows for a logarithmic response, meaning that it provides a physical value at the pixel output, such as a voltage or current, that varies logarithmically with illumination. However, pixels implemented in this way have a noisy response due to thresholding effects. Furthermore, the manufacturing dispersion of the threshold voltages of the MOS transistors in the pixel array, related to the logarithmic conversion, drastically limits performance.Low-light performance is also penalized by the use of MOS transistors below the threshold, which causes operating latencies.

[0050] Pixels 1 lOi can for example be organized in an interlaced matrix (“interlaced” or “interleaved” in English) with some having an event-based operation and others dedicated to a static operation.

[0051] In another example not shown, each pixel 110 (i, ii, iii), 120 (i, ii, iii), 130 (i, ii, iii) of the image acquisition device 100 comprises a photodiode connected to a circuit having a first architecture dedicated to event-based operation and to another circuit having a second architecture dedicated to linear operation. In this example, for each sensor, a switch directs the current photogenerated by the respective photodiode either to the pixel having the first architecture or to the pixel of the sensor having the second architecture. This allows for high resolution but does not allow for simultaneous operation.

[0052] Depending on their architecture, pixels can operate asynchronously or synchronously. Asynchronous pixels require an Address-Event Representation (AER), and pulses are sent each time an event, such as a change in light intensity, occurs. Synchronous sensors, on the other hand, require storage, and with each clock signal pulse, data is sent or not depending on whether an event has been detected or not.

[0053] The various examples presented base the detection of events or movements in a scene on temporal variations of light, because the strong mismatch of MOS transistors operating below the threshold makes it impossible to subtract the signal from pixel to pixel. This has the disadvantage that the number of transistors used per pixel exceeds ten and that capacitive contrast amplification devices are required.

[0054] The use of standard pixels having a linear response in light intensity does not allow for effective contrast detection, because in scenes where variations in light intensity are significant, their low dynamic range can create saturated areas and many false events in areas of strong light, and make them blind under low light intensity.

[0055] In order to overcome the disadvantages raised, the embodiments provide for the use of logarithmic response pixels having a photosensitive element connected to at least one bipolar junction transistor (B JT) mounted as a diode.

[0056] The use of a bipolar transistor mounted as a diode is counterintuitive because for many years MOS or CMOS technology has been prioritized for pixel design. This is due to the fact that MOS transistors are smaller than bipolar transistors. Designers seeking miniaturization or increased resolution have therefore naturally developed systems based on MOS or CMOS technology. However, given the number of transistors per pixel used for event-based information processing, the intrinsic advantage of MOS or CMOS transistors becomes limited.The use of a pixel with a bipolar transistor, mounted as a diode, i.e. whose base is connected, preferably connected, to one of these conduction nodes, has an important advantage over MOS or CMOS transistors, which is that the differences in threshold voltages, due to dispersions during manufacturing, between two bipolar junction transistors, are much lower compared to the dispersion of threshold voltages of MOS transistors of the same matrix.

[0057] This makes it possible to consider a detection of spatial variations in light intensity, and no longer temporal, and which works even when significant variations in light are present in the scene, while implementing only a limited number of transistors.

[0058] In some cases, this also makes it possible to do without capacitive amplification.

[0059] Even though bipolar transistors have a larger footprint on the surface of a chip than MOS transistors, the fact that the pixel using a bipolar transistor mounted as a diode requires a lower total number of transistors ultimately improves performance compared to pixels based on MOS transistors, while obtaining an equivalent footprint.

[0060] The embodiments presented illustrate examples of implementation of logarithmic response pixels having a photosensitive element connected to at least one bipolar junction transistor mounted as a diode, i.e. it is biased under its threshold voltage.

[0061] [Fig.2] represents a pixel 200 of sensor 100 of [Fig.1] according to one embodiment.

[0062] More specifically, pixel 200 represents a possible implementation of all or part of pixels 110(i, ii, iii), 120(i, ii, iii), 130(i, ii, iii).

[0063] The pixel 200 comprises a photosensitive element DI connected, preferably connected, at a node NI, to at least one bipolar junction transistor BJT1 configured as a diode, i.e., in the illustrated example, its base is connected to the collector. In other words, during operation, the BJT1 transistor is biased below its threshold. The collector of the BJT1 transistor is connected, preferably connected, to a terminal for applying a reference voltage Vdd (also written as VDD in the text). In the example in [Fig. 2], the BJT1 transistor is an NPN bipolar junction transistor.

[0064] The photosensitive element DI is, for example, a silicon-based photodiode or pinch-off diode, or a photodiode comprising nanoparticles forming a photosensitive layer. In the example shown, the photosensitive element is represented by a capacitor in parallel with a current source connecting ground (Gnd) to node NI.

[0065] In the example shown, the pixel 200 also includes a transistor 202, for example of the NMOS type, which is mounted as a source follower with its source connected, preferably connected, to node NI, a conduction node connected, preferably connected, to the voltage application terminal Vdd and another conduction node connected, preferably connected, to a node N2. Node N2 is connected, for example, to a ground application terminal by a current source 204.

[0066] During operation, the current generated by the photosensitive element DI when it receives light becomes a voltage, at node NI, varying logarithmically with respect to the photogenerated current, due to the diode configuration of transistor BJT1. This logarithmic response can be read, to within the voltage Vgs of transistor 202, at node N2.

[0067] By comparing these voltages between several pixels it is possible to deduce relative variations of light intensity in a scene in a spatial way and to obtain for example contours of objects, even if the variations in intensity are significant since they are attenuated by the logarithmic function.

[0068] The example in [Fig.2] can constitute the first stage of a dynamic vision sensor (DVS) and / or edge detection sensor.

[0069] Figure 3 represents a pixel 300 of the sensor of Figure 1 according to one embodiment. More particularly, pixel 300 represents a possible implementation of all or part of pixels 110(i, ii, iii), 120(i, ii, iii), 130(i, ii, iii).

[0070] Pixel 300 is similar to that of [Fig. 2] except that pixel 300 includes a transistor 306, which is used to select the row of the respective pixel matrix when activated. Transistor 306, which is, for example, an NMOS transistor, connects node N2 to current source 204. In the example shown, current source 204 is also connected, preferably connected, to one of the columns 114 (i, ii, iii) of the matrix. Pixel 300 further connects node N2 to column 114 (i, ii, iii) at a node N3.

[0071] Pixel 300 forms what is commonly called a "3T" pixel due to the use of three transistors, including a bipolar junction transistor.

[0072] Figure 4 represents a pixel 400 of the sensor of Figure 1 according to one embodiment. More particularly, pixel 400 represents a possible implementation of all or part of pixels 110(i, ii, iii), 120(i, ii, iii), 130(i, ii, iii).

[0073] The pixel of [Fig.4] is similar to that of [Fig.3] except that it includes additional transistors 402 and 408, for example of the NMOS type, and a capacitor 410.

[0074] Transistor 408 connects the control node of transistor 202 to the ground application terminal. Capacitor 410 also connects the control node of transistor 202 to the ground application terminal. Transistor 402 connects the Vdd voltage application terminal to the control node of transistor 202. The control node of transistor 402 is connected, preferably connected, to node NI. Transistor 408 allows the reset of the charges stored on capacitor 410.

[0075] Pixel 400 forms what is commonly called a "5T" pixel due to the use of five transistors. This type of pixel implements an integration stage on capacitor 410 to reduce noise sensitivity.

[0076] Figure 5 represents a pixel 500 of the sensor of Figure 1 according to one embodiment. More particularly, pixel 300 represents a possible implementation of all or part of pixels 110(i, ii, iii), 120(i, ii, iii), 130(i, ii, iii).

[0077] The sensor 500 comprises a photosensitive element D2 connected, preferably connected, at a node N02, to at least one bipolar junction transistor BJT2, here of the PNP type and configured as a diode, i.e., in the illustrated example, its base is connected to the emitter. In other words, the BJT2 transistor operates below its threshold voltage. The emitter of the BJT2 transistor is connected, preferably connected, to a terminal for applying a reference voltage -VDD. The photosensitive element D2 is, for example, a silicon-based photodiode or pinch-off diode, or a photodiode comprising nanoparticles forming a photosensitive layer.

[0078] In the example shown, pixel 200 also includes an SF2 transistor, for example of the NMOS type, which is mounted as a source follower with its source connected, preferably connected, to node N02, a conduction node connected, preferably connected, to the ground application terminal or -VDD, and another conduction node connected, preferably connected, to a node N03. A selection transistor SEL2 connects node N03 to a column 113 (i, ii, iii) of the pixel matrix at a node N04. In the example shown, a current source 516, for example similar to the current source 204, is connected to column 113 (i, ii, iii).

[0079] The photosensitive element D2 of [Fig. 5] comprises, for example, a photodiode having its cathode connected, preferably connected, to a first electrode N01 and its anode connected, preferably connected, to node N02. The photosensitive element D2 further comprises a capacitance Cfwl (full well capacitance) corresponding to the capacitance of the depleted photodiode, in series with a capacitance Ccdti, between the first electrode N01 and a terminal for applying a voltage Vcdti, corresponding to the biasing of a Metal-Oxide-Semiconductor (MOS) capacitance made, for example, of highly doped polysilicon cores coated with oxide and the silicon of the photodiode, the trench cores being biased (CDTI, Capacitor deep trench insulation) with the voltage Vcdti. The application of the voltage Vcdti depletes the photodiode. A midpoint of the Cfw and Ccdti capabilities is connected to node N02.When a photon is received by the photodiode, one or more electron-hole pairs are generated. The electrons (e-) are stored by the Cfwl capacitor while the holes (h+) are stored on the capacitance. Ccdti, which is implemented, for example, in the form of vertically doped zones, by implantation for example, with a type of P-type doping, and biased with Vcdti. The holes are located at node N02 and the voltage at node N02 varies logarithmically as a function of the photogenerated hole current.

[0080] This architecture makes it possible to use the information given by the photogenerated holes instead of having them absorbed without use.

[0081] Figure 6 illustrates a cross-sectional view of one-pixel elements of Figures 2 to 4 according to one embodiment. More particularly, the example shown is a cross-section of an implementation of the bipolar junction transistor BJT1 with the photosensitive element, here a photodiode. The example shown comprises a silicon (Si-N) box 604 doped with a first type of doping, for example, N. This box forms a photodiode in which photogenerated negative charges are stored. The box 604 is surrounded laterally by capacitive deep trench isolation (CDTI) trenches 610.

[0082] An electrode H is connected to the box 604 by a region 612 doped according to a second type of doping, for example P. The electrode H is configured to receive the H+ holes photogenerated in the box 604 and collected in the trenches 610 and evacuate them to ground.

[0083] An electrode B, which forms the base of the BJT1 transistor, is connected to the 604 housing by a 606 region doped according to the second type of doping.

[0084] An electrode C, which constitutes the collector of the BJT1 transistor, is connected to the 604 box by the same region 606.

[0085] Region 606 also connects the collector to a region E which forms the emitter of the BJT1 transistor. Region E is also directly connected to the housing 604 on a lower part of the electrode.

[0086] In the illustrated example, the collector C is formed on each side of the emitter so as to laterally surround the emitter E. In this case, the region 606 laterally surrounds the emitter and connects it to the collector.

[0087] In the example shown, an insulating trench 614 is formed between the electrode H and the base B and it extends vertically from the top of the base and the electrode H to the box 604.

[0088] In the example shown, another insulating trench 615 is formed between the collector C and the base B. It extends vertically from the top of the base and the collector until it stops in the region 606 without going as far as the box 604.

[0089] Figure 7 represents a pixel 700 of the sensor of Figure 1 according to one embodiment. More particularly, pixel 300 represents a possible implementation of all or part of pixels 110(i, ii, iii), 120(i, ii, iii), 130(i, ii, iii).

[0090] Pixel 700 includes circuit 200 of [Fig.2] as well as a contrast amplification stage 701 and an event detection stage 702. The contrast amplification stage 701 connects node N2 and the event detection stage 702.

[0091] In the example shown, the contrast amplification stage 701 includes a capacitor 602 connecting node N2 to an input node of an amplifier 604. An output node N5 of the amplifier 604 is connected to its input node via a transistor 608, for example NMOS, in parallel with a capacitor 606. The transistor 608 is controlled by an output signal from the event detection stage 702 to perform a reset of the contrast amplification stage 701.

[0092] The event detection stage 702 includes, for example, two comparators 610 and 612 configured to compare the signal at node N5 with, respectively, a voltage V+ and a voltage V- that define high and low thresholds. The respective output nodes N6 and N7 of comparators 610 and 612 are connected to a logic block 614 (OR) configured to implement an OR logic function based on the signals present at nodes N6 and N7. The result of the OR function is found at the control node of transistor 608. Transistor 608 is reset when at least one of the two thresholds V+ or V- is exceeded, or, for example, when the voltage at node N5 falls outside the voltage range defined by the voltages V+ and V-.

[0093] The event detection stage 702 further includes a memory block 703, for example a register, of which a storage bit (0, 1, -1) is modified according to the results of comparators 610, 612.

[0094] The example in [Fig. 7] provides a sensor whose operation is event-based, using a bipolar transistor configured as a diode. This sensor improves upon the problem of threshold voltage dispersion in event-based sensors whose pixels operate with one or more MOS transistors instead of the bipolar junction transistor BJT1. This notably reduces the detection of false events.

[0095] Fig. 8 represents an exploded view of an optoelectronic device 800 according to one embodiment.

[0096] The device 800 of [Fig.8] includes for example the sensor 100 of [Fig.1] of which a first set 820 of pixels 110 (i, ii, iii), 120 (i, ii, iii), 130 (i, ii, iii), of the matrix includes 3T type pixels each based on three MOS transistors, and a second set of pixels 811, 812, 814 of the matrix includes (log) pixels with logarithmic response such as those 200, 300, 400, 500, 700 of the examples in Figures 2, 3, 4, 5 and 7.

[0097] In the example shown, the pixels of the second set are arranged along all or part of the diagonals of the pixel matrix of sensor 100. In this example, a Pixel 814 of the second set of pixels is arranged in the second row and third column of a 4x4 pixel array. Pixel 812 of the second set is arranged in the third row and fourth column of the 4x4 pixel array. Pixel 814 of the second set is arranged in the third row and second column of the 4x4 pixel array.

[0098] The example in [Fig. 8] also includes a Bayer 802 grid, in which the blue pixels are represented, for example, by the letter B, the green pixels by the letter G, and the red pixels by the letter R. The Bayer 802 grid has, directly above pixels 811, 812, and 814, transparent portions with no color or very little color. The light intensity loo is received by pixel 811, the light intensity lox is received by pixel 812, and the light intensity loy is received by pixel 814.

[0099] In the illustrated example, a lower tier or substrate 820 is arranged below the pixel matrix and in which are arranged, for example, subtractor circuits, logic processing circuits or asynchronous read circuits (Address event representation, AER).

[0100] The illustrated example includes a single 4*4 set of the pixel matrix, however the same architecture can be replicated over the entire pixel matrix.

[0101] The example in [Fig.8] allows us to obtain both a color image of a scene and information on the contours of objects in that scene.

[0102] [Fig.9] represents an optoelectronic sensor 900 according to one embodiment. The example in [Fig.9] focuses in particular on the processing of signals from pixels 811, 812 and 814 of [Fig.8].

[0103] In the example of [Fig. 9], pixels 812, 811, and 814, with their respective bipolar junction transistors configured as diodes, transform the light intensity received by their respective photosensitive elements. The voltages obtained at the respective nodes N2 are denoted Vox, Voo, and Voy, respectively. The voltages Vox, Voy, and Voo are logarithmic functions of the respective light intensities lox, loo, and loy.

[0104] In the illustrated example, neighboring bipolar junction transistors located in two intersecting diagonals are associated with a subtractor block configured to amplify the signal differences between the two pixels on the two diagonals to measure the diagonal contrast. This allows for a combination of contrast information along two diagonals to perform a pseudo-convolution, known as a "Roberts" convolution, in post-processing to obtain a spatial contrast measurement.

[0105] To do this, in the illustrated example, the sensor 900 includes a subtractor block 910 configured to make a first subtraction Subl=Vx=Vox-Voo=SS.log(Iox)-log(Ioo)=SS.log(Iox / Ioo) and optionally a second subtraction Sub2=Vy=Voy-Voo=SS.log(Ioy)-log(Ioo)=SS.log(Ioy / Ioo); where SS represents the slope under the threshold, and the light sensitivity of the logarithmic stage.

[0106] In the example shown, the sensor 900 includes a block 930 comprising a comparator block 920 configured to compare Vx to a first threshold V+, which is, for example, a voltage. Optionally, the block 930 includes a comparator block 921 configured to compare Vx to a second threshold V-.

[0107] In the example shown, block 930 includes a comparator block 922 configured to compare Vy to the threshold V+, which is, for example, a voltage. Optionally, block 930 includes another comparator block 923 configured to compare Vy to the second threshold V-.

[0108] The results of comparators 920, 921, 922 and 923 are then, for example, processed by an event address representation block 924 (AER logic) for asynchronous reading and contrast detection.

[0109] The subtractor block 910 and block 930 enable the implementation of spatial contrast detection on diagonals of the pixel matrix. This allows the implementation of Roberts convolution from the spatial contrast directly in the pixel matrix.

[0110] The following equations represent true Roberts convolution matrices along the x and y axes of the pixel matrix: [YES] [Math.l] Gx” 1 0 1

[0112] [Math.2] r _M 01 Ho 11

[0113] The following equations represent constraint matrices of Bayer 802 grids:

[0114] [Math.3] BGBGR G. Gx = e 1_______________________J

[0115] [Math.4] BGB Gy^ GRGBB B.

[0116] The following equations represent the Roberts pseudo-convolution matrices The results obtained are along the x and y axes:

[0117] [Math.5] 0 0 .0 -r 0 0.

[0118] [Math.6]

[0119] Roberts pseudo-convolution matrices are to be applied to the green pixels (Gx, Gy) with a contrast calculated along the x and y axes.

[0120] By using the norm of the vector defined by Gx and Gy and comparing it to a threshold N, it is possible to obtain a motion-sensitive edge detection sensor that is also capable of providing an automatic focusing capability (autofocus in English).

[0121] The subtractor block(s) are for example integrated into the same substrate as the pixels as part of the pixel circuits.

[0122] In one example, the bipolar junction transistors of the pixels are made in a first substrate (top tier) and the subtractors and the 930 blocks are made in another substrate (bottom tier). The two substrates are connected by copper pillars, for example.

[0123] The example in [Fig.9], although shown for a set of three logarithmic response pixels having a bipolar junction transistor, can be duplicated for other sets of three logarithmic response transistors having a bipolar junction transistor arranged within the pixel matrix.

[0124] Fig. 10 represents an optoelectronic sensor 1000 according to one embodiment.

[0125] In particular, the optoelectronic sensor 1000 of the example in [Fig. 10] is similar to the sensor 900 with an example implementation of the subtractors 910.

[0126] In the example in [Fig. 10], pixel 812 comprises the photosensitive element DI connected in series with the bipolar junction transistor BJTli. The base of the BJTli transistor is connected to its collector. The voltage Vox is found at the midpoint of the BJTli transistor and the photosensitive element DI.

[0127] In the example in [Fig. 10], pixel 811 includes another photosensitive element D2 connected in series with a bipolar junction transistor BJT2i. The base of transistor BJT2 is connected to its collector. The voltage Voo is found at the midpoint of transistor BJT2i and photosensitive element D2. In this example, the collector and base of transistor BJT2i are connected to a terminal for applying a bias voltage Vbias.

[0128] In the example of [Fig. 10], pixel 814 comprises a photosensitive element D3 connected in series with a bipolar junction transistor BJT3i. The base of transistor BJT3i is connected to its collector. The voltage Voy is found at the midpoint of transistor BJT3i and photosensitive element D3.

[0129] In the illustrated example, the subtraction Subi is obtained with a differential amplifier 1004, one inverting input of which is connected to the midpoint of transistor BJT1 and the photosensitive element D1, and one non-inverting input is connected to the midpoint of transistor BJT2 and the photosensitive element D2. The collector and base of transistor BJT1 are connected to an output of amplifier 1004 so that the voltage Vx is obtained at the output of amplifier 1004.

[0130] In the illustrated example, the subtraction Sub2 is obtained with a differential amplifier 1006, one inverting input of which is connected to the midpoint of transistor BJT3i and the photosensitive element D3, and one non-inverting input is connected to the base of transistor BJT2i. The base and collector of transistor BJT2i and a bias voltage Vbias terminal are connected together. The collector and base of transistor BJT3i are connected to an output of amplifier 1006 so that the voltage Vy is obtained at the output of amplifier 1006.

[0131] In this example the transistors BJTli, BJT2i and BJT3i serve not only for the logarithmic response but they also serve as resistors for the subtraction operations Subi and Sub2 which gives a compact arrangement.

[0132] Figure 11 represents an optoelectronic sensor according to one embodiment. More particularly, the example in Figure 10 represents the sensor 900 with an example of the implementation of the subtractors 910.

[0133] In the example shown, pixels 811, 812 and 814 are each similar to pixel 200. The equivalents of node N2 of pixel of transistors 811, 812 and 814, are respectively called N2_811, N2_812, and N2_814.

[0134] In the illustrated example, the subtraction Subi is obtained with a differential amplifier 1104 whose inverting input is connected to node N2_812 and whose output is connected to node N2_812 via a resistor 1108. In this example, a non-inverting input of the amplifier 1104 is connected to node N2_811. Node N2_811 is further connected to a terminal for applying a voltage Vref or Vbias via a resistor 1110.

[0135] In the illustrated example, the subtraction Sub2 is obtained with a differential amplifier 1106 whose inverting input is connected to the node N2_814 and whose output is connected to the node N2_814 via a resistor 1116. In this example, a non-inverting input of the amplifier 1106 is connected to the node N2_811.

[0136] In this example, pixels 811, 812, and 814 are formed in a top-tier substrate, while the subtraction circuits and block 930 are formed in a bottom-tier substrate. These two substrates are, for example, connected by copper pillars. This reduces the surface area of ​​the edge detection sensor.

[0137] Figure 12 represents an optoelectronic sensor 1200 according to one embodiment. More particularly, the sensor 1200 comprises a pixel matrix where a set of horizontal lines 1202 comprises an alternation of a pixel 1211 (shown in gray) with a logarithmic response, such as that of Figure 3, and four active pixels (APS) of type 3T, 4T, or 5T based solely on MOS transistors and without bipolar junction transistors (shown not grayed out). A second set of lines 1207 comprises only 3T, 4T, or 5T pixels based solely on MOS transistors, without bipolar junction transistors. The first and second sets of lines 1202, 1207 alternate vertically so that, in the pixel matrix shown, the logarithmic response pixels of the 1202 lines having logarithmic response pixels are arranged along diagonals of the matrix.

[0138] In the example shown, contrast amplification and logic processing circuits are arranged at the end of columns of the matrix.

[0139] In the example shown, the logarithmic response pixels 1211, 1212, 1214, located on two intersecting diagonals, form a triangle 1225 between them vertically and are each connected to respective current sources 204_2, 204_1, 204_4.

[0140] In the case where the logarithmic response pixels 1211, 1212, 1214 of the row sets 1202 are each similar to the pixel in [Fig. 3], pixel 1211 has its node N2 connected to an inverting input of the differential amplifier 1104 as described in [Fig. 11], for example, pixel 1212 has its node N2 connected to a non-inverting input of the differential amplifier 1104, and an output of amplifier 1104 is connected to node N2 of pixel 1211 via resistor 1108 as illustrated in [Fig. 11]. As illustrated in [Fig. [Fig. 11], node N2 of transistor 1212 is connected to the application terminal of the voltage Vref via resistor 1110. Pixel 1214 has its node N2 connected to an inverting input of differential amplifier 1106 as described in [Fig. 11] for example.The non-inverting inputs of amplifiers 1104 and 1106 are connected together, and the output of amplifier 1106 is connected to its inverting input via resistor 1116 as shown in [Fig. 3]. The outputs of amplifiers 1104 and 1106 are connected respectively to analog-to-digital converters (ADCs) 1228 and 1218 (4 / 6-bit ADCs).

[0141] In the example of [Fig. 12], in the case where the logarithmic response pixels are similar to the example in [Fig. 3], their transistor 306 is used to send successively the signals from the neighboring pixels, and logarithmic response with bipolar junction transistor, to the subtractor.

[0142] In a first time sequence T1, a first column containing vertical triangles such as the triangle formed by the logarithmic response pixels 1211, 1212 and 1214, is read. Then, in a second time sequence T2, an adjacent column containing vertical triangles formed by the logarithmic response pixels is read, and so on for the entire pixel matrix.

[0143] By alternating the reading, we can alternately measure the contrasts along a first diagonal and then a second diagonal.

[0144] Analog-to-digital converters 1228, 1218 (4 / 6 bit ADC) which are for example of relatively low resolution 4 / 6 bits, make it possible to detect contrasts if the current differences in the pixels due to manufacturing are comparable to the contrast threshold.

[0145] In the case where the current differences due to manufacturing are small compared to the contrast threshold, a converter of only two bits is sufficient, or two comparators instead of four are sufficient per triangle.

[0146] Such an architecture makes it possible to reduce the complexity of pixels, to obtain a smaller footprint, to lower consumption by sharing subtractors, and also to increase the resolution.

[0147] [Fig. 13] represents a pixel 1300 of the sensor of [Fig. 1] according to one embodiment.

[0148] Pixel 1300 is similar to that illustrated in [Fig.5] except that a circuit 1310, similar to a 4T type MOS active pixel, is additionally connected to node N01.

[0149] Circuit 1310 includes a sell transistor, for example of the NMOS type, connecting column 114i, ii, iii to a conduction node of a transistor SF1, for example of the NMOS type. The transistor SF1 has another conduction node, for example, connected to the application terminal of the second reference voltage VDD. Circuit 1310 further includes a Reset transistor, for example of the NMOS type, connecting the application terminal of the second reference voltage VDD to ground GND via a capacitor Cfd. The control node of transistor SF1 is connected, preferably connected, to the midpoint N3 of the Reset transistor and the capacitor Cfd. A TX transistor, for example of the NMOS type, further connects node N3 and node N01.

[0150] In one example, the circuit 1310 and the photosensitive element DI are arranged in a first substrate (top tier). A portion 1320 of the pixel, which includes the BJT2 transistor, the SF2 transistor, and the Sel2 transistor, is arranged in another substrate (bottom tier). These two substrates are, for example, connected by copper pillars.

[0151] In an example not shown, the NO2 nodes of several, for example four, adjacent photosensitive elements are connected in parallel and are connected to a single circuit 1320. This allows combining (binning in English) the intensity of hole currents from several adjacent pixels, for example.

[0152] The example in [Fig. 13] allows us to obtain both an image made from the photogenerated electrons and a contrast image on the same image simultaneously thanks to the use of the photogenerated holes and the use of the bipolar junction transistor processing these photogenerated holes.

[0153] Figure 14 represents the optoelectronic sensor 1300 according to one embodiment. More particularly, Figure 14 represents the arrangement of the circuits 1310 and 1320 of Figure 13 within a sensor.

[0154] In the example shown, the sensor comprises a 1410 Bayer grid positioned above a pixel array like that of [Fig. 13]. The 1310 circuits, labeled "4T", and the photosensitive DI elements of the pixels are each arranged directly above one of the color filters of the 1410 Bayer grid in a first substrate (Top tier). The 1320 circuits, labeled "Logx" and "Logy", are arranged in a substrate (Bottom tier) located below the first substrate. The 1320 circuits labeled "Logx" are arranged along a first diagonal, and the 1320 circuits labeled "Logy" are arranged along a second diagonal at 90° to the first. In the example shown, each 1320 circuit has a footprint equivalent to four of the 1310 circuits. In other words, the hole voltages or currents from four photosensitive elements of the 1310 circuits are added together and used by a single 1320 circuit.

[0155] Not shown, the outputs of the 1310 circuits are connected to a synchronous readout circuit and an analog-to-digital converter (ADC), for example, a 12-bit ADC. The outputs of the 1320 circuits are connected to subtractors such as those illustrated in Figures 10, 11, or 12.

[0156] One advantage of using bipolar junction transistors, as in the 1320 circuits, is that it limits manufacturing-induced threshold voltage variations and provides a minimum current close to that under low light conditions. Another advantage is that the outputs of the analog-to-digital converters correspond to the manufacturing-induced threshold voltage variations. Furthermore, the output variations around the average values ​​correspond to contrast detection.

[0157] Figures 15A to 15E represent an optoelectronic sensor according to one embodiment. More particularly, Figures 15A to 15E represent possible arrangements of pixels 811, 812, 814 of [Fig. 8]. These different arrangements enable automatic focusing.

[0158] In the example in [Fig. 15A], pixel 811 is located in the upper right corner of a 4x4 pixel array, pixel 812 is located on the second row and left edge of this 4x4 pixel array, and pixel 814 is located on the bottom row in the third column. In this example, the other pixels are of type "3T", "4T", or "5T" without a bipolar junction transistor and are alternately dedicated, within the 4x4 pixel array, to the colors green, blue, and red.

[0159] In the example in [Fig. 15B], pixel 811 is located in the third row and fourth column of the 4x4 pixel array. In this example, pixel 812 is located adjacent to pixel 811 in the third row and third column. Pixel 814 is located adjacent to pixel 812 in the fourth row and third column. In this example, the other pixels are of type "3T", "4T", or "5T" without a bipolar junction transistor and are alternately dedicated, within the 4x4 pixel array, to the colors green, blue, and red.

[0160] In the example in [Fig. 15C], pixels 811, 812, and 814 are arranged in the same way as in [Fig. 15B]. In this example, four pixels of type "3T", "4T", or "5T" and dedicated to the color green are arranged in a top-left quadrant of 2 x 2 pixels within the 4 x 4 pixel set. Four pixels of type "3T", "4T", or "5T" and dedicated to the color red are arranged in a top-right quadrant, and four pixels of type "3T", "4T", or "5T" and dedicated to the color blue are arranged in a bottom-left quadrant. The bottom-left corner pixel is of type "3T", "4T", or "5T" and dedicated to the color green.

[0161] In the example in [Fig. 15D], pixels 811, 812, and 814 are arranged in the same way as in [Fig. 15B] but are centered in the middle of the 4x4 pixel array. In this example, three pixels of type "3T", "4T", or "5T", dedicated to the color green, are arranged in a top left quadrant of the 4x4 pixel array. Three pixels of type "3T", or "4T" or "5T" and dedicated to the color red are arranged on a top right quadrant of the 4*4 pixel set, three pixels of type "3T", or "4T" or "5T" and dedicated to the color blue are arranged on a bottom left quadrant of the 4*4 pixel set, and four pixels of type "3T", or "4T" or "5T" and dedicated to the color green are arranged on a bottom right quadrant of the 4*4 pixel set.

[0162] In the example of [Fig.15E], pixels 811, 812 and 814 are arranged in the same way as in [Fig.15D] except that a pixel 1502, similar to pixels 812 or 814 but whose photosensitive element is sensitive to all or part of the infrared spectrum, is arranged in contact with pixels 812 and 814 on the third row and the third column of the set of 4*4 pixels.

[0163] Figure 16 represents an optoelectronic sensor 1600 according to one embodiment. The sensor 1600 comprises the same pixels 811, 812 and 814 as Figure 9, as well as the same subtractor block 910.

[0164] In the example shown, the 1600 sensor includes a 1620 standard calculation block configured to calculate the square of the output value Vx of the subtractor as well as the square of the value Vy.

[0165] In the example shown, the 1600 sensor includes a 1630 block configured to add the square of the Vx value to the square of the Vy value and take the square root of this sum. The norm is thus calculated.

[0166] In the example shown, the sensor 1600 includes a comparator block 1630 which compares the calculated standard with one or more thresholds V+, V-.

[0167] The illustrated example allows for spatial contrast detection, which differs from temporal contrast detection linked to events.

[0168] The different pixel embodiments described can be applied to cameras, image acquisition devices, smartphones, cameras, but also radars or equivalents for image acquisition in non-visible domains.

[0169] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. In particular, the pixels in the first set of pixels in the example in [Fig. 8] can also be 4T or 5T type pixels implementing 4 or 5 MOS transistors respectively, without bipolar junction transistors mounted as diodes or with bipolar transistors but not mounted as diodes. The pixels shown in non-gray in the example in [Fig. 12] can also be 3T, 4T, or 5T type pixels implementing 3, 4, or 5 MOS transistors respectively, without bipolar junction transistors mounted as diodes or with bipolar transistors but not mounted as diodes. The 3T pixels in [Fig.14] can also be of type 4T or 5T implementing respectively 4 or 5 MOS transistors without bipolar junction transistors mounted as diodes or with bipolar transistors but not mounted as diodes.

[0170] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, a person skilled in the art will be able to place the pixels having a bipolar junction transistor (BJT) configured as a diode within the pixel matrix according to their knowledge. Furthermore, the number of pixels having a BJT configured as a diode per pixel matrix can vary from a single pixel to all the pixels in the matrix. Spatial contrast detection can also be performed with groups of only two BJT pixels configured as diodes instead of of three, but this results in lower resolution. Diode-mounted bipolar junction pixels can be sensitive to wavelengths other than visible light, such as infrared, ultraviolet, or microwaves. Diode-mounted bipolar junction pixels can also be used individually or in groups without being arranged in a pixel matrix.

[0171] A person skilled in the art will be able to implement, according to their knowledge, NPN or PNP type bipolar junction transistors, and will vary the connections of the circuits accordingly.

Claims

Demands

1. Logarithmic response pixel having a photosensitive element (Dl) connected to at least one bipolar junction transistor (BJT1, BJT2, BJT3, BJTli, BJT2i, BJT3i) mounted as a diode.

2. Pixel according to claim 1, wherein the base and a conduction node of the bipolar junction transistor (BJT1) are connected.

3. Pixel according to claim 1 or 2, wherein the photosensitive element (Dl) is connected in series to the bipolar junction transistor (BJT1) between a first terminal and a second terminal, the second terminal being connected to a terminal for applying a first reference voltage (GND).

4. Pixel according to the preceding claim, wherein the first terminal is connected to an application terminal of a second reference voltage (VDD) different from the first reference voltage.

5. Pixel according to claim 3 or 4, wherein the pixel comprises a first transistor (202), of the MOS type, connecting the application terminal of the second reference voltage (VDD) and a first node (N2) connected to a current source (204), a control node of the first transistor (202) being connected to the midpoint (NI) of the photosensitive element (D1) and the bipolar junction transistor (BJT1); the pixel preferably comprising a second transistor (306), of the MOS type, connecting the first node (N2) to the current source (204), the current source (204) being preferably connected to a column of an optoelectronic sensor (100);or wherein the pixel comprises: a first transistor (202), of MOS type, connecting the application terminal of the second reference voltage (VDD) and a first node (N2), a second transistor (306), of MOS type, connecting the first transistor (202) to a current source (204), and a third transistor (402) in series with a storage capacitor (410) between the first terminal and the second terminal, a control node of the third transistor (402) being connected to the midpoint (NI) of the photosensitive element (D1) and the bipolar junction transistor (BJT1), a control node of the first transistor (202) being connected to the midpoint (N4) of the third transistor (402) and the; storage capacity (410), a fourth transistor (408) connecting the midpoint (N4) of the third transistor and the storage capacity to the second terminal (Gnd).

6. Pixel according to the preceding claim, comprising a transimpedance capacitive amplification stage (701) linking an event detection stage (702) and the first node (N2), the event detection stage (702) being configured to modify a value (0, 1, -1) of a storage bit as a function of the voltage present at the output of the transimpedance capacitive amplification stage (701).

7. Pixel according to the preceding claim, wherein the event detection stage (702) comprises at least one comparator circuit (610, 612) configured to detect a variation in the output voltage of the transimpedance capacitive amplification stage (701) with respect to a threshold or voltage range and reset the capacitive amplification stage (701) according to this variation.

8. Pixel according to claim 2, wherein: - the photosensitive element is configured to photogenerate holes and is connected in series to the bipolar junction transistor (BJT2) between a first terminal and a second terminal, the second terminal being connected to an application terminal of a first reference voltage; - the bipolar junction transistor (BJT2) is a PNP type transistor; and - the base and emitter of the bipolar junction transistor (BJT2) are connected together at the second terminal, the photosensitive element being, preferably, connected to the first terminal and the first reference voltage being -VDD.

9. Method of operating a pixel according to any one of claims 1 to 8, comprising generating a logarithmic response of the bipolar junction transistor (BJT1), following light excitation of the photosensitive element.

10. Optoelectronic sensor comprising a pixel array having linear response pixels, for example of type 3T, 4T or 5T, and logarithmic response pixels according to any one of claims 1 to 8.

11. Optoelectronic sensor according to the preceding claim in which the logarithmic response pixels are arranged along diagonals of the matrix.

12. An optoelectronic sensor according to claim 10 or 11 in their dependence on claim 4, wherein the sensor comprises: - at least one subtractor block (910) configured to perform a first subtraction of a voltage (Vox), present on the midpoint of the photosensitive element and the junction bipolar transistor of a first pixel (812) with logarithmic matrix response, with a voltage (Voo) present on the midpoint of the photosensitive element and the junction bipolar transistor of a second pixel (811) with logarithmic matrix response; - a comparator block (920, 921) configured to compare the result of the first subtraction to a first and a second threshold (V+, V-); and - an event-based readout circuit (924) connected to the comparator block;or in which the sensor comprises: - at least one subtractor block configured to perform a first subtraction of a voltage (Vox), present on the first node (N2_812) of a first pixel (812) with logarithmic response of the matrix, with a voltage (Voo) present on the first node (N2_811) of a second pixel with logarithmic response of the matrix; - a comparator block (920, 921) configured to compare the result of the first subtraction to a first and a second threshold (V+, V-); and - an event-based readout circuit (924) connected to the comparator block.

13. An optoelectronic sensor according to the preceding claim, wherein: - the subtractor block is further configured to perform a second subtraction of the voltage (Voo) present at the midpoint of the photosensitive element and the logarithmic response bipolar junction transistor of the second pixel (811) of the matrix, with a voltage (Voy) present at the midpoint of the element photosensitive and bipolar junction transistor of a third pixel (814) with logarithmic matrix response; - the comparator block being configured to compare the result of the second subtraction with said first threshold and said second threshold; Or in which: - the subtractor block is further configured to perform a second subtraction of the voltage (Voo) present on the first node (N2_811) of the second pixel with logarithmic response of the matrix, with a voltage (Voy) present on the first node (N2_814) of a third pixel (814) with logarithmic response of the matrix; - the comparator block being configured to compare the result of the second subtraction with said first threshold and said second threshold.

14. Optoelectronic sensor according to claim 12 or 13, wherein the subtractor block comprises at least one differential amplifier (1004) of which: - an output is connected to the first terminal of the first pixel (812); - an inverting input (-) is connected to the midpoint of the photosensitive element and the bipolar junction transistor of the first pixel (812); - a non-inverting input (+) is connected to the midpoint of the photosensitive element and the bipolar junction transistor of the second pixel (811).

15. Optoelectronic sensor according to claim 12 or 13, wherein the subtractor block comprises at least one differential amplifier (1104) of which: - an output is connected to the first node (N2_812) of the first pixel via a first resistor (1108); - an inverting input (-) is connected to the first node (N2_812) of the first pixel; and - a non-inverting input (+) is connected to the first node (N2_811) of the second pixel and to a terminal applying a third reference voltage (Vref) via a second resistor (1110).

Images