METHOD FOR MANUFACTURING A BEARING SUBSTRATE AND BEARING SUBSTRATE

Abstract

METHOD FOR MANUFACTURING A BEARING SUBSTRATE AND BEARING SUBSTRATE The invention relates to a method for manufacturing a bearing substrate comprising the following steps: providing a temporary substrate formed of a first material and comprising a first face, a second face opposite the first face and a lateral surface connecting the first and second faces; depositing on the temporary substrate a semiconducting support layer of polycrystalline silicon carbide, said first material being different from polycrystalline silicon carbide, the semiconducting support layer being deposited at least on the first face and on the lateral surface of the temporary substrate; cutting the temporary substrate along a plane parallel to the plane of said temporary substrate so as to obtain a part of the temporary substrate, called the reduced temporary substrate, covered with the semiconducting layer on its first face and on its lateral surface;remove the reduced temporary substrate so as to obtain the carrier substrate formed by the semiconductor support layer previously deposited on the first face and on the lateral surface of the reduced temporary substrate, said carrier substrate having a base wall and a lateral wall extending from the base wall, the internal volume delimited by the base wall and the lateral wall being hollow. Figure to be published with the abbreviation: none;

Description

Title of the invention: METHOD FOR MANUFACTURING A BEARING SUBSTRATE AND BEARING SUBSTRATE TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of advanced substrates used as supports for the manufacture of electronic components. The invention relates more particularly to a method for manufacturing a carrier substrate. The invention also relates to a carrier substrate obtained, in particular, by the manufacturing method. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] It is common to use thin film transfer solutions to develop multilayer structures comprising a high crystalline quality semiconductor useful layer on a lower crystalline quality semiconductor support substrate, the useful layer then being used to form electronic components.

[0003] A well-known thin-film transfer solution is the Smart Cut™ process, based on light ion implantation and direct bonding. In addition to the economic advantages related to streamlining the use of high-quality material for the active layer, the multilayer structure can also provide advantageous properties, for example, related to thermal conductivity, electrical conductivity, or the mechanical compatibility of the support substrate.

[0004] In the field of power electronics, for example, it is advantageous to establish electrical conduction between the useful layer and the supporting substrate, in order to form vertical components, which are generally less bulky than lateral components.

[0005] The Smart Cut™ process makes it possible, in particular, to fabricate a multilayer structure comprising a thin layer of monocrystalline silicon carbide (SiC) (mono-SiC), taken from a mono-SiC donor substrate, in direct contact with a polycrystalline SiC (poly-SiC) support substrate. Such a multilayer structure allows vertical electrical conduction, thus enabling the fabrication of vertical power electronic components.

[0006] Interest in SiC has increased considerably in recent years because power electronic components and integrated power systems based on monocrystalline SiC can handle much higher power density than their silicon counterparts, and with smaller active area dimensions.

[0007] The substrate, which must be of sufficient thickness to allow for component formation, is ultimately thinned to obtain the complete set of electronic components ready for integration. Even if the substrate is of lower quality, the thinning steps and material loss remain cost contributors that are desirable to eliminate.

[0008] French patent FR3120736B1 describes a solution to this problem, proposing a manufacturing process for a mono-SiC multilayer structure on poly-SiC, comprising: • the provision of a temporary graphite substrate; • the deposition of a poly-SiC support layer on one or both main faces of the temporary substrate, but also on its lateral surface; • the transfer of a useful layer in mono-SiC onto the support layer, this transfer implementing a bonding by molecular adhesion; • the formation of an active layer of mono-SiC doped on the useful layer; and • the removal of the temporary graphite substrate and the poly-SiC layer on the lateral surface.

[0009] The temporary graphite substrate, a material much less expensive than poly-SiC and having a coefficient of expansion close to that of poly-SiC, makes it possible to deposit only the desired thickness of poly-SiC (and therefore to avoid a loss of poly-SiC by thinning) and to have a reduced vertical resistivity while maintaining an overall rigidity without risk of deformation during handling of the substrate.

[0010] However, the above solution has the disadvantage of requiring the graphite to be protected by a protective layer. Indeed, in the absence of a controlled atmosphere, i.e., without oxygen, the graphite begins to burn at temperatures of around 400-600°C, leading to a risk of contamination. Summary of the invention

[0011] The invention relates to a method for manufacturing a carrier substrate which makes it possible to overcome the cost problems associated with thinning a thick polycrystalline SiC support substrate and material loss, while maintaining sufficient rigidity and limiting the risks of contamination associated with the use of a material such as graphite.

[0012] To this end, the invention relates in particular to a method for manufacturing a carrier substrate comprising the following steps: • provide a temporary substrate made of a first material and comprising a first face, a second face opposite the first face and a lateral surface connecting the first and second faces; • deposit on the temporary substrate a semiconducting support layer of polycrystalline silicon carbide, said first material being different from the polycrystalline silicon carbide, the semiconductor support layer being deposited at least on the first face and on the lateral surface of the temporary substrate; • cut the temporary substrate along a plane parallel to the plane of said temporary substrate so as to obtain a part of the temporary substrate, called reduced temporary substrate, covered with the semiconducting layer on its first face and on its lateral surface; • remove the reduced temporary substrate so as to obtain the carrier substrate formed by the semiconducting support layer previously deposited on the first face and on the lateral surface of the reduced temporary substrate, said carrier substrate having a base wall and a lateral wall in the extension of the base wall, the internal volume delimited by the base wall and the lateral wall being hollow.

[0013] Contrary to what is described in particular in patent FR3120736B1, the invention consists of taking advantage of the polycrystalline silicon carbide lateral surface to obtain a load-bearing substrate with sufficient rigidity due to the presence of said lateral surface. Such a solution goes against what a person skilled in the art would do, who would tend to remove this lateral surface at the same time as the temporary substrate material, for example, graphite. The resulting support substrate makes it possible, in particular, to subsequently transfer a useful layer onto said load-bearing substrate, for example by bonding, after the temporary substrate material has been removed, thus avoiding the risk of contamination by the latter.

[0014] The temporary substrate cutting step makes it possible to obtain a reduced temporary substrate with a thickness less than the initial thickness before cutting, the thickness being measured in a direction perpendicular to the plane of the substrate. This temporary substrate cutting step makes it possible to define the height of the lateral surface of the supporting substrate and thus adapt the desired stiffening effect.

[0015] It should also be noted that the process according to the invention makes it possible to produce different thicknesses of polycrystalline silicon carbide on the first base face and on the lateral surface, in order to obtain the desired rigidity. The load-bearing substrate obtained by the process according to the invention also makes it possible, as in the case of the structure described in patent FR3120736B1, to deposit only the desired thickness of poly-SiC, thus avoiding loss of poly-SiC through thinning and resulting in reduced vertical resistivity.

[0016] In addition to the characteristics mentioned in the preceding paragraphs, the manufacturing process according to the invention may have one or more additional characteristics from among the following, considered individually or according to all technically possible combinations: • The first material is graphite. • The thickness of the semiconductor layer deposited on the first face is different from the thickness of the semiconductor layer deposited on the lateral surface, the thickness of the semiconductor layer deposited on the lateral surface being preferentially greater than the thickness of the semiconductor layer deposited on the first face. • The thickness of the semiconductor layer deposited on the first face is between 50 microns and 200 microns. • The thickness of the semiconductor layer deposited on the lateral surface is between 0.5 mm and 20 mm and preferably between 0.5 mm and 5 mm. • The thickness of the reduced temporary substrate is between 10 microns and 200 microns and preferably between 10 microns and 100 microns. • The process according to the invention includes a step of transferring a useful layer to the free surface of the semiconductor support layer. • The transfer is a transfer by gluing. • The transfer step is carried out after the step of removing the reduced temporary substrate • The process according to the invention includes a step of treating the free surface of the semiconductor support layer deposited on the first face. • This free surface treatment step is carried out before the cutting step. • The thickness of the semiconductor support layer deposited on the first face after the surface treatment step is between 10 and 150 microns. • The temporary substrate cutting stage is carried out using a diamond saw or a laser. • The step of removing the reduced temporary substrate is carried out by sandblasting or burning. • The deposition of the semiconductor support layer is also carried out on the second side of the temporary substrate.

[0017] The present invention also relates to a carrier substrate formed by a semiconducting support layer of polycrystalline silicon carbide, said semiconducting support layer comprising a base wall and a side wall in extension of the base wall, the internal volume delimited by the base wall and the side wall being hollow.

[0018] The carrier substrate according to the invention may comprise one or more complementary features defined with reference to the process according to the invention, considered individually or in all technically possible combinations. BRIEF DESCRIPTION OF FIGURES

[0019] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which Figures [Fig. 1], [Fig. 2], [Fig. 3], [Fig. 4], [Fig. 5], and [Fig. 6] illustrate an example of an embodiment of the process for manufacturing a carrier substrate according to the invention. Figure [Fig. 5] also illustrates an example of a carrier substrate according to the invention.

[0020] For clarity, identical or similar elements are identified by identical reference numerals throughout the figures. DETAILED DESCRIPTION

[0021] Figures 1 to 5 illustrate an example of an embodiment of the manufacturing process for a carrier substrate according to the invention

[0022] As illustrated in [Fig.1], the manufacturing process of the carrier substrate according to the invention includes a first step 100 of supplying a temporary substrate 1 formed of a first material.

[0023] The temporary substrate 1 comprises: • a first face, referred to interchangeably as the front face, • a second face 1b, referred to interchangeably as the back face, opposite the first face and • a lateral surface connecting the first and second faces 1a and 1b.

[0024] Advantageously, the first material has a coefficient of thermal expansion CTE1 between 40% and 150% of the coefficient of thermal expansion CTE2 of polycrystalline silicon carbide, referred to indifferently as poly-SiC, which will subsequently be deposited on the temporary substrate 1. Thus, the coefficient of thermal expansion of the first material is matched to the coefficient of thermal expansion of poly-SiC, which limits the mechanical stresses in the structure during high-temperature operations or treatments.

[0025] The first material can be graphite, silicon, polycrystalline aluminium nitride (AIN), tungsten (W) or porous polycrystalline silicon carbide (poly-SiC).

[0026] According to a preferred embodiment, the first material is graphite. Graphite may, in particular, have a grain size between 4 µm and 35 µm, a porosity between 6% and 17%, and a coefficient of thermal expansion between 4 x 10⁶ / °C and 5 x 10⁶ / °C. These characteristics are specifically chosen to to provide an excellent seed for the deposition of a polycrystalline silicon carbide support semiconductor layer.

[0027] The temporary substrate 1 can be in the form of a circular plate. The first and second faces 1a and 1b of the temporary substrate 1 are preferably flat and parallel to each other. The lateral surface 1 of the temporary substrate 1 connects the first and second faces 1a and 1b at their periphery. This can therefore also be referred to as the "peripheral edge" 1.

[0028] The temporary substrate 1 advantageously has a thickness e greater than 100 pm. The thickness of the temporary substrate is measured along a direction perpendicular to the plane of the first and second faces 1a and 1b.

[0029] As illustrated in [Fig.2], the manufacturing process of the carrier substrate according to the invention continues with a step 101 of deposition of a semiconducting layer 2 of poly-SiC support.

[0030] The semiconductor layer 2 comprises at least a first portion 2a deposited on the first face la of the temporary substrate 1 and a second portion 2b deposited on the lateral surface le of the temporary substrate 1. According to the embodiment illustrated in [Fig.2], and optionally, the semiconductor layer 2 here comprises a third portion 2c deposited on the second face 1b of the temporary substrate 1.

[0031] Prior to the deposition of the semiconductor support layer 2, cleaning operations may be applied to the temporary substrate 1 to remove all or part of particulate, metallic or organic contaminants potentially present on its first and second faces la and 1b as well as on its lateral surface le.

[0032] The deposition can be carried out by any known technique, in particular by chemical vapor deposition (CVD), at a temperature of approximately 1100°C to 1400°C in the case of poly-SiC. Examples of thermal CVD techniques include atmospheric pressure CVD (APCVD) or low pressure CVD (LPCVD). Plasma-enhanced CVD (PECVD) can also be used.

[0033] It should be noted that if the support semiconductor layer 2 is to ensure vertical electrical conduction, it must have low resistivity. To guarantee this latter property of electrical conduction (low resistivity), necessary for example for vertical power components, the support semiconductor layer 2 can be doped of type n or p as required.

[0034] Alternatively, the semiconductor support layer 1 can be semi-insulating (resistivity between 102 Q.cm and 104 Q.cm), or even highly resistive (resistivity between 104 Q.cm and 108 Q.cm), particularly in the case of lateral power components or radio frequency (RF) components.

[0035] The first portion 2a of the semiconductor support layer 2 preferably has a thickness el between 50 pm and 200 pm.

[0036] The thickness e2 of the second portion 2b of the semiconductor support layer 2 is, for example, between 0.5 mm and 5 mm. It is preferably greater than the thickness of the first portion 2a.

[0037] Generally, the thickness of a deposited layer is measured along a direction perpendicular to the surface on which it is deposited.

[0038] Obtaining a thickness el of the first portion 2a different from the thickness e2 of the second portion 2b can, for example, be achieved by exposing more to the flux of reactants the surface on which a greater thickness is desired.

[0039] As mentioned previously, the semiconductor layer 2 optionally includes a third portion 2c deposited on the second face 1b of the temporary substrate 1. Advantageously, the thickness e3 of the third portion is equal to the thickness el of the first portion 2a of the support semiconductor layer 2.

[0040] According to an advantageous but not limiting embodiment, surface treatment can be performed on the first and second portions 2a and 2b, and optionally on the third portion 2c. For example, the second portion 2b deposited on the lateral surface can be ground to correct the thickness e2. Treatment of the free surface of the first portion 2a, for the purpose of transferring a useful layer onto the free surface by bonding, can also be carried out after the deposition step and before the cutting step illustrated in [Fig. 3]. This surface treatment aims to improve the surface roughness of the first poly-SiC portion 2a. Conventional chemical etching and / or mechanical grinding and / or chemical polishing techniques can thus be implemented to achieve the desired surface roughness.The thickness el of the first portion 2a of the poly-SiC semiconductor layer is thus reduced to become a thickness e6 illustrated in [Fig.3]: the thickness e6 can for example be between 10 and 150 microns.

[0041] As illustrated in [Fig.3], the manufacturing process of the carrier substrate according to the invention continues with a step 102 of cutting or slicing on the upper part of the temporary substrate 1 on which the semiconductor support layer 2 is deposited in a plane PI parallel to the plane of the temporary substrate 1.

[0042] This cutting step makes it possible to obtain a part 3 of the temporary substrate 1, called the reduced temporary substrate, covered with the first portion 2a of the semiconductor support layer on its first face la and with a part of the second portion 2b of the semiconductor support layer on its lateral surface, said reduced temporary substrate 3 consequently having a thickness e4 strictly less than the initial thickness e of the temporary substrate 1. The assembly comprising the reduced temporary substrate 3 covered by the first and second portions 2a and 2b is designated by the reference 4. The thickness e4 of the reduced temporary substrate 3 is for example between 10 microns and 200 microns and preferably between 10 microns and 100 microns.

[0043] The cutting step can be carried out using a laser, for example according to the "Laser Microjet®" technology developed by Synova®. This technology combines a laser with a very fine water jet that precisely guides the laser beam by total internal reflection (similar to optical fibers). The water jet continuously cools the cutting area and effectively removes debris.

[0044] The cutting step can also be carried out using a diamond saw.

[0045] A second cut can be made on the lower part of the temporary substrate 1 on which the support semiconductor layer 2 is deposited along a plane P2 parallel to the plane of the temporary substrate 1 when the third portion 2c of the support semiconductor layer 2 is present.

[0046] This second cutting step makes it possible to obtain a lower part 5 of the temporary substrate 1, called the reduced second temporary substrate, covered with the third portion 2c of the semiconductor support layer on its second face 1b and with a part of the second portion 2b of the semiconductor support layer on its lateral surface, said reduced second temporary substrate 5 having a thickness e5 strictly less than the initial thickness e of the temporary substrate 1. The assembly comprising the reduced second temporary substrate 5 covered with the first and second portions 2a and 2b is designated by reference numeral 6. The thickness e5 of the reduced temporary substrate 3 is for example between 10 microns and 200 microns and preferably between 10 microns and 100 microns.

[0047] As illustrated in [Fig.4], the manufacturing process of the carrier substrate according to the invention continues with step 103 of preserving assembly 4. It will be noted that the remainder of the description will be illustrated with reference to assembly 4 comprising the reduced temporary substrate 3 covered with the first and second portions 2a and 2b, it being understood that the same steps can be applied to assembly 6 comprising the second reduced temporary substrate 5 covered with the first and second portions 2a and 2b.

[0048] As illustrated in [Fig. 5], the manufacturing process for the carrier substrate according to the invention continues with step 104 of removing the reduced temporary substrate 3 present in the assembly 4. Once this removal has been carried out, the process makes it possible to obtain a poly-SiC carrier substrate 7 comprising the first portion 2a of the semiconductor support layer, referred to as the base wall, and the second portion 2b of the semiconductor support layer, referred to as the side wall. The side wall 2b is in line with the base wall 2a. The internal volume 8 delimited by the base wall 2a and the side wall 2b is hollow (i.e., empty of material) after the removal of the first material forming the reduced temporary substrate 3. The removal of the reduced temporary substrate 3 can, for example, be carried out by an abrasive blasting or burning step. At the end of this step 104, an example of a load-bearing substrate according to the invention is obtained, the various dimensions of which can be adjusted according to the desired functions, and in particular the stiffening effect: thus, as we saw previously, the respective thicknesses e2 and e6 of the side wall 2b and the base wall 2a, as well as the additional thickness e4 due to the presence of the side wall 2b and corresponding substantially to the thickness of the removed reduced temporary substrate, are adjusted during the various steps described above.It is also possible to carry out a surface treatment, even a minor one, on the rear face 9 of the base wall 2a in order to remove the nucleation layer whose properties, particularly thermal and electrical, are not optimal and which may also be a layer under stress.

[0049] The manufacturing process according to the invention can then proceed with a step of transferring a useful layer 8 onto the support substrate 7. This step 105 is illustrated in [Fig. 6]. More specifically, the transfer of the useful layer 8 is carried out on the free surface of the first portion 2a of the poly-SiC semiconductor layer formed here by the base wall 2a of the support substrate 7. The transfer of the useful layer 8 can be carried out by any known layer transfer technique. However, transfer techniques employing molecular adhesion, and consequently an adhesion interface, are preferred.

[0050] Molecular adhesion bonding does not require an adhesive material, as bonds are established at the atomic scale between the surfaces being joined. Several types of molecular adhesion bonding exist, differing in particular by the conditions of temperature, pressure, atmosphere, or pretreatments prior to contacting the surfaces. Examples include room-temperature bonding with or without prior plasma activation of the surfaces to be joined, atomic diffusion bonding (ADB), and surface-activated bonding (SAB).

[0051] The useful layer 8 can be transferred directly onto the free surface of the first portion 2a of the poly-SiC semiconductor layer or via an intermediate layer. The intermediate layer can be formed on the side of the useful layer 8 and / or on the side of the support substrate 7, to promote bonding, in particular by smoothing out residual roughness or surface defects present on the faces to be joined.

[0052] When the intermediate layer is metallic (e.g., tungsten) or made of semiconductor material, for example a doped semiconductor material (e.g., silicon), it can Furthermore, it promotes vertical electrical conduction. The intermediate layer can alternatively be an electrically insulating layer (e.g., silicon oxide, silicon nitride, etc.) or an intrinsically conductive semiconductor material for applications not requiring vertical electrical conduction. The intermediate layer can also be a metalloid layer.

[0053] Advantageously, and as is known with reference to the Smart Cut™ process, transfer step 105 comprises the following successive substeps: • the introduction of light species (typically hydrogen ions and / or helium ions), preferably by ion implantation, into a donor substrate to form a buried fragile plane, the buried fragile plane defining with the front face of the donor substrate the useful layer 8; • the assembly of the front face of the donor substrate onto the free surface of the first portion 2a of the poly-SiC semiconductor layer, directly or via an intermediate layer, by molecular adhesion bonding, along a bonding interface; and • the separation along the buried fragile plane to transfer the useful layer 8 onto the free surface of the first portion 2a of the poly-SiC semiconductor layer, for example by applying a heat treatment at a temperature between 800 °C and 1200 °C.

[0054] The assembly substep may include, prior to bringing the faces to be assembled into contact, cleaning, surface activation or other surface preparation operations, which may promote the quality of the bonding interface (low defect, high adhesion energy).

[0055] The useful layer 8 can be, for example, made of silicon carbide, gallium(III) oxide (Ga2O3), an IILV semiconductor material (such as GaN), or an ILVI semiconductor material. The semiconductor material of the useful layer 8 is preferably single-crystal. Furthermore, it can be intrinsic or doped, of type n or type p (as required).

[0056] The thickness of the useful layer 8 can be between 100 nm and 1500 nm.

[0057] As is known, the process according to the invention may then include a step of forming an active layer on the useful layer 8. The active layer may be deposited by epitaxial growth. The manufacturing process according to the invention may further include a step of fabricating one or more electronic components on and / or in the active layer. The electronic components may be, for example, transistors or other high-voltage and / or high-frequency components. It should be noted that these steps may be carried out at high temperatures (i.e., greater than or equal to 1600°C), particularly due to the presence of heat treatments: the absence of the first material, for example graphite, which could lead to risks of Contamination thus represents an advantage provided by the manufacturing process and the carrier substrate according to the invention. Another advantage linked to the prior removal of the first material, such as graphite, is to avoid damaging the components during this removal. Once the components are made, it is possible either to cut the components individually without removing the side wall 2b (which is ring-shaped in the case of a carrier substrate 7 shaped like a circular wafer) or to attach a handle to the upper face of the carrier substrate 7 (on which the components are formed) to remove, for example by grinding, the side wall 2b.

[0058] As mentioned previously, assembly 6 shown in [Fig.3] can be used in the same way as assembly 4 in order to obtain a second carrier substrate.

[0059] The manufacturing process of the carrier substrate and the carrier substrate are not limited to the implementation method described previously in relation to the figures.

[0060] Thus, even though the manufacturing process has been described with a transfer of the useful layer carried out once the substrate bearing the [Fig.5] has been made, it is also possible to carry out this transfer of the useful layer after the step of deposition of the poly-SiC semiconductor layer (the latter having undergone a surface treatment in view of carrying out the transfer) and before the cutting of the temporary substrate, it is also possible to carry out this transfer of the useful layer after the cutting of the temporary substrate and before the removal of the first material such as graphite.

Claims

Demands

1. A method for manufacturing a carrier substrate comprising the following steps: - providing (100) a temporary substrate (1) formed of a first material and comprising a first face (la), a second face (1b) opposite the first face (la) and a lateral surface (le) connecting the first and second faces (la, 1b); - depositing (101) on the temporary substrate (1) a semiconducting support layer (2) of polycrystalline silicon carbide, said first material being different from polycrystalline silicon carbide, the semiconducting support layer being deposited at least on the first face (la) and on the lateral surface (le) of the temporary substrate (1);- cut (102) the temporary substrate (1) along a plane (PI) parallel to the plane of said temporary substrate (1) so as to obtain a part (3) of the temporary substrate, called the reduced temporary substrate, covered with the semiconducting layer (2a, 2b) on its first face (la) and on its lateral surface (le); - remove (104) the reduced temporary substrate (3) so as to obtain the carrier substrate (7) formed by the semiconducting support layer previously deposited on the first face and on the lateral surface of the reduced temporary substrate, said carrier substrate having a base wall (2a) and a lateral wall (2b) in the extension of the base wall, the internal volume (8) delimited by the base wall (2a) and the lateral wall (2b) being hollow.;

2. The method according to claim 1 wherein the first material is graphite.

3. A method according to any one of the preceding claims, wherein the thickness of the semiconductor support layer deposited on the first face is different from the thickness of the semiconductor support layer deposited on the lateral surface, the thickness of the semiconductor support layer deposited on the lateral surface being preferably greater than the thickness of the semiconductor support layer deposited on the first face.

4. A method according to any one of the preceding claims wherein the thickness of the semiconductor support layer deposited on the first face is between 50 microns and 200 microns.

5. A method according to any one of the preceding claims wherein the thickness of the semiconductor support layer deposited on the lateral surface is between 0.5 mm and 20 mm and preferably between 0.5 mm and 5 mm.

6. A method according to any one of the preceding claims wherein the thickness of the reduced temporary substrate is between 10 microns and 200 microns and preferably between 10 microns and 100 microns.

7. A method according to any one of the preceding claims comprising a step of transferring a useful layer onto said carrier substrate.

8. A method according to the preceding claim in which the transfer is a transfer by gluing.

9. A method according to claim 7 or 8, wherein the transfer step is carried out after the step of removing the reduced temporary substrate

10. A method according to any one of the claims comprising a surface treatment step of the semiconductor support layer deposited on the first face.

11. A method according to the preceding claim in which said surface treatment step is carried out before the cutting step.

12. A method according to any one of claims 10 or 11 wherein the thickness of the semiconductor support layer deposited on the first face after the surface treatment step is between 10 and 150 microns.

13. A method according to any one of the preceding claims wherein the step of cutting the temporary substrate is carried out by means of a diamond saw or a laser.

14. A method according to any one of the preceding claims wherein the step of removing the reduced temporary substrate is carried out by sandblasting or by burning.

15. A method according to any one of the preceding claims wherein the deposition of the semiconductor support layer is also carried out on the second face of the temporary substrate.

16. Carrier substrate formed by a semiconducting support layer of polycrystalline silicon carbide, said semiconducting support layer comprising a base wall and a side wall in extension of the base wall, the internal volume delimited by the base wall and the side wall being hollow.

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