Method for manufacturing an electronic device

Abstract

Method for making an electronic device This description relates to a method for making an electronic device, the method comprising the following successive steps: a) forming, on a support substrate (101), an electropolishing stack (109) comprising: – a first sacrificial semiconductor layer (117); – a second charge-carrying semiconductor layer (113); and – a third semiconductor layer (115) protecting the second layer (113), the third layer (115) being interposed between the first (117) and second (113) layers and having a doping level strictly lower than those of the first (117) and second (113) layers; b) forming, on the side of a face of the electropolishing stack (109) opposite the support substrate (101), at least a fourth layer (121, 123, 125) based on gallium nitride; and c) remove the support substrate (101) by electropolishing the first layer (117).Figure for the abridged version: Fig. 1.

Description

Title of the invention: Method for making an electronic device. Technical field.

[0001] This description relates generally to electronic devices, and in particular to power electronic devices and their manufacturing processes. Prior art

[0002] Power electronic devices, for example devices comprising at least one high-electron-mobility transistor (HEMT), and methods for manufacturing such devices have been proposed. HEMTs are generally made from a stack of gallium nitride (GaN) layers, because this material exhibits a high breakdown field, or critical field, and significant electron mobility. This makes it possible to produce transistors with small dimensions and high voltage ratings.

[0003] To reduce the manufacturing cost of HEMT transistors, the GaN-based layer stack is generally formed by epitaxial growth on a substrate made of another semiconductor material, for example, a silicon wafer with a diameter of at least 150 mm, or even at least 200 mm. Buffer layers are then interposed between the substrate and the GaN-based layer stack. The buffer layers not only allow for lattice parameter matching and thermal expansion coefficient matching between the substrate and the GaN-based layer stack, to obtain GaN-based layers of high crystalline quality, but also provide electrical isolation of the GaN-based layer stack from the substrate, to withstand a blocking voltage of the HEMT transistor during operation.The fact that buffer layers perform both mesh parameter adaptation and electrical insulation functions makes their optimization particularly difficult. Summary of the invention

[0004] There is a need to improve existing power electronic devices and their manufacturing processes. In particular, there is a need to decouple the mesh parameter and thermal expansion coefficient adaptation functions from the electrical insulation functions.

[0005] To this end, an embodiment provides a method for manufacturing an electronic device, the method comprising the following successive steps: a) forming, on a support substrate, an electropolishing stack comprising: - a first sacrificial semiconductor layer; - a second semiconductor charge-transporting layer; and - a third semiconductor layer to protect the second layer, the third layer being interposed between the first and second layers and having a doping level strictly lower than those of the first and second layers; b) forming, on the side of a face of the electropolishing stack opposite the support substrate, at least one fourth gallium nitride-based layer; and c) removing the support substrate by electropolishing the first layer by applying, between an electrode in contact with the second or third layer and a counter electrode disposed in an electrolytic solution, a biasing current passing, in that order, through the second, third, and first layers.

[0006] According to one embodiment, the process further comprises, subsequent to step c), a step d) of transferring said at least one fourth layer onto a transfer substrate.

[0007] According to one embodiment, said at least a fourth layer is part of an active stack of power electronic components.

[0008] According to one embodiment, the process further comprises, between steps b) and c), a step of forming, in and on the active stack, at least one HEMT transistor.

[0009] According to one embodiment, the first layer is located on and in contact with a face of the third layer opposite the supporting substrate.

[0010] According to one embodiment, the method further comprises, subsequent to the step of forming said at least one HEMT transistor and prior to step c), a step of forming one or more vias or one or more trenches extending from a face of the active stack opposite the support substrate, through the active stack and through the second and third layers, into the thickness of the first layer.

[0011] According to one embodiment, the second layer is located on and in contact with a face of the third layer opposite the supporting substrate.

[0012] According to one embodiment, the method further comprises, subsequent to the step of forming said at least one HEMT transistor and prior to step c), a step of forming one or more vias extending from a face of the support substrate opposite to the electropolishing stack, through the support substrate, into the thickness of the first layer.

[0013] According to one embodiment, said at least a fourth layer is a single gallium nitride layer.

[0014] According to one embodiment, the method further comprises, subsequent to step d), steps for forming an active stack of electronic components power and formation, in and on the active stack, of at least one HEMT transistor.

[0015] According to one embodiment, the first layer has a doping level at least ten times higher than that of the third layer.

[0016] According to one embodiment: - the first and second layers each have a doping level of approximately 1 x 10¹⁹ at.cm³; and - the third layer has a doping level of approximately 1.1016 at.cm 3.

[0017] According to one embodiment, the method further comprises, between steps b) and c), a step of fixing a handle to the side of a face of the electropolishing stack opposite the support substrate.

[0018] According to one embodiment, the electropolishing stack further comprises a fifth transition semiconductor layer interposed between the support substrate and the first layer.

[0019] According to one embodiment, the process further comprises, prior to step a), a step of forming, on the support substrate, a buffer stack comprising at least one adaptation layer of mesh parameter and coefficient of thermal expansion. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0021] [Fig.1] is a schematic and partial side and cross-sectional view of a structure obtained at the end of a step in a manufacturing process of an electronic device according to an embodiment;

[0022] [Fig.2A], [Fig.2B], [Fig.2C] and [Fig.2D] are schematic and partial side and section views of structures obtained at the end of successive steps of a process for making an electronic device according to an embodiment;

[0023] [Fig.3A] and [Fig.3B] are schematic and partial side and cross-sectional views of structures obtained at the end of successive steps of a process for making an electronic device according to an embodiment;

[0024] [Fig.4] is a nomogram representing pre-breakage, porosification and electropolishing zones of a gallium nitride layer as a function of a doping level and a bias voltage applied to said layer;

[0025] [Fig. 5A], [Fig. 5B], [Fig. 5C] and [Fig. 5D] are schematic and partial side and cross-sectional views of structures obtained at the end of successive steps in a process for manufacturing an electronic device according to an embodiment; and

[0026] Figures 6A, 6B, and 6C are schematic and partial side and cross-sectional views of structures obtained after successive steps in a process for manufacturing an electronic device according to an embodiment. Description of embodiments

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various applications of the power electronic devices in this description, including the various devices capable of incorporating such devices, have not been detailed, as the described embodiments are compatible with all or most common applications and devices implementing at least one power electronic device, possibly with adaptations that are within the grasp of a person skilled in the art upon reading this description.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0032] Unless otherwise specified, the terms "insulator" and "conductor" mean respectively electrically insulating and electrically conductive.

[0033] Unless otherwise specified, the expression "in contact with" means "in mechanical contact with".

[0034] Fig. 1 is a schematic and partial side and cross-sectional view of a structure 100 obtained at the end of a step in a manufacturing process of an electronic device according to an embodiment.

[0035] In the example shown, the structure 100 comprises a support substrate 101. The support substrate 101 is, for example, a wafer or a piece of wafer made of a semiconductor material, for example, silicon. Alternatively, the support substrate 101 may be made of sapphire, silicon carbide (SiC), gallium nitride (GaN), etc. The material of the support substrate 101 is, for example, chosen depending on whether or not there is a subsequent drilling or cutting step in this substrate. The support substrate 101 has, for example, a diameter greater than or equal to 150 mm, for example, approximately 150 mm or approximately 200 mm.

[0036] In the illustrated example, the structure 100 further comprises a stack 103 of buffer layers covering an upper face 101T of the support substrate 101. In the example shown, the stack 103 comprises a buffer layer 105 located on and in contact with the upper face 101T of the support substrate 101 and another buffer layer 107 located on and in contact with the upper face of the buffer layer 105.

[0037] By way of example, buffer layer 105 is made of aluminum nitride (AIN). Buffer layer 105 has, for example, a thickness on the order of several hundred nanometers, for example, approximately 250 nm. Buffer layer 105 can have a monolayer or multilayer structure.

[0038] By way of example, buffer layer 107 is made of aluminum gallium nitride (AlGaN). Buffer layer 107 has, for example, a thickness on the order of several hundred nanometers, for example, approximately 600 nm. Buffer layer 107 has, for example, a monolayer structure with a molar concentration gradient of aluminum, for example, a higher molar concentration of aluminum near its lower face than near its upper face. Alternatively, buffer layer 107 has a multilayer structure consisting of a set of layers whose aluminum concentration decreases the further the layer is from buffer layer 105.

[0039] Figure 1 illustrates an example in which the stack 103 comprises two buffer layers. However, this example is not limiting and the stack 103 may, as an alternative, comprise any number of buffer layers analogous to layers 105 and 107.

[0040] According to one embodiment, the structure 100 further comprises an electropolishing stack 109 located on the support substrate 101. In the example shown, the electropolishing stack 109 coats the stack 103 with buffer layers.

[0041] In the example illustrated in [Fig.1], the electropolishing stack 109 comprises: - a transition layer 111 located on and in contact with the upper face of the buffer layer 107; - a load-carrying layer 113 located on and in contact with the upper face of layer 111; - a protective layer 115 for layer 113 located on and in contact with the upper surface of layer 113; and - a sacrificial layer 117 located on and in contact with the upper face of layer 115.

[0042] Each layer 111, 113, 115, 117 is for example based on a semiconductor material, for example GaN.

[0043] Layer 111, for example, has a multilayer structure comprising a carbon-doped GaN (GaN:C) layer coating the buffer layer 107 and another unintentionally doped GaN (GaN UID, or GaN NID, or GaN Non-Intentionally Doped) layer coating the GaN:C layer. For example, the GaN:C layer has a doping level on the order of 10¹⁸ at.cm³. The GaN:C layer has, for example, a thickness of several hundred nanometers, for example, approximately 600 nm. For example, the GaN UID layer has a doping level on the order of 1 x 10¹⁶ at.cm³. The GaN UID layer, for example, has a thickness less than that of the GaN:C layer, for example equal to about 300 nm.As an alternative, layer 111 is, for example, a single layer, for example in GaN:C, having a thickness in the range of 100 to 600 nm, or in GaN UID, having a thickness in the range of 100 to 300 nm. The choice of the structure of layer 111 depends, for example, on the nature of the buffer layers of the stack 103 and the type of support substrate 101 chosen.

[0044] As an alternative, layer 111 is omitted.

[0045] Layer 113 is, for example, made of heavily doped N-type GaN (N-GaN). As an example, layer 113 has a doping level of approximately 1 x 10¹⁹ at.cm³. Layer 113 has, for example, a thickness of approximately 1 pm.

[0046] Layer 115 is, for example, made of UID GaN. As an example, layer 115 has a doping level similar to or substantially equal to that of the UID GaN region of layer 111. Layer 115 has, for example, a thickness in the range of 200 to 500 nm.

[0047] Layer 117 is, for example, made of heavily doped N-type GaN. By way of example, layer 117 has a doping level greater than or equal to that of layer 113. In particular, the doping level of layer 117 is much greater, for example, at least ten times greater, than that of layer 115. Layer 117 has, for example, a doping level of approximately 1 x 10¹⁹ at.cm³. Layer 117 has a thickness strictly less than that of layer 113, for example, on the order of a few tens or a few hundred nanometers. By way of example, the thickness of layer 117 is in the range of 20 to 500 nm.

[0048] In the example shown, the structure 100 further includes an active stack 119 of a power electronic component, for example an active stack of a GaN-based High-Electron-Mobility Transistor (HEMT), located on the electropolishing stack 109. In this example, the stack 109 is interposed between the buffer layer stack 103 and the stack 119.

[0049] In the example illustrated in [Fig. 1], the active stack 119 of power electronic components comprises: - a layer 121 in P-type doped GaN (P-GaN) located on and in contact with the upper face of the sacrificial layer 117; - a 123 layer in UID GaN located on and in contact with the upper face of the 121 layer; - a layer 125 made of AlGaN located on and in contact with the upper face of layer 123; and - a layer 127 in silicon nitride (SiN), in AIN or in GaN located on and in contact with the upper face of layer 125.

[0050] Layer 121 is, for example, doped with magnesium (Mg) and has, for example, a doping level in the range of 1.1017 to 5.1018 at.cm3. As an example, layer 121 has a thickness of approximately 100 nm.

[0051] Layer 123 is, for example, intended to form a channel region of the HEMT transistor. Layer 123 has, for example, a doping level similar to that of layer 111, for example less than or equal to 1.1016 at.cm3. As an example, layer 123 has a thickness of approximately 300 nm.

[0052] Layer 125, for example, has a molar concentration of aluminum in the range of 12 to 30%, or greater than 60%. As an example, layer 125 has a thickness in the range of 10 to 30 nm.

[0053] Layer 127 is, for example, a protective layer of layer 125. As an example, layer 127 has a thickness in a range of 2 to 10 nm.

[0054] In the structure 100, the stack 103 of buffer layers accommodates differences in lattice parameters and coefficients of thermal expansion between the support substrate 101 and the layers of the active stack 119. The buffer layers 105 and 107 of the stack 103 notably ensure the crystalline quality of the GaN-based layers of the active stack 119.

[0055] Fig. 2A, Fig. 2B, Fig. 2C and Fig. 2D are schematic and partial side and section views of structures obtained at the end of successive steps of a process for making an electronic device according to an embodiment.

[0056] [Fig.2A] illustrates more precisely a structure 200A obtained at the end of a step of realization of the structure 100 previously described in relation to [Fig.1]. In the structure 200A, the electropolishing stack 109 is devoid of the transition layer 111.

[0057] In the example shown, a passivation layer 201 covers the active stack 119 of power electronic component of the structure 100. In this example, the passivation layer 201 is more precisely located on and in contact with the top face of the layer 127. By way of example, the passivation layer 201 is made of SiN, SiO2 or Al2O3.

[0058] In the illustrated example, the structure 200A further comprises a T-shaped conductive region 203 having a horizontal portion extending laterally on and in contact with the upper face of the passivation layer 201 and a vertical portion extending vertically from the upper face of the layer 201 into the stack formed by the layers 201, 127 and 125 and penetrating into the thickness of the layer 123. The conductive region 203 is, for example, made of a metal or a metal alloy, for example a titanium nitride (TiN) and tungsten (W) alloy.

[0059] In the example shown, the sides and bottom of the conductive region 203 are coated with an insulating layer 205 allowing the conductive region 203 to be isolated from the layers 123, 125, 127 and 201. By way of example, the insulating layer is made of an oxide, for example silicon oxide or aluminium oxide, or of a nitride, for example aluminium nitride.

[0060] The conductive region 203 and the insulating layer 205 form, for example, a control region, or gate region, of a HEMT transistor formed in and on the active stack 119.

[0061] In the illustrated example, the structure 200A further comprises an insulating layer 207 covering the passivation layer 201 as well as the upper face and the sides of the horizontal part of the T formed by the conductive region 203. By way of example, the insulating layer 207 is made of tetraethyl orthosilicate (TEOS).

[0062] In the example shown, the structure 200A further comprises disjoint conducting regions 209S and 209D. Region 209S is located above conducting region 203, and region 209D is located at a distance from region 203. In the illustrated example, conducting region 209S extends laterally on and in contact with the upper face of insulating layer 207, directly above the horizontal portion of the T formed by the underlying conducting region 203. Conducting region 209S passes through each layer 207, 201, 127, 125, 123 and penetrates the thickness of layer 121. In the example shown, region 209D extends laterally on and in contact with the top face of layer 207 and passes through each layer 207, 201, 127, 125.

[0063] The conductive regions 209S and 209D are, for example, made of a metal or a metal alloy. By way of example, the conductive regions 209S and 209D are made of the same material as the conductive region 203.

[0064] When the HEMT transistor is in operation, the conductive regions 209S and 209D form, for example, the source and drain contacts of the HEMT transistor. Although not shown in [Fig. 2A], the HEMT transistor also includes, for example, a gate contact connected to the conductive region 203.

[0065] In the illustrated example, the structure 200A further comprises an insulating layer 211 covering the insulating layer 207. More precisely, the insulating layer 211 is located on and in contact with portions of the upper face of the insulating layer 207 that are not covered by the conductive regions 209S and 209D. In addition, the insulating layer 211 is located on and in contact with at least a portion of the upper faces and sides of the conductive regions 209S and 209D. By way of example, the insulating layer 211 is made of TEOS.

[0066] In the example shown, the structure 200A further comprises conductive regions 213S and 213D. Regions 213S and 213D are respectively connected to regions 209S and 209D. In the illustrated example, regions 213S and 213D are respectively located on and in contact with regions 209S and 209D and on and in contact with parts of the insulating layer 211.

[0067] The conductive regions 213S and 213D form, for example, the source and drain electrodes of the HEMT transistor, respectively. Although not shown in [Fig. 2A], the HEMT transistor also includes, for example, a gate electrode connected to the conductive region 203.

[0068] In the HEMT transistor, a two-dimensional (2DEG) electron gas forms in layer 123 near the interface between layers 123 and 125. The conducting regions 209S and 209D are in contact with the two-dimensional electron gas. In the example shown, the HEMT transistor is normally blocked because the two-dimensional electron gas is interrupted by the gate region comprising the conducting region 203 coated with the insulating layer 205. In this example, the two-dimensional electron gas is discontinuous and comprises two parts located on either side of the gate region of the HEMT transistor.

[0069] When a voltage Vgs less than a threshold voltage V* of the transistor, for example a voltage Vgs substantially zero, is applied between the gate electrode (not shown) and the source electrode 213S, the gate region embedded in layer 123 prevents electrons from flowing between the source electrode 213S and the drain electrode 213D. The transistor is then in a blocked state.

[0070] Conversely, when the voltage Vgs applied between the gate electrode and the source electrode 213S exceeds the transistor's threshold voltage V*, electrons can flow between the source electrode 213S and the drain electrode 213D. The transistor is then in a conducting state. In the conducting state, electrons flow from one part of the two-dimensional electron gas to the other, bypassing the gate region. More precisely, when the transistor is conducting and subjected to a bias voltage applied between its drain and source, the electrons then use a conduction path located within layer 123 along the interface between layer 123 and the insulating layer 205 to flow from one side of the gate to the other.

[0071] [Fig. 2B] illustrates a structure 200B obtained from structure 200A, following further steps of deposition of an insulating layer 221 and formation of one or more vias 223. In order not to clutter the drawing, only one via 223 has been shown in [Fig. 2B], it being understood that structure 200B can comprise any number of vias 223. As an alternative, the via 223 can be replaced by a trench corresponding to a cutting path of the HEMT transistor.

[0072] In the example shown, the insulating layer 221 covers the insulating layer 211 as well as the lateral faces of the conductive regions 213S and 213D. In the illustrated example, the insulating layer 221 is flush with the upper faces of the conductive regions 213S and 213D and fills all the gaps extending laterally between the regions 213S and 213D. By way of example, the insulating layer 221 is made of the same material as the insulating layer 211.

[0073] In the illustrated example, the via 223 extends vertically from the top face of the layer 221, through the layers 221, 211, 207, 201, 127, 125, 123, and 121, down to the thickness of the sacrificial layer 117. The via 223 has a ratio between its lateral dimension (for example, its diameter, in the case of a via with a circular cross-section) and its depth that is favorable for etching. By way of example, a cumulative thickness of approximately 10 to 20 pm of insulating material such as SiN or SiO2 is etched, followed by less than 1 pm of III-V semiconductor material, for example, AlGaN, GaN, or AIN. The walls of via 223 are coated with an insulating layer 225, with the exception of parts of the walls of via 223 located in layer 117. As an alternative, the parts of the walls of via 223 located in layer 117 are coated with the insulating layer 225.The bottom of via 223 is not coated with insulating layer 225 and is made up of part of layer 117. As an example, via 223 has a maximum lateral dimension of approximately 100 pm.

[0074] The via 223 is for example made by engraving at a location of a future cutting path of the device, opening from the upper face of the insulating layer 221 to the upper face of the sacrificial layer 117, depositing the insulating layer 225 on the sides and bottom of the opening, removal of the insulating layer 225 at the bottom of the opening and engraving opening into the sacrificial layer 117.

[0075] In the example shown, the structure 200B further comprises spacers 227 formed in the layer 207 on either side of the via 223. By way of example, the spacers 227 are made of a nitride or an oxide, for example, silicon nitride or silicon oxide. The spacers 227 are, for example, formed by PECVD (Plasma-Enhanced Chemical Vapor Deposition).

[0076] Figure 2C illustrates a structure 200C obtained from structure 200B following a subsequent step of attaching a handle 231 to the upper face of structure 200B. In the example shown, the handle 231 is bonded with a layer of adhesive 233. An opening 235 is also made in the handle 231 and in the adhesive layer 233 directly above the via 223. By way of example, the handle 231 is a wafer or a piece of wafer made of silicon, glass, etc. The handle 231 has, for example, lateral dimensions substantially identical to those of the support substrate 101.

[0077] Figure 2D illustrates a structure 200D obtained from structure 200C following a subsequent step of removing the support substrate 101 by electropolishing the sacrificial layer 117. For this purpose, structure 200C is, for example, immersed in a bath containing an electrolytic solution, and a potential is, for example, applied between an electrode in contact with layer 113 and a counter electrode immersed in the electrolytic solution. The electrode in contact with layer 113 is, for example, located on and in contact with a portion of the upper surface of layer 113 that is not coated with layer 115 (on the right side of structure 200C). Alternatively, the electrode is in contact with layer 115, the electrode then being, for example, located on and in contact with a portion of the upper surface of layer 115 that is not coated with layer 117.Furthermore, the counter electrode is, for example, located above structure 200C, for example opposite handle 231. The electrolytic solution in which structure 200C is immersed enters the opening 235 and the via 223. This allows the electrolytic solution to come into contact with layer 117.

[0078] When the potential is applied, a bias current flowing from the electrode in contact with layer 113 or 115 to the counter electrode passes, in that order, through layer 113, layer 115, and layer 117. The bias current causes the sacrificial layer 117 to be removed by electropolishing. This leads to the dissociation of the active stack 119 from the buffer stack 103 coating the support substrate 101.

[0079] During this step, the insulating layer 225 prevents the electrolytic solution from coming into contact with the layers of the active stack 119 and with the insulating layers 201, 207, 211 and 221.

[0080] Once the support substrate 101 is removed, the rear face is freed to allow, for example, the deposition of a layer of a dielectric material having, for example, a thickness in the range of 1 to 2 pm, followed by the deposition of a metallic layer. By way of example, the transfer substrate 241 has lateral dimensions substantially equal, within manufacturing variations, to those of the support substrate 101.

[0081] The handle 231 and the layer of glue 233 are then removed, for example.

[0082] An advantage of the process described above in relation to Figures 2A to 2D is that it allows decoupling on the one hand the lattice parameter adaptation functions and thermal expansion coefficient, ensured in this case by the layers 105 and 107 of the buffer stack 103, and on the other hand the electrical insulation function, ensured by the transfer substrate 241. This makes it possible to improve the crystalline quality of the layers of the active stack 119 and / or to increase the voltage withstand of the HEMT transistor in the blocked state.

[0083] Fig. 3A and Fig. 3B are schematic and partial side and cross-sectional views of structures obtained at the end of successive steps of a process for making an electronic device according to an embodiment.

[0084] Figure 3A illustrates more precisely a 300A structure comprising elements in common with the 200A structure previously described in relation to Figure 2A. These common elements will not be detailed again hereafter. The 300A structure differs from the 200A structure in that, instead of structure 100, the 300A structure comprises a 300 structure analogous to structure 100 but in which the order of layers 113, 115, and 117 has been reversed. In the 300 structure, layers 113, 115, and 117 are part of an electropolishing stack 309.

[0085] In the electropolishing stack 309: - the sacrificial layer 117 is located on and in contact with the upper face of the buffer layer 107; - the protective layer 115 is located on and in contact with the upper surface of layer 117; and - the load transport layer 113 is located on and in contact with the upper face of layer 115.

[0086] Although not shown in [Fig. 3A], the electropolishing stack 309 of the structure 300A may, alternatively, further include the transition layer 111. In this case, the layer 111 is interposed between the buffer layer 107 and the sacrificial layer 117.

[0087] In the example shown, the structure 300A comprises the insulating layer 221. Furthermore, the structure 300A comprises insulating layers 311 and 313 covering the insulating layer 221 and the upper faces of the conductive regions 213S and 213D. The insulating layers 311 and 313 are, for example, made of an oxide, such as silicon dioxide. In the illustrated example, the insulating layers 311 and 313 are interposed between the insulating layer 221 and the handle 231.

[0088] By way of example, the insulating layer 311 is deposited on the upper face of the structure. Furthermore, the insulating layer 313 is deposited on one face of the handle 231. The assembly comprising the handle 231 and the insulating layer 313 is then, for example, brought into contact with the insulating layer 311 by the face of the insulating layer 313 opposite the handle 231. During this step, the handle 231 is attached to the structure described above. By way of example, the attachment is achieved by direct bonding, for example by molecular bonding, between the two surfaces brought into contact.

[0089] Furthermore, during this step, one or more vias 323 are formed from the underside of the support substrate 101. In order not to clutter the drawing, only one via 323 has been shown in [Fig. 3A]. As an alternative, the via(s) 323 may be replaced by trenches.

[0090] In the illustrated example, the via 323 extends vertically from the underside of the support substrate 101, through the support substrate 101 and the layers 105 and 107 of the buffer stack 103, into the thickness of the sacrificial layer 117.

[0091] Via 323 is for example made by engraving opening into the thickness of the sacrificial layer 117.

[0092] [Fig.3B] illustrates a structure 300B obtained, from the structure 300A, as a result of a further step of removal of the support substrate 101 by electropolishing the sacrificial layer 117, for example in a manner analogous to that which has been described previously in relation to [Fig.2D].

[0093] Once the support substrate 101 has been removed, the structure is for example transferred to the transfer substrate 241. The handle 231 and the insulating layers 311 and 313 are then removed for example.

[0094] In the example shown, layers 113 and 115 have not been removed. However, this example is not limiting and removal of layers 113 and 115 may, as an alternative, be carried out before transferring them to the substrate 241. Layers 113 and 115 are, for example, removed by applying, between the electrode in contact with layer 113 and the counter electrode, a potential higher than that used to perform the electropolishing of the sacrificial layer 117.

[0095] The process described above with regard to Figures 3A and 3B has advantages similar to those of the process previously described with regard to Figures 2A to 2D. Another advantage of the process of Figures 3A and 3B is that the Fabrication of the via(s) 323 does not require alignment with the device's cutting paths. Furthermore, the vias 323 do not cross the active stack 119, thus reducing the risk of damage to this stack during device fabrication.

[0096] Fig. 4 is a nomogram 400 representing pre-breakage, porosification and electropolishing regions of a GaN layer, for example sacrificial layer 117, as a function of an Nd doping level (expressed in atoms per cubic centimeter, at.cm3, the values ​​indicated on the ordinate being to be multiplied by 1018) and a bias voltage E (in volts, V) applied to said layer.

[0097] In the example shown, the graph includes: - a 401 pre-breakdown region in which the crystalline structure of the layer begins to degrade; - a 403 region of porification, in which pores form within the layer without these pores significantly reducing the mechanical cohesion of the layer; - a 405 region of the electropolishing boundary, in which the beginning of a degradation of the mechanical cohesion of the layer is observed; and - an electropolishing region 407, in which the layer is removed, or eliminated, under the effect of the application of the bias voltage E.

[0098] In the case where the sacrificial layer 117 is made of GaN, a doping level of Nd greater than or equal to approximately 1.4 x 10¹⁹ at.cm³ and a voltage E applied to the layer 117 of approximately 15 V make it possible, for example, to implement the electropolishing steps of the sacrificial layer 117 described above in relation to Figures 2D and 3B. In this case, the protective layer 115 has, for example, a doping level less than or equal to approximately 4 x 10¹⁸ at.cm³, which allows the layer 115 to remain in the pre-break region 401.

[0099] The thickness of the sacrificial layer 117 is chosen to be as small as possible, so that the electropolishing, and therefore the removal, of this layer is as fast as possible, while being thick enough to allow the engraving of the vias 223 or 323, or of the trenches, so that these vias or trenches open into the layer 117.

[0100] The thickness of the protective layer 115 is chosen so that the layer 115 is thin enough to allow good charge transfer from the charge transport layer 113, and thick enough to remain intact during the electropolishing step of the sacrificial layer 117.

[0101] The thickness of the charge-transport layer 113 is chosen so that the layer 113 is sufficiently thin so as not to degrade the crystalline quality of the layers of the active stack 119, and sufficiently thick to remain intact during the electropolishing step of the sacrificial layer 117, to avoid edge effects in the case where the support substrate 101 has a diameter greater than or equal to 200 mm, and to allow good conduction of charges.

[0102] Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D are schematic and partial side and section views of structures obtained at the end of successive steps of a process for making an electronic device according to an embodiment.

[0103] Fig. 5A is a schematic and partial side and cross-sectional view of a 500A structure obtained at the end of a step in a manufacturing process of an electronic device according to an embodiment.

[0104] Structure 500A of [Fig. 5A] includes elements in common with structure 100 previously described in relation to [Fig. 1]. These common elements will not be detailed again hereafter. Structure 500A differs from structure 100 in that structure 500A includes, instead of the electropolishing stack 109, an electropolishing stack 509 located on the upper face 101T side of the support substrate 101. In the example shown, the electropolishing stack 509 covers the buffer stack 103.

[0105] In the example illustrated in [Fig.5A], the electropolishing stack 509 comprises: - the transition layer 111 located on and in contact with the upper face of the buffer layer 107; - the sacrificial layer 117 located on and in contact with the upper face of layer 111; - layer 115, which protects layer 113, located on and in contact with the upper surface of layer 117; and - the load transport layer 113 located on and in contact with the upper face of layer 115.

[0106] Furthermore, the structure 500A includes the active stack 119 located on the electropolishing stack 509. In this example, the stack 509 is interposed between the buffer layer stack 103 and the stack 119.

[0107] [Fig. 5B] illustrates a structure 500B obtained from structure 500A following a subsequent via formation step 323 in a manner analogous or identical to that previously described in relation to [Fig. 3A]. In the illustrated example, three vias 323 extend vertically from the underside of the support substrate 101, through the support substrate 101 and the layers 105 and 107 of the buffer stack 103, into the thickness of the sacrificial layer 117.

[0108] Figure 5C illustrates a structure 500C obtained from structure 500B following a subsequent step of removing the support substrate 101 by electropolishing the sacrificial layer 117, for example in a manner analogous to that which has been described previously in relation to [Fig.3B]. Previously, the handle 231 is for example fixed to the structure 500B on the side of the upper face of layer 127.

[0109] Once the sacrificial layer 117 has been electropolished, the layers 115 and 113 of the electropolishing stack 509 are, for example, removed by etching, for example by dry or wet etching. Alternatively, the layers 115 and 113 are removed by applying a higher potential, allowing the lightly doped layer 115 to be etched first, and then layer 113, for example according to the chart in [Fig. 4].

[0110] A bonding layer 501 is then deposited, for example, under the layer 121. In the example shown, the layer 501 is located under and in contact with a lower face of the layer 121, that is to say, a face of the layer 121 opposite the handle 231.

[0111] Layer 501 is formed, for example, by an atomic thin-film deposition process, for example by ALD (Atomic Layer Deposition). Layer 501 is, for example, insulating, for example in a case where the 500C structure is used for the subsequent realization of a so-called "horizontal" HEMT transistor. In this case, the layer is, for example, made of an insulating metal nitride, for example AlN.

[0112] As an alternative, layer 501 is conductive, for example in a case where a so-called "vertical" HEMT transistor is subsequently made from the 500C structure. In this alternative, layer 501 is for example made of a metal, for example tungsten or titanium, or of a conductive metal nitride, for example TiN.

[0113] By way of example, layer 501 has a thickness of less than 10 nm.

[0114] Figure 5D illustrates a 500D structure obtained from the 500C structure, the outcome of a subsequent step of transferring the 500C structure onto the transfer substrate 241 and removing the handle 231.

[0115] In the example shown, the transfer substrate 241 is pre-coated with a layer 503, for example a bonding layer of the same material as the layer 501, for example AlN.

[0116] By way of example, the fixation of the structure 500C on the transfer substrate 241 is obtained by direct bonding, for example by molecular bonding, between the two surfaces of the layers 501 and 503 brought into contact.

[0117] Although not illustrated, further manufacturing steps of a power electronic component, including for example at least one horizontal or vertical HEMT transistor, are implemented from the 500D structure. These steps include, for example, in the case of a horizontal HEMT transistor, the formation of a structure identical or analogous to that of the HEMT transistor previously described in relation to [Fig. 2A].

[0118] The process described above in relation to Figures 5A to 5D offers advantages similar to those of the processes previously described in relation to Figures 2A to 2D and Figures 3A and 3B. Another advantage of the process in Figures 5A to 5D lies in the fact that the electropolishing step of the sacrificial layer 117 is carried out prior to the fabrication of the power electronic component. This avoids, or reduces, the risk of damage to the component during the fabrication of the electronic device.

[0119] Fig. A, Fig. B and Fig. C are schematic and partial side and section views of structures obtained at the end of successive stages of a process for making an electronic device according to an embodiment.

[0120] The [Fig. 0A] is a schematic and partial side and cross-sectional view of a 600A structure obtained at the end of a step in a manufacturing process of an electronic device according to an embodiment.

[0121] Structure 600A of [Fig. 5A] includes elements in common with structure 500 previously described in relation to [Fig. 5A]. These common elements will not be detailed again hereafter. Structure 600A differs from structure 500A in that structure 600A includes, instead of the active stack 119, at least one GaN-based layer. In the example shown, structure 600A includes, instead of the active stack 119, a single GaN layer 601. In this example, layer 601 is located on and in contact with the upper face of the charge-carrying layer 113. Structure 600A is, for example, devoid of the active layer of a power electronic component.

[0122] [Fig. 3B] illustrates a structure 600B obtained from structure 600A following a subsequent step of removing the support substrate 101 by electropolishing the sacrificial layer 117, for example in a manner analogous to that described previously in relation to [Fig. 3B]. Prior to this, the via(s) 323 are, for example, formed from the lower face of the support substrate 101, and the handle 231 is, for example, fixed to structure 600A on the upper face of layer 601.

[0123] Once the electropolishing of the sacrificial layer 117 has been carried out, the layers 115 and 113 of the electropolishing stack 509 are for example removed by etching, for example a dry or wet etching.

[0124] The bonding layer 501 is then deposited, for example, under the layer 601. In the example shown, the layer 501 is located under and in contact with a lower face of the layer 601, that is to say a face of the layer 121 opposite the handle 231.

[0125] Fig. 6C illustrates a 600C structure obtained from the 600B structure after a subsequent step of transferring the 600B structure onto the transfer substrate 241 and removing the handle 231.

[0126] In the example shown, the transfer substrate 241 is pre-coated with the adhesive layer 503. As an example, the attachment of the structure 600B to the transfer substrate 241 is achieved by direct bonding, for example by molecular bonding, between the two surfaces of the layers 501 and 503 brought into contact.

[0127] Although not illustrated, further manufacturing steps of a power electronic component, comprising for example at least one horizontal or vertical HEMT transistor, are carried out from the 600C structure. These steps include, for example, in the case of a horizontal HEMT transistor, the formation of an active stack, for example identical or analogous to the active stack 119, and of a structure identical or analogous to that of the HEMT transistor previously described in relation to [Fig. 2A].

[0128] The process described above in relation to Figures 6A to 6C offers advantages similar to those of the processes previously described in relation to Figures 2A to 2D and Figures 3A and 3B. Another advantage of the process in Figures 6A to 6C is that it allows for the production of a GaN substrate—consisting, in the example shown, of layer 601—with a crystalline quality superior to that of existing substrates. Furthermore, performing the electropolishing step of the sacrificial layer 117 prior to the fabrication of the active stack of the power electronic component reduces the risk of damage to this stack during the fabrication of the electronic device.

[0129] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to them. In particular, those skilled in the art are able to transpose the described embodiments in relation to Figures 2A to 2D and to Figures 3A and 3B in the case where the transition layer 111 is present.

[0130] Moreover, although the case of the formation of a single HEMT transistor has been detailed above, the embodiments described apply more generally to the formation, in and on the active stack, of any number of GaN-based power electronic components, for example any number of HEMT transistors.

[0131] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, the described embodiments are not limited to the specific examples of materials and dimensions mentioned in this description.

Claims

Demands

1. Method for making an electronic device, the method comprising the following successive steps: a) forming, on a support substrate (101), an electropolishing stack (109; 309; 509) comprising: - a first sacrificial semiconductor layer (117); - a second charge-carrying semiconductor layer (113); and - a third semiconductor layer (115) for protecting the second layer (113), the third layer (115) being interposed between the first (117) and second (113) layers and having a doping level strictly lower than those of the first (117) and second (113) layers; b) form, on the side of a face of the electropolishing stack (109; 309; 509) opposite the support substrate (101), at least a fourth layer (121, 123, 125; 601) based on gallium nitride;and c) remove the support substrate (101) by electropolishing the first layer (117) by applying, between an electrode in contact with the second (113) or third (115) layer and a counter electrode disposed in an electrolytic solution, a biasing current passing, in that order, through the second (113), third (115) and first (117) layers.;

2. Method according to claim 1, further comprising, subsequent to step c), a step d) of transferring said at least a fourth layer (121, 123, 125; 601) onto a transfer substrate (241).

3. Method according to claim 1 or 2, wherein said at least a fourth layer (121, 123, 125) is part of an active stack (119) of power electronic component.

4. Method according to claim 3, further comprising, between steps b) and c), a step of forming, in and on the active stack (119), at least one HEMT transistor.

5. Method according to claim 4, wherein the first layer (117) is located on and in contact with a face of the third layer (115) opposite the support substrate (101).

6. A method according to claim 5, further comprising, subsequent to the step of forming said at least one HEMT transistor and prior to step c), a step of forming one or more vias (223) or one or more trenches extending from a face of the active stack (119) opposite the support substrate (101), through the active stack (119) and through the second (113) and third (115) layers, into the thickness of the first layer (117).

7. Method according to claim 4, wherein the second layer (113) is located on and in contact with a face of the third layer (115) opposite the support substrate (101).

8. A method according to claim 7, further comprising, subsequent to the step of forming said at least one HEMT transistor and prior to step c), a step of forming one or more vias (323) extending from a face of the support substrate (101) opposite the electropolishing stack (309; 509), through the support substrate (101), into the thickness of the first layer (117).

9. Method according to claim 1 or 2, wherein said at least a fourth layer (601) is a single gallium nitride layer.

10. A method according to claim 9, in its dependence on claim 2, further comprising, subsequent to step d), steps of forming an active stack (119) of power electronic component and of forming, in and on the active stack (119), at least one HEMT transistor.

11. A method according to any one of claims 1 to 10, wherein the first layer (117) has a doping level at least ten times higher than that of the third layer (115).

12. A method according to claim 11, wherein: - the first (117) and second (113) layers each have a doping level of approximately 1.1019 at.cm3; and - the third layer (115) has a doping level of approximately 1.1016 at.cm3.

13. A method according to any one of claims 1 to 12, further comprising, between steps b) and c), a step of fixing a handle (231) on the side of one face of the electropolishing stack (109) opposite the support substrate (101).

14. A method according to any one of claims 1 to 13, wherein the electropolishing stack (109) further comprises a fifth transition semiconductor layer (111) interposed between the support substrate (101) and the first layer (117).

15. A method according to any one of claims 1 to 14, further comprising, prior to step a), a step of forming, on the support substrate (101), a buffer stack (103) comprising at least one layer (105, 107) of mesh parameter and thermal expansion coefficient adaptation.

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