Atomic layer etching process of III-V materials

Abstract

Atomic Layer Etching Process for III-V Materials This description relates to an atomic layer etching process for a III-V material comprising the following steps: a) placing a structure comprising a layer of III-V material (100) in a chamber, b) carrying out, in the chamber at an etching temperature, one or more times the following atomic layer etching cycle: - oxidizing a surface of the III-V material layer (100) with an oxidizing gas, thereby forming an oxide layer (110), - purging the chamber under a flow of inert gas, - exposing the formed oxide layer (110) to thionyl chloride vapor to etch the oxide layer (110), - purging the chamber under a flow of inert gas. Figure for the abstract: Fig. 1

Description

Title of the invention: Method for atomic layer etching of III-V materials. Technical field

[0001] This description relates generally to the field of microelectronics, and more particularly to III-V material etching processes. The invention is particularly interesting for the manufacture of power devices or optoelectronic devices. Previous technique

[0002] IILV materials (GaN, InGaN, AlGaN, AIN, InN, GaAs, InGaAs, etc.) are used for the manufacture of optoelectronic devices (high brightness micro-LEDs) or power transistors (HEMT for 'high electron mobility transistors').

[0003] During the manufacturing process, these materials are etched to form cavities or patterns (contact holes in the case of transistors or pixel definition in the case of micro-LEDs). The etching must be fast and directional (anisotropic). It is primarily based on the use of plasmas containing BC13, Cl2, or a mixture of these two compounds to form volatile compounds of the metals to be etched (mainly GaCl3, InCl3, and AlCl3). However, the formation of these compounds requires high plasma energies, which makes the etching process quite invasive and leads to the formation of surface defects, or even amorphization of the IILV material surface after etching. This etching step is generally followed by removal of the lithography resin and then cleaning of the carbon residues by calcination (O2 plasma). This step can also alter the surface of the IILV material (formation of an oxide layer).

[0004] The presence of these surface defects is critical for the performance of the aforementioned devices. Indeed, in the case of a power transistor, the presence of defects related to plasma etching, surface oxidation or resin residues increases the contact resistance at the metal / IILV interface, thus degrading the electrical performance of the device, and in the case of micro-LEDs, the defects generate non-radiative charge recombinations at the edges of the cavities between the pixels, considerably reducing the quantum efficiency of the LED.

[0005] In order to eliminate these defects, post-etching cleaning can be carried out using a wet method (HCl or hydrofluoric acid buffer solution (BOE)). Wet cleaning results in a clean and deoxidized surface. However, such Cleaning must be quickly followed by the next step to avoid oxidizing the cleaned surface before depositing the contact metal or passivation layer.

[0006] Alternatively, post-etching cleaning can be carried out by a dry method, using an atomic layer etching (ALE) process. The advantage of this type of process is that it can be performed directly in vapor deposition equipment, thus allowing the post-etching cleaning and the deposition step to be carried out consecutively (without venting the device).

[0007] For example, US patent 8,124,505 B1 describes a process for atomic layer etching of GaN and other III-V materials in which the material is first surface oxidized by an O2 plasma, and then the oxide layer formed is selectively etched by a BC13 plasma. Note that both steps of the process require the use of a plasma, which is not ideal for obtaining a surface free of structural defects.

[0008] US patent 10,056,264 B2 describes an alternative atomic layer etching (ALE) process for GaN and other III-V materials based on the use of a BC13 / C12 mixture to chlorinate the material surface, followed by selective vaporization of the chlorinated layer by an inert gas plasma. This method has the disadvantage of terminating the sequence with a plasma that can generate structural defects in the III-V material.

[0009] The article by Chittock et al. (“Isotropy atomic layer etching of GaN using SF6 plasma and A1(CH3)3”, J. Appl. Phys. (2023) 134, 075302) presents a GaN ALE process based on alternating exposure to an SF6 plasma and trimethylaluminum (TMA) vapor. The GaN surface is first fluorinated by an SF6 plasma, and then the surface fluoride is vaporized in the presence of TMA via an exchange reaction that forms volatile fluoromethyl derivatives of aluminum and gallium (A1F(CH3)2 and GaF(CH3)2). This method can be considered gentler than those previously described since the TMA etching step is performed chemically (without plasma). Summary of the invention

[0010] There is a need for a process for etching a III-V material which remedies the disadvantages of the prior art, and, in particular, which allows isotropic etching of the III-V material without generating defects.

[0011] This goal is achieved by an ALE etching process of a III-V material comprising the following steps: a) place in an enclosure a structure comprising a substrate covered by a layer of material III-V, b) implement, within the enclosure, at an etching temperature, one or more times the following atomic layer etching cycle: - Oxidize a surface of the III-V material layer with an oxidizing gas, thereby forming an oxide layer, - Purge the chamber under a flow of inert gas. - expose the formed oxide layer to thionyl chloride vapor to etch the oxide layer, - purge the chamber under a flow of inert gas, c) preferably, deposit a layer of interest on the surface of the etched III-V material layer.

[0012] According to a particular embodiment, the oxidizing gas is dioxygen, ozone or nitrogen dioxide.

[0013] According to a particular embodiment, the etching temperature is between 20°C and 1000°C, preferably between 200°C and 600°C.

[0014] According to a particular embodiment, the III-V material is free of aluminum, the III-V material being for example GaN or InGaN, and the etching temperature is preferably between 200°C and 400°C, even more preferably between 300°C and 400°C.

[0015] According to a particular embodiment, the cycle includes an injection of water vapor simultaneously with the injection of oxidizing gas or after the injection of oxidizing gas.

[0016] According to a particular embodiment, the III-V material comprises aluminum, the III-V material being for example AlGaN or AIN, and the etching temperature is preferably between 300°C and 600°C, even more preferably between 400°C and 600°C.

[0017] This objective is also achieved by a method for manufacturing a power device, for example a transistor, preferably a HEMT-type transistor, comprising a substrate covered by a GaN layer and one or more additional layers of III-V material selected from AlGaN and AlN, through holes through the additional layer(s) and opening into the GaN layer, the through holes having been created by a reactive ion etching step, the method comprising the following steps: a) placing the device in an enclosure, b) carrying out, in the enclosure at an etching temperature, preferably between 200°C and 600°C, one or more times the following ALE step cycle to perform post-etching cleaning: - exposing the device to an oxidizing gas, thereby forming an oxide layer on a surface of the GaN layer exposed to the oxidizing gas; a surface of the additional layer(s) may also be oxidized, - purge the chamber under a flow of inert gas, - expose the device to thionyl chloride vapor to selectively etch the oxide layer of the GaN layer, - purge the chamber under a flow of inert gas, c) deposit in the through holes a layer of interest, in particular a metallic layer, for example TiN, or a dichalcogenide layer, for example VS2, the layer of interest being in contact with the etched surface of the GaN layer, step c) being carried out in the enclosure used during step b).

[0018] This objective is also achieved by a method for manufacturing an optoelectronic device, for example a micro-LED, comprising a substrate covered by a stack comprising an n-doped GaN layer, quantum wells for example in InGaN / GaN, a p-doped GaN layer, and a transparent conductive oxide layer, the stack having been etched, by reactive ion etching, so as to form pixels, the n-doped GaN layer being partially etched, the method comprising the following steps: a) placing the device in an enclosure, b) carrying out, in the enclosure at an etching temperature, preferably between 200°C and 600°C, one or more times the following ALE step cycle to perform post-etching cleaning: - exposing the device to an oxidizing gas, whereby a surface of the stack exposed to the oxidizing gas is oxidized and an oxide layer is formed, - purging the enclosure under a flow of inert gas, - expose the device to thionyl chloride vapor to etch the oxide layer, - purge the enclosure under a flow of inert gas, c) deposit between the pixels and on the side of the pixels, a dielectric layer, for example in SiO2, A12O3, SiN or AIN, step c) being carried out in the enclosure used during step b).

[0019] This goal is also achieved by a device comprising a substrate covered by a layer of III-V material, a layer of interest, for example a contact layer of metal, dichalcogenide, or a passivation layer, for example oxide or nitride, being in contact with the layer of III-V material, the surface of the layer of III-V material in contact with the layer of interest being deoxidized.

[0020] This goal is also achieved by a power device, for example a transistor, preferably a HEMT-type transistor, comprising a substrate covered by a GaN layer and at least one or more additional layers of III-V material chosen from AlGaN and AlN, with holes passing through the additional layer(s) and opening into the GaN layer, a layer of interest being formed in the through holes and in contact with the GaN layer, the layer of interest being a metallic layer, for example in TiN, or a conductive dichalcogenide layer, for example in VS2, the surface of the GaN layer in contact with the layer of interest being deoxidized.

[0021] This goal is also achieved by an optoelectronic device, for example a micro-LED, comprising a substrate covered by a stack comprising an n-doped GaN layer, quantum wells, a p-doped GaN layer, and a transparent conductive oxide layer, the stack being etched so as to form pixels, the n-doped GaN layer being partially etched, a dielectric layer covering the n-doped GaN layer between the pixels and the pixel flank, the dielectric layer being in contact with the n-doped GaN layer, the dielectric layer being, for example, made of SiO2, A12O3, SiN or AIN, the surface of the n-doped GaN layer in contact with the dielectric layer being deoxidized. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] Views A), B), C) and D) of [Fig.1] represent, schematically and in cross-section, several stages of a process for engraving a III-V material, according to a particular embodiment of the invention;

[0024] [Fig.2] is a graph representing the free enthalpies of the reaction between SOC12 and various oxides from the oxidation of III-V materials;

[0025] Views A) and B) of [Fig.3] represent, respectively, schematically and in cross-section, a HEMT type power transistor (the dotted lines represent the 2D electron gas) and a micro-LED according to different particular embodiments of the invention;

[0026] [Fig.4A] and [Fig.4B] are images obtained by atomic force microscopy of a layer of GaN, respectively, before and after an atomic layer etching process according to another particular embodiment (scale 5pmx5pm).

[0027] The different elements are not necessarily represented at a uniform scale to make the figures more legible. Description of the implementation methods

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the Different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean at 10%, preferably at 5%.

[0033] By between X and Y, we mean that the bounds X and Y are included.

[0034] The process which will be described in more detail later, with reference to The attached figures describe a purely thermal (i.e., plasma-free) atomic layer etching (ALE) process for III-V materials. It therefore enables isotropic etching of IILV materials without generating defects. It is particularly well-suited for removing the first few nanometers of surface that have been damaged by plasma during the etching of patterns in devices made from IILV materials.

[0035] The process comprises the following steps: a) place in an enclosure a structure comprising a substrate 10 covered by a layer of IILV material 100, the IILV material being able to be covered by a layer of native oxide 101 (view A) of [Fig.1]), b) to implement, within the enclosure, at an etching temperature, preferably between 20°C and 1200°C, even more preferably between 20°C and 1000°C and even more preferably between 200°C and 1000°C, one or more cycles of atomic layer etching (or ALE for "Atomic Layer Etching"), whereby the surface of the IILV 100 material layer is etched (views B) and C) beyond [Fig.1]), c) preferably, deposit a layer of interest 150 (for example a contact or passivation layer) on the engraved surface (view D) of [Fig.l]).

[0036] The ALE cycle (or ALE sequence) consists of repeating the following steps cyclically: 1) Exposure of the surface of the III-V 100 material to an oxidizing gas (view B) of [Fig. 1]), thereby forming an oxidized surface 110, 2) Purging of the reactor under a flow of inert gas, 3) Exposure of the oxide 110 of material III-V to thionyl chloride vapor (view C) of [Fig.1]), 4) Reactor purging under inert gas flow.

[0037] Repeating steps 1) to 4) constitutes one ALE cycle. The etching speed of the III-V material is expressed in nm / cycle or Å / cycle and corresponds to the average thickness of III-V material etched for each ALE cycle (averaged over several cycles). Steps 1) to 4) are repeated until the desired thickness is removed.

[0038] The process involves a first step of surface oxidation of the III-V material to form a thin oxide layer 110, followed by a second step in which the oxide layer is selectively etched (volatilized) using thionyl chloride (SOC12) vapor. Selective etching means that only the oxide layer is etched. During this step, the III-V material itself is not etched. Only the few nanometers of surface that have been damaged and / or oxidized are removed. The surface of the III-V material is thus cleaned and deoxidized.

[0039] The oxidation step 1) is limited by the diffusion of the oxidizing gas and remains very superficial at the temperature used for the process. During this step, the elements of group VA are oxidized and eliminated for the most volatile of them (in the form of NO, NO2, P4O6, P2O5,...), or etched during step 3) for the less volatile ones (As2O3, Sb2O3, Bi2O3).

[0040] The etching step 3) selectively etches the oxide formed during step 1) via the formation of volatile chlorides of group IIIA or VA elements (GaCl3, InCl3, AlCl3, AsCl3, SbCl3, BiCl3), and the removal of oxygen in the form of sulfur dioxide (SO2).

[0041] The chemical equation for the etching reaction is as follows: M2O3 + 3 SOCl2(g) 2 MCl3(g) + 3 SO2(g) (with M the metallic or pnictogen element).

[0042] Thionyl chloride does not etch (or only very weakly) IILV materials. It reacts selectively with oxides, which allows for etching layer by layer in which each step (oxidation and etching) is limited to the surface atoms of the material.

[0043] The oxidizing gas used in step 1) can be oxygen (O2), ozone (O3), nitrogen dioxide (NO2), or any other compound capable of releasing molecular or radical oxygen at the process temperature. The oxidizing gas can be introduced into the reactor pure or diluted in an inert gas.

[0044] It is possible to inject water in the form of vapor simultaneously with the injection of oxidizing gas or consecutively with the injection of oxidizing gas.

[0045] The exposure time of the III-V material to the oxidizing gas is adjusted according to the process temperature to ensure self-limiting oxidation (i.e., the oxide layer formed at the end of step 1 is sufficiently thick to act as a diffusion barrier to the oxidizing gas, thus stopping the oxidation process). This ensures an identical thickness of the oxide layer at every point on the surface of the material.

[0046] The thickness of the oxidized layer is typically less than 5 nm. In some cases, oxidation may be limited to only the atoms exposed on the surface of the sample (cases where the IILV material itself constitutes a diffusion barrier to the oxidizing gas).

[0047] The etching gas (SOC12 vapor) introduced in step 3) is generated by evaporation from a liquid SOC12 source. Mass transport is ensured either by the pressure differential between the reactor and the SOC12 source, or by an inert gas flow. Alternatively, thionyl chloride can be introduced into the reactor by direct injection. The exposure time of the material to be etched to the SOC12 vapor is adjusted to ideally allow complete etching of the oxide formed during oxidation step 1). This complete etching of the oxide layer ensures good process uniformity and allows obtaining a completely deoxidized IILV material surface at the end of the ALE etching process. It is facilitated by the ability of thionyl chloride to react selectively with oxides.

[0048] According to one embodiment, the ALE cycle includes subsequent steps in which steps 3) and 4) are repeated again.

[0049] Multiple exposures to SOC12 can ensure the complete elimination of the oxide formed during the oxidation step.

[0050] The oxidation step 1) and the etching step 3) are separated by purges to remove reaction by-products (volatile oxides during the oxidation step, and volatile chlorides during the etching step) and to prevent mixing between the two precursors. This purge consists of introducing a flow of inert gas or maintaining the reactor under dynamic vacuum for a sufficiently long time to allow the complete removal of precursors and gaseous reaction by-products introduced or generated during the previous step.

[0051] The purging steps are essential to prevent the mixing of the different precursors. If the precursors were to be mixed in the reactor, etching would occur continuously (etching the oxide as it is generated). If the oxidizing gas and thionyl chloride are introduced from By sequentially and not mixed, excellent uniformity and atomic-scale control of the etching are obtained.

[0052] The neutral gas used in step 2) may be the same as the neutral gas used in step 4). Preferably, the gases are identical. The gases may be chosen from nitrogen, or a noble gas such as helium or argon.

[0053] The neutral gas can be used as a carrier gas (or dilution gas) for the reactive species used in the oxidation (step 1)) or etching (step 3) steps).

[0054] We will now describe in more detail the different stages of the process.

[0055] Before step a), the deposition chamber can be passivated, for example, by a deposition of SiO2, alumina or mixed aluminium and silicon oxide (AlSiOx) in order to protect the metallic elements of the reactor from corrosion by SOC12.

[0056] The structure provided in step a) comprises a substrate 10 covered by a layer of IILV material 100 and optionally by one or more additional layers 200, 300, 400, 500, 600, 700. The additional layer(s) may be of an IILV material identical or different from the IILV material of layer 100.

[0057] IILV materials may contain aluminum or be aluminum-free. For example, IILV materials may be selected from GaN, InGaN, AlGaN, AlN, InN, GaAs, and InGaAs. IILV materials may be doped or undoped.

[0058] Patterns can be formed in the structure, for example to delimit pixels or to create holes allowing contact on the sides of the IILV material.

[0059] The structuring can, for example, result from a reactive ion etching (or RIE) step. The gases used for etching are, in particular, chlorinated gases.

[0060] The IILV 100 material layer can be covered by a native oxide 101 layer. This layer will disappear during the implementation of step b).

[0061] The substrate 10 is, for example, made of silicon or aluminum. The substrate can be passivated during step 1).

[0062] Step a) is a thermalization step of the material to the process temperature. The temperature to which the substrate is heated in step a) is preferably the same as the temperature in step b) and the same as the temperature in step c).

[0063] The substrate temperature during step b) depends on the material to be etched ([Fig. 2]). It is preferably above 20°C. It can be between 20°C and 1200°C, preferably between 200°C and 1000°C, and even more preferably between 200°C and 600°C. Preferably, it is between 200°C and 400°C, and even more preferably between 300°C and 400°C, for IILV materials not containing aluminum (e.g., GaN, InGaN). Preferably, it is above 300°C (e.g., between 300°C and 600°C), and even more preferably above at 400°C (for example between 400°C and 1000°C or between 400°C and 600°C) for those containing aluminium (for example AIN, AlGaN).

[0064] Thus, at a temperature below 400°C, for example at 350°C, it will be possible to selectively etch GaN or InGaN with respect to AlN or AlGaN. This is particularly advantageous in the case of a structure comprising a layer of an aluminum-free III-V material 100 and one or more additional layers 200, 300 of an aluminum-containing III-V material (view B) of [Fig. 3]). Implementing step b) at a temperature below 400°C leads to the selective etching of the aluminum-free III-V material 100. The additional layer(s) 200, 300 containing aluminum are not etched. As we will see later, this selective etching is particularly useful for manufacturing microelectronic devices.

[0065] Preferably, the temperature during etching (step b)) is identical to the deposition temperature (step c)) which will follow. For example, the temperature during steps b) and c) is between 300°C and 400°C, for aluminum-free IILV materials, which is ideal for following up with a CVD or ALD deposition process of most common metals or dielectrics (SiO2, SiN, Al2O3, AlN, HfO2, TiN, Ti(Al)C, etc...).

[0066] During step b), the working pressure is, for example, between 0.1Pa and 1000Pa, preferably between 0.1hPa and 50hPa.

[0067] During step c), a layer of interest 150 (conductive layer or dielectric layer) is deposited on the etched surface.

[0068] Steps b) and c) can be carried out in the same chamber, without re-exposing the material to air after deposition, in order to avoid the presence of oxide at the interface. For certain materials, this allows the formation of a so-called van der Waals interface (devoid of covalent bonds) and therefore prevents alteration of the surface state of the IILV material during the formation of the layer of interest 150.

[0069] The surface of the IILV materials thus engraved, and in contact with the layer of interest, is deoxidized (i.e. devoid of oxygen).

[0070] The layer of interest 150 can be a metallic electrode, for example, based on TiN, TiC, Ti(Al)C, VN, VC, NbN, TaN, MoN, WN, Ni, Co, Pt, or Ru. Such metals can be deposited by ALD and used as contacts on transistors based on IILV materials (mainly GaN / AlGaN). According to another embodiment, the layer of interest is a layer of conductive dichalcogenides such as VS2, VSe2, NbS2, NbSe2, TaS2, or TiS2. These metals or semimetals can be particularly useful as contacts in power transistors.

[0071] According to another embodiment, the layer of interest 150 is made of a dielectric material such as SiO2, Al2O3, HfO2, ZrO2, SiN, or AIN. Such dielectric materials can be deposited by ALD and used as electrical insulators on III / V material-based pixels, for micro-LED applications, for example.

[0072] To form the dielectric layer of SiO2 or Al2O3, it is also possible to first deposit a barrier layer of SiN or AIN (of thin thickness, typically between 1.5 and 2 nm) to protect the surface of the III-V material from oxidation. The subsequent deposition of SiO2 or Al2O3 will partially oxidize this barrier layer to form a passivation layer mainly composed of oxide, while preserving the surface of the III-V material.

[0073] Steps a), b) and c) can be directly implemented in most vacuum deposition reactors, which allows the surface preparation by ALE of the IILV material and the subsequent metal or dielectric deposition to be linked without re-airing in the manufacturing process of the device.

[0074] In particular, the ALE cycle is implemented in a vapor phase deposition reactor, ideally of the ALD ('atomic layer deposition') or CVD ('chemical vapor deposition') type, preferably modified to allow the sequential sending of precursors.

[0075] The isotropic and self-limiting character of ALE also allows the process to be implemented in 'batch' type reactors.

[0076] The etching process described above can be implemented to manufacture a device, for example a power device or an optoelectronic device, comprising a substrate 10 covered by a first layer 100 of a first IILV material and at least one or more additional layers 200, 300, 500, 600 of IILV material identical or different from the IILV material of the first layer 100.

[0077] The process may include the following steps: a) placing the device in an enclosure, b) performing the following ALE step cycle one or more times at an etching temperature: - exposing the device to an oxidizing gas, whereby oxide layers are formed on the surfaces of the IILV materials exposed to the oxidizing gas, - purging the chamber under a flow of inert gas, - expose the device to thionyl chloride (SOC12) vapor to etch at least the oxide layer 110 formed on the first IILV material of the first layer 100, - purge the chamber under a flow of inert gas, c) optionally, deposit a layer of interest at least 150 on the surface of the first etched material III-V.

[0078] The atomic layer etching process is particularly relevant for reducing the defect density at the III-V / metal or III-V / dielectric interfaces at the contact level (source and drain) in power transistors, particularly in GaN / AlGaN (view A) of [Fig.3]), or for optoelectronic devices, particularly for the passivation of pixel edges in GaN-based micro-LEDs (view B) of [Fig.3]).

[0079] By way of illustration and not limitation, the power device, in particular a power transistor for example of the HEMT ('High Electron Mobility Transistors') type, can be manufactured according to the following steps: - provide a structure comprising successively a substrate 10, a layer of GaN 100, a stack formed of a layer of AlGaN 200, a layer of AIN 300, a layer of SiN 400, a grid 20 being formed in the stack, - etch the stack and part of the GaN 100 layer to form, on either side of the grid 20, contact holes 30 for the source and drain regions, the etching step preferably being carried out by reactive ion etching, - perform post-etching cleaning by selectively etching the GaN 100 according to the ALE cycle of step b) described previously, - deposit a contact layer 150 in the through holes, the contact layer being in contact with the GaN layer 100 and preferably being made of metal or conductive dichalcogenide (view A) of [Fig.3]).

[0080] The post-etching and deposition steps are advantageously carried out in the same enclosure, without exposing the structure to air. The surface of the GaN 100 layer in contact with the layer of interest 150 is deoxidized.

[0081] By way of illustration and not limitation, the optoelectronic device, in particular a micro-LED, can be manufactured according to the following steps: - provide a structure comprising successively a substrate 10, an n-doped GaN layer 100, a stack formed of quantum wells (MQW) 500 in IILV material (for example InGaN / GaN wells), a p-GaN layer 600, a transparent conductive oxide layer 700 (for example indium tin oxide (ITO)), - etch the stack and part of the n100-doped GaN layer to define the pixel edges, the etching step preferably being carried out by reactive ion etching, - perform post-etching cleaning by implementing the ALE cycle from step b) described above, to etch the layers in IILV materials, - deposit an insulating layer of interest 150 on the sides of the pixels and on the n-doped GaN layer 100, the insulating layer of interest 150 being a dielectric such as alumina, or any other insulating oxide or nitride (view B) of [Fig.3]).

[0082] The cleaning and deposition step is advantageously carried out in the same enclosure, without re-exposing the structure to air. The surface of the n-doped GaN layer 100 in contact with the dielectric layer 150 is deoxidized.

[0083] The process is advantageously implemented for devices comprising an aluminum electrode. In particular, this applies to the lower electrode. Indeed, in the ALE etching sequence, the aluminum is not etched because the oxidant forms a barrier layer of Al2O3 and protects the electrode from the SOC12 etching. Since the etching is selective, the aluminum electrodes are preserved and integration is facilitated. There is no need to use hard masks to protect the electrode during the process.

[0084] With the process described above, the resulting device exhibits very good quality at the interface between the IILV material and the passivation layer or the contact metal. The IILV material is free of surface oxide. Furthermore, by removing the damaged surface layer, at least some of the structural defects formed during the RIE etching are eliminated, thus improving the performance of the final device.

[0085] Illustrative and non-limiting example

[0086] In this example, a layer of GaN is etched by thermal ALE.

[0087] A thin layer of GaN epitaxially grown on silicon 111 is introduced into a reactor The ALD is equipped with an ozone generator and a SOC12 source maintained at 20°C. The working pressure is approximately 1 hPa with a continuous nitrogen flow of 500 ml / min. The wafer is heated to a temperature of 350°C and exposed to 600 cycles of the following etching sequence: - O3 (19% in O2); 200 ml / min; 12 s - Nitrogen purge; 500 ml / min; 15 seconds - SOCl2(g); lOOOml / min; 0.2s - Nitrogen purge; 500 ml / min; 15 seconds

[0088] An ellipsometric measurement before and after etching indicates that 6.7 nm of GaN was etched, corresponding to an etching rate of 0.11 Å / cycle. The same sequence used without the oxidation step (600 cycles of SOC12 alone) does not lead to any measurable etching of GaN, which confirms the ALE regime of the process and the total selectivity of the Ga2O3 etching by SOC12 with respect to GaN at 350°C.

[0089] A characterization was also performed by AFM before and after the ALE process (Figures 4A and 4B). The images obtained by AFM confirm that the GaN layer after the ALE process is etched uniformly.

[0090] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0091] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. A method for etching a III-V material by ALE comprising the following steps: a) placing in an enclosure a structure comprising a substrate (10) covered by a layer of III-V material (100), b) carrying out, in the enclosure, at an etching temperature, one or more times the following atomic layer etching cycle: - oxidizing a surface of the layer of the III-V material (100) with an oxidizing gas, thereby forming an oxide layer (110), - purging the enclosure under a flow of inert gas, - exposing the formed oxide layer (110) to thionyl chloride vapor to etch the oxide layer (110), - purging the enclosure under a flow of inert gas, c) preferably, depositing a layer of interest (150) on the surface of the etched III-V material layer (100).

2. A process according to the preceding claim, wherein the oxidizing gas is dioxygen, ozone, or nitrogen dioxide.

3. A method according to any one of the preceding claims, wherein the etching temperature is between 20°C and 1000°C, preferably between 200°C and 600°C.

4. A method according to any one of claims 1 to 3, wherein the III-V material is free of aluminum, the III-V material being for example GaN or InGaN, and wherein the etching temperature is preferably between 200°C and 400°C, even more preferably between 300°C and 400°C.

5. A method according to the preceding claim, wherein the cycle includes an injection of steam simultaneously with or after the injection of oxidizing gas.

6. A method according to any one of claims 1 to 3, wherein the III-V material (100) comprises aluminum, the III-V material being for example AlGaN or PAIN, and wherein the etching temperature is preferably between 300°C and 600°C, even more preferably between 400°C and 600°C.

7. A method for manufacturing a power device, for example a transistor, preferably a HEMT-type transistor, comprising a substrate (10) covered by a GaN layer (100) and one or several additional layers (200, 300) of III-V material selected from AlGaN and AIN, through holes through the additional layer(s) (200, 300) and opening into the GaN layer (100), the through holes having been made by a reactive ion etching step, the process comprising the following steps: a) placing the device in an enclosure, b) carrying out, in the enclosure at an etching temperature, preferably between 200°C and 600°C, one or more times the following ALE step cycle to perform post-etching cleaning: - exposing the device to an oxidizing gas, whereby an oxide layer (110) is formed on a surface of the GaN layer (100) exposed to the oxidizing gas, a surface of the additional layer(s) (200, 300) may also be oxidized, - purging the enclosure under a flow of inert gas,- expose the device to thionyl chloride (SOC12) vapor to selectively etch the oxide layer (110) of the GaN layer (100), - purge the chamber under a flow of inert gas, c) deposit in the through holes a layer of interest (150), in particular a metallic layer, for example TiN, or a dichalcogenide layer, for example VS2, the layer of interest (150) being in contact with the etched surface of the GaN layer (100), step c) being carried out in the chamber used in step b).

8. A method for manufacturing an optoelectronic device, for example a micro-LED, comprising a substrate (10) covered by a stack comprising an n-doped GaN layer (100), quantum wells (500) for example in InGaN / GaN, a p-doped GaN layer (600), and a transparent conductive oxide layer (700), the stack having been etched, by reactive ion etching, to form pixels, the n-doped GaN layer (100) being partially etched, the method comprising the following steps: a) placing the device in an enclosure, b) carrying out, in the enclosure at an etching temperature, preferably between 200°C and 600°C, one or more times the following ALE step cycle to perform post-etching cleaning: - expose the device to an oxidizing gas, whereby a surface of the stack exposed to the oxidizing gas is oxidized and an oxide layer (110) is formed, - purge the enclosure under a flow of inert gas, - expose the device to a thionyl chloride (SOC12) vapor to etch the oxide layer (110), - purge the enclosure under a flow of inert gas, c) deposit between the pixels and on the side of the pixels, a dielectric layer, for example of SiO2, A12O3, SiN or AIN, step c) being carried out in the enclosure used during step b).

9. Device comprising a substrate (10) covered by a layer of III-V material (100), a layer of interest (150), for example a contact layer of metal, dichalcogenide, or a passivation layer, for example of oxide or nitride, being in contact with the layer of III-V material (100), the surface of the layer of III-V material (100) in contact with the layer of interest being deoxidized.

10. Power device, for example a transistor, preferably a HEMT transistor, comprising a substrate (10) covered by a GaN layer (100) and at least one or more additional layers (200, 300) of III-V material selected from AlGaN and AlN, through holes through the additional layer(s) (200, 300) and opening into the GaN layer (100), a layer of interest (150) being formed in the through holes and in contact with the GaN layer (100), the layer of interest being a metallic layer, for example TiN, or a conductive dichalcogenide layer, for example VS2, the surface of the GaN layer (100) in contact with the layer of interest (150) being deoxidized.

11. Optoelectronic device, for example a micro-LED, comprising a substrate (10) covered by a stack comprising an n-doped GaN layer (100), quantum wells (500), a p-doped GaN layer (600), and a transparent conductive oxide layer (700), the stack being etched to form pixels, the n-doped GaN layer (100) being partially etched, a dielectric layer (150) covering the n-doped GaN layer (100) between the pixels and the pixel flanks, the dielectric layer (150) being in contact with the n-doped GaN layer (100), the dielectric layer (150) being, for example, made of SiO2, Al2O3, SiN or AIN, the surface of the n(100) doped GaN layer in contact with the dielectric(150) layer being deoxidized.

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