IMPROVED METHOD FOR IMPLEMENTING CONSTRAINT BY FLUAGE OF THE BOX

Abstract

Fabrication of a device with constrained semiconductor regions (12a, 12b, 12c, 120b, 120c, 220a, 220d) comprising: a) coating a semiconductor layer (12) of a semiconductor-on-insulator substrate with a stress-relieving layer (30) of an amorphous material having intrinsic tensile stress, then b) forming in the stress-relieving layer (30) at least one opening (33; 2331, 2332) opposite a first semiconductor region (12a; 220a, 220d) of said semiconductor layer, and then c) performing a creep annealing at a time and temperature suitable for allowing the creep of the insulating layer (11) of the substrate and energizing the first semiconductor region. Figure for the abstract: 1D

Description

Title of the invention: IMPROVED METHOD FOR STRESSING THE BOX BY FLUAGE - TECHNICAL DOMAIN AND PRIOR ART

[0001] The present description relates to the field of microelectronics and semiconductor devices having one or more constrained semiconductor regions.

[0002] It is particularly aimed at the methods of making such devices and the methods for putting a semiconductor region under stress or relaxing it.

[0003] To improve the performance of certain microelectronic components, in particular transistors, it may be advantageous to plan to make them partly in a layer of semiconductor material in which a mechanical stress in tension or compression is applied.

[0004] By mechanical stress of a semiconductor layer we mean that its material has its crystalline lattice parameter(s) deformed.

[0005] In the case where the deformed lattice parameter is greater than the so-called "natural" parameter of a crystalline material in a given direction, the latter is said to be under tensile strain in that direction.

[0006] When the deformed lattice parameter is smaller than the natural lattice parameter, the material is said to be in compressive deformation or in compression.

[0007] To these states of mechanical deformation, states of mechanical stress are associated.

[0008] A semiconductor material subjected to a given stress state will have its band structure modified, which will lead to a change in the electrical properties of that material, in particular the mobility of the charge carriers within it. The same semiconductor material will be affected differently depending on its type of doping and its crystallographic orientation.

[0009] Thus, to improve the performance of transistors, it is possible to plan to make their channel region in a semiconductor material having a biaxial mechanical stress in tension or compression depending on whether it is a p-type doped semiconductor (the majority carriers being holes) or an n-type doped semiconductor (the majority carriers being electrons).

[0010] To apply stress to a region of semiconductor material, it is known to use a method commonly called "BOX creep" (i.e., "BOX creep") where a layer of thermal oxide commonly called "BOX" (for "Buried Oxide") is used in a semiconductor substrate. insulating conductor to allow stress to be applied to a semiconductor layer.

[0011] This involves taking advantage of the sharp decrease in the viscosity of the BOX at high temperature by carrying out a thermal annealing during which stress relaxation is possible due to the thinning of the BOX.

[0012] Document US2008169508A1 uses such a method with a particular BOX or FIN layer in BPSG ("BoroPhosphoSilicate Glass", i.e. borophosphosilicate glass), in a process where a semiconductor island is formed by structuring a semiconductor layer under tension and a semiconductor island under compression, on which a SiN-based stress layer having an intrinsic compressive stress and a SiN-based stress layer having an intrinsic tensile stress have respectively been formed, which are relaxed following a heat treatment for FINING allowing modification of the viscoelastic properties of the BPSG layer.

[0013] The process implemented here has the particular disadvantage of using a doped BOX layer and of requiring the implementation of two different nitride layers obtained by different processes to constrain the N and P zones of a given substrate differently.

[0014] US2020 / 0066909 A1 describes another process in which the BOX finishing method is used, this time on an undoped BOX layer, which requires the use of higher temperatures for the finishing heat treatments. However, in the case of high-temperature heat treatment, particularly above 600°C, it proves difficult to maintain the intrinsic stress of a compressive nitride stress-relieving layer.

[0015] The problem arises of finding a new process, preferably improved with respect to at least one of the disadvantages mentioned above, allowing the stress state of one or more semiconductor regions of different types (N or P) to be modified while limiting the number of steps required for this. Description of the invention

[0016] It is therefore an object of the present invention to propose a method for modifying the stress state of at least one semiconductor region of a semiconductor device, the method comprising, in this order, the following steps:

[0017] a) coating a "surface" semiconductor layer of a semiconductor-on-insulator substrate with a stress-bearing layer, the substrate comprising: a support layer, an insulating layer resting on the support layer and the surface semiconductor layer resting on the insulating layer, then,

[0018] b) form, in the stress layer, at least one opening through the stress layer and arranged opposite a first semiconducting region of the surface semiconducting layer while keeping at least a portion of the stress layer on and opposite at least a part of the substrate arranged against and in contact with the first semiconducting region, then,

[0019] c) carry out a so-called "finishing" annealing with a duration and temperature adapted to allow the finishing of the insulating layer of the substrate and release the portion of the stress layer so as to modify a stress state of the first semiconducting region.

[0020] With such a method one can put under stress, or increase the stress or possibly relax a semiconductor region.

[0021] Here, the stress state of at least one region of the surface layer is modified without having to perform a significant number of steps.

[0022] Typically, areas of insulation based on insulating material such as insulation trenches are provided.

[0023] Thus, advantageously, in step a), the substrate comprises insulation zones based on insulating material passing through the "surface" semiconductor layer, in particular insulation trenches arranged on either side of a so-called "active" semiconductor zone comprising the first semiconductor region.

[0024] The opening through the stress layer can be made so as to retain a second portion of the stress layer, the portion of the stress layer and the second portion then being arranged on either side of the opening.

[0025] The portion of the stress layer and the second portion of the stress layer can be arranged respectively opposite a second semiconductor region and a third region of the surface semiconductor layer arranged against and in contact with the first semiconductor region, the second semiconductor region and the third semiconductor region being arranged on either side of the first semiconductor region.

[0026] This allows for advantageous creation of regions constrained in tension and compression without necessarily having to deposit several different layers of stress and having to use different materials having different intrinsic stresses.

[0027] According to a particular embodiment, the stress-bearing layer in which the opening is formed in step b) has a tensile stress. In this case, the annealing of the substrate's insulating layer and the release of portions of the stress-bearing layer can lead to compression of the second semiconductor region and third semiconductor region and a voltage increase of the first semiconductor region.

[0028] According to one possible embodiment, the first semiconductor region belongs to a semiconductor area called the "active area" intended to accommodate at least one N-type transistor, and the opening can be made so as to retain a portion of the stress layer opposite another active area, the other active area being intended to accommodate one or more P-type transistors.

[0029] According to a particular embodiment, after formation of the opening and prior to the finishing annealing, the process may further include the deposition of a second stress layer on the stress layer as well as on the first semiconducting region.

[0030] According to one possible implementation, a second opening can be formed in the stress layer revealing another semiconducting region of said surface semiconducting layer, the opening and the second opening having different respective dimensions.

[0031] According to an embodiment in which, prior to the finishing annealing step, a part of the substrate is coated by a second stress layer different from said stress layer and / or of different thickness from the stress layer, the process may further include, prior to the finishing annealing step, making an opening in the second stress layer revealing another semiconducting region of the surface semiconducting layer.

[0032] According to a particular embodiment, the material of the stress layer can be tensile-stressed silicon nitride.

[0033] Here, a stress layer of material with an intrinsic tensile stress is used which, unlike the nitride stressed in compression, can be preserved at high temperature, and this layer is structured to allow a semiconducting region to be obtained subsequently under tension stress following fining.

[0034] Typically, the stress layer can be provided with a thickness between 20 nm and 100 nm.

[0035] According to one possible implementation, the finishing annealing in step b) is carried out at a temperature between 900°C and 1200°C, in particular for a duration of between 1 and 30 minutes.

[0036] According to a particular embodiment, the first semiconductor region is Si-based, and in which at least one other semiconductor region of the substrate coated by the stress layer is SixGei x (with 0 < x < 1).

[0037] Advantageously, this at least one other semiconductor zone is enriched in Germanium of the surface semiconductor layer, the semiconductor layer surface being made of silicon. In this case, the process may include, prior to step a), the following steps:

[0038] - formation of a germanium silicon block on the other semiconductor zone,

[0039] - thermal oxidation of the germanium silicon semiconductor block and of said superficial semiconductor layer so as to achieve an enrichment in germanium of the other semiconductor zone.

[0040] According to another aspect, the invention provides a method for making a transistorized device using a method as defined above and in particular comprising:

[0041] - the implementation of a process as defined above and then, after step c) of annealed finish

[0042] - the removal of the stress layer, the method further comprising, after stress layer removal: the formation of at least one transistor in the first semiconductor region and at least one other transistor in another semiconductor region of the surface layer of the substrate. Brief description of the drawings

[0043] The present invention will be better understood on the basis of the following description and the accompanying drawings in which:

[0044] [Fig.1A] [Fig.1B] [Fig.1C] [Fig.1D] serve to illustrate an example of an embodiment of a process according to the invention, of the creation of a structure comprising a stressed semiconductor region, here in tension, with on either side of semiconductor regions stressed differently, in this example in compression, this from a substrate of the semiconductor-on-insulator type by implementing a BOX creep step.

[0045] [Fig. 1E] [Fig. 1F] serve to illustrate the realization of N-type transistors and P-type transistors on such a structure.

[0046] [Fig.2A] [Fig.2B] serve to illustrate an alternative embodiment in which a silicon-based region is formed in tension and on either side of the regions constrained in compression in SixGeix.

[0047] [Fig.3] serves to illustrate a structure for implementing a condensation in Germanium in order to form SixGeix regions intended to be subjected to compression stress.

[0048] [Fig.4] serves to illustrate the implementation of several openings in a layer of applying stress and comparing the same active zone in order to form in this active zone several tension-constrained portions distributed opposite the openings.

[0049] [Fig.5] [Fig.6] [Fig.7] [Fig.8] [Fig.9] [Fig.10] serve to illustrate the influence of different parameters on the level and distribution of stress(s) in an active zone obtained by implementing a process according to the invention.

[0050] [Fig. 11 A] [Fig. 1 IB] [Fig. 1 IC] serve to illustrate an alternative embodiment;

[0051] [Fig. 12] serves to illustrate a variant of the process in which different parts of a substrate of stress layers made of different materials.

[0052] [Fig. 13] serves to illustrate a variant of the process in which stress layers of different respective thicknesses are provided on different parts of a substrate.

[0053] [Fig. 14] serves to illustrate a variant of the process in which openings of different respective dimensions are provided in a stress layer opposite different parts of a substrate.

[0054] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0055] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0056] In addition, in the description below, terms which depend on the orientation of a structure such as "front", "back", "upper", "lower", "on", "under", "above", "below", "above", "below", apply considering that the structure is oriented in the manner illustrated in the figures.

[0057] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0058] We now refer to [Fig.1A] which gives an example of a starting structure of a process for making a semiconductor device comprising one or more constrained semiconductor regions and here in particular at least one voltage-constrained semiconductor region.

[0059] The structure comprises a semiconductor-on-insulator substrate 5, for example of the SOI type (SOI for "Silicon on insulator"). The substrate 5 is thus provided with a support layer 10, typically semiconductor, which may be silicon-based, as well as an insulating layer 11, which is disposed on and in contact with the support layer 10, and a so-called "surface" semiconductor layer 12 located on and in contact with said insulating layer 11 and in which, typically, transistors are intended to be formed.

[0060] The superficial semiconductor layer 12 can have a thickness of, for example, between 5 and 20 nm, preferably between 5 and 10 nm.

[0061] The insulating layer 11 is typically based on silicon oxide, preferably undoped or unintentionally undoped. This insulating layer 11 can be provided with a thickness of, for example, between 10 and 30 nm, preferably between 15 and 25 nm.

[0062] Isolation zones allowing the delimitation of several active zones can also be made in and / or on the substrate 5.

[0063] In the particular embodiment shown in [Fig. 1A], these insulation zones are in the form of STI insulation trenches 21 (for "Shallow Trench Isolation"). To create such insulation trenches, trenches are cut through the "surface" semiconductor layer 12, the insulating layer 11, and the bottom of which is at the level of the support layer 10. Then, these trenches 21 are filled with an insulating material 23, for example, silicon oxide.

[0064] Alternatively, isolation zones of another type may be provided. For example, so-called "mesa" isolation zones involving the fabrication of insulating structures on the surface of the surface semiconductor layer 12 may be produced.

[0065] A semiconductor zone 120 located between the isolation trenches 21 can be provided to form an active zone in which one or more transistors are intended to be formed, in particular N-type transistors. Such a zone 120 can have a length LACT (dimension here measured from one STI zone to another and parallel to the x-axis of an orthogonal frame [Oo;x°;yo;z°] of, for example, between 100 nm and 10000 nm and typically corresponding to dimensions provided by drawing rules of a targeted technological node.

[0066] In the particular embodiment illustrated in [Fig. 1A], the substrate 5 is also coated with a thin insulating layer 25 which can be, for example, based on SiO2. The thin insulating layer 25 can be produced after deposition of the material 23 and then planarization by CMP (“Chemical Mechanical Planarization”, i.e. “Chemical Mechanical Polishing”), removal of a hard mask, for example, based on nitride, used to perform CMP polishing.

[0067] Such a thin insulating layer 25 can act as a buffer and serve to prevent possible degradation of the surface semiconductor layer 12 by preventing in particular the appearance of dislocations, in particular during subsequent annealing steps, especially at high temperature.

[0068] A stress layer 30 is then formed in a material 32 having a tensile stress ([Fig. 1B]). For example, such a layer can be formed by a CVD (Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced CVD) technique. The stress layer 30 can be deposited with an intrinsic stress, in particular a tensile stress.

[0069] Thus, the material 32 can be, for example, silicon nitride (SixNy) with an intrinsic tensile stress. This stress can, for example, be understood as between 0.5 GPa and 1.5 GPa for a 30 layer of planned stressing with a thickness that can be, for example, between 20 nm and 100 nm.

[0070] Next, an opening 33 is formed in the stress layer 30, traversing the stress layer 30. The opening 33 exposes a semiconducting region 120a of the surface semiconducting layer 12, which is located between the STI isolation trenches 21 and belongs to the active zone 120. The opening 33 is designed with a critical dimension Letch (the smallest dimension of the opening 33 in a plane parallel to the x-axis of an orthogonal coordinate system [00;x°;y0;z°]) which can be, for example, between 10 nm and the length LAcr of the first active zone. Advantageously, Letch is designed to be < Lact - 10 nm.

[0071] Preferably, the critical dimension LetCh is less than the length LACT of the active region. The size difference between the critical dimension LetCh and the length LACT can be at least one or several tens of nanometers. For example, when implementing an active region with a length LACT of approximately 500 nm, an aperture with a critical dimension LetCh of approximately 400 nm can be provided.

[0072] In this embodiment example, portions 30B, 30C of the stress layer 30 are preserved opposite regions 120b, 120c of the surface semiconducting zone 120 arranged on either side of the region 120a revealed by the opening 33.

[0073] Such an opening 33 can be formed by photolithography by making a masking based on photosensitive resin and then, by engraving by reproducing patterns made by the masking in the stress layer 30 here based on nitride and in the particular example described here, in the optional thin insulating layer 25.

[0074] Next ([Fig.1D]), a heat treatment, for example in an annealing furnace, is carried out at a high temperature and for a duration chosen so as to modify the viscoelastic behavior of the material of the insulating layer 11 and in particular to decrease its viscosity.

[0075] To induce the thinning of the insulating layer 11, the annealing treatment is preferably carried out at a "high temperature", i.e. at least equal to or greater than 900°C. Preferably, the temperature of this annealing is chosen to be below 1200°C in order to avoid the risk of damaging the substrate.

[0076] The degree of deformation due to the fining increases as the duration of the high-temperature annealing treatment increases and as the temperature at which the high-temperature annealing treatment is carried out increases.

[0077] The finishing of the insulating layer 11 results in a modification of the stress state of the semiconductor layer 12. Due to the finishing annealing, the portions 30B, 30C of the tension-stressing layer arranged on either side also tendency to relax, which promotes the stretching of the lattice of the material in the semiconductor region 120a. The semiconductor region 120a opposite which the stress layer 30 has been removed thus undergoes a tensile stress.

[0078] The annealing time can be adapted according to the geometry of the zone 120 and the underlying insulating layer 11, and the type of material composing this insulating layer 11. The duration of the finishing annealing can be predicted, for example, between 1 and 30 minutes.

[0079] Such fining also promotes the narrowing of the lattice of the material of the semiconducting regions 120b, 120c and consequently a compression of the semiconducting regions 120b, 120c located on either side of the semiconducting region 120a.

[0080] The level of stress in the surface semiconductor layer 12 and in particular of tension in the semiconductor region 120a depends on, and can be adjusted according to, the chosen thickness of the stress layer 30 and / or the intrinsic stress level of the material 32, itself being dependent on parameters of the material 32 deposition process which can be adjusted.

[0081] Once this creep annealing has been carried out, the stress layer 30 can then be removed.

[0082] Such removal can be carried out for example by dry or wet etching when the material 33 is silicon nitride based.

[0083] In the case where the thin insulating layer 25 covers the surface semiconductor layer 12, this thin insulating layer 25 is then also removed ([Fig. 1E]). Such removal can be carried out, for example, by etching using HF or a plasma using a fluorinated gas, particularly when this thin layer is an oxide.

[0084] Ti T2T3 transistors can then be formed on the structure obtained and having at least one semiconductor region constrained to 120a in voltage.

[0085] In particular, at least one N-type transistor Ti is provided, the channel of which extends into the energized semiconductor region 120a and one or more P-type transistors T2T3 in semiconductor regions 121, 122 located on either side of the semiconductor region 120 and put into compression following creep annealing due to the release of portions 30B, 30C located above these semiconductor regions 121, 122.

[0086] The fabrication of the transistors may include, in particular, steps of forming a gate dielectric 41 and a gate block 42 opposite each of the semiconductor regions 120, 121, 122 using deposition, photolithography, and etching steps, followed by the formation of insulating spacers on either side of the gate block ([Fig. 1F]). Doping of the source and drain regions may then be carried out. In the case where it is planned to fabricate so-called "raised" source and drain regions ", these regions are typically formed by epitaxial growth on the semiconductor layer 12. Doping of the source and drain regions can then be carried out at least partially during the epitaxial step.

[0087] According to an embodiment of a process as described above and instead of compressing semiconductor areas 121, 122 of a silicon layer, to improve the performance of P-type transistors, this compression can be carried out on regions of SixGeix (with 0 < x < 1).

[0088] Thus, in the embodiment example given in Figures 2A-2B, the stress layer 30, having an intrinsic tensile stress and typically made of silicon nitride, is formed first ([Fig.2A]) on a semiconductor layer comprising at least one semiconductor region 120 in silicon and, on either side of this region 120, semiconductor regions 221, 222 in SixGei_x.

[0089] Then, at least one opening 33 is formed in the stress layer 30 opposite the semiconductor region 120a and so as to preserve portions 30B, 30C of the stress layer 30 located opposite respectively the SixGebx semiconductor regions 221 and 222 located on either side of the silicon semiconductor region 120 ([Fig.2B]).

[0090] A finishing anneal is then carried out with a duration and temperature adapted to allow the finishing of the insulating layer 11 of BOX and to cause a tensioning of the semiconducting region 120a opposite the opening 33 while putting into compression the semiconducting regions 221, 222 in SixGei_x located opposite the portions 30B, 30C of the layer 30 of stressing.

[0091] One way of making the semiconducting areas 221, 222 in SixGei x is to carry out an enrichment in Germanium of the regions of a surface semiconductor layer 12 in silicon.

[0092] For this, we can start from a substrate 5 of the semiconductor-on-insulator type, possibly equipped with insulation zones, in particular STI trenches, and prior to the realization of the stress layer 30 we can form blocks 54b, 54c in silicon Germanium, respectively on semiconducting regions 121, 122 of the surface semiconducting layer 12 of the substrate 5 ([Fig.3]).

[0093] Such blocks can be produced, for example, by depositing or growing a silicon germanium layer on the surface semiconductor layer 12 and then forming patterns in this silicon germanium layer. Next, thermal oxidation of the silicon germanium semiconductor blocks 54b, 54c is carried out to allow the germanium atoms to migrate into portions of the surface layer and to achieve germanium enrichment of the surface semiconductor layer. Documents EP2075826B1 and FR2908924A1 from the applicant give examples of a germanium enrichment process, also called a germanium condensation process, to form SixGebx regions from silicon blocks.

[0094] A layer of oxide formed during the germanium condensation step can then be removed, for example by cleaning with HF.

[0095] As an alternative to what has just been described, it is also possible to plan to create the isolation zones such as STI trenches after the formation of the SixGei_ x regions by condensation or enrichment in Germanium.

[0096] P-type transistors can be provided in the germanium-enriched regions and under compression stress and one or more N-type transistors in the silicon-preserved region and which has been voltage-stressed using fining.

[0097] A particular embodiment given in [Fig. 4] provides for the several openings 4331, 4332 are created in the stress layer 30 opposite the same active zone. Thus, several openings 433b 4332 are formed in the stress layer 30 and between insulating zones, for example of the STI type (not shown in [Fig.4]).

[0098] In the embodiment illustrated in [Fig. 4], a first opening 433i is formed in the stress layer 30 opposite a semiconductor region 412a of said surface semiconductor layer 12, and a second opening 4332 is formed in the stress layer 30 opposite another semiconductor region 412b of said surface semiconductor layer 12. Portions 430B, 430C and 430C, 430D of the stress layer 30 are preserved on either side of these semiconductor regions 412a, 412b exposed by the openings 433b and 4332.

[0099] High-temperature annealing is then carried out for a duration and at a temperature adapted to allow the insulating layer 11 of the substrate to be finished and the portions 430B, 430C, 430D, of the stress-bearing layer 30 to be released. This puts into tension semiconducting regions 412a, 412b located opposite the openings 433i, 4332. Several stress-bearing regions are thus obtained in specific areas of an active zone.

[0100] Such an arrangement and distribution of constraints can be implemented for particular applications, for example when a transistor is made only with regard to the energized regions 412a, 412b.

[0101] As previously stated, the level and distribution of stresses in the regions of the semiconductor surface layer 12 can be adapted according to certain parameters of layer 30 of stress and of the opening(s) made in this layer.

[0102] Figure 5 shows various curves C5i, C52, C53 representing the evolution of a stress level in the surface semiconductor layer 12, obtained here by simulation using the Ansys Mechanical™ tool for a nitride-based stress layer 30 with a thickness of 50 nm, as a function of the position in this surface semiconductor layer 12, and for different critical dimensions LetCh of the aperture of 40 nm, 60 nm, and 80 nm, respectively. The stress level thus varies little as a function of the value of the critical dimension Letch of the aperture.

[0103] Fig. 6 gives various curves C6oi, C6o2, C6o3, C6o4, C6o5, C6o6, C6o7, C6o8, C6o9, C6io, C6n, C6i2, C6i3 representing the evolution of a stress level in an active zone of length Lact of 100 nm as a function of the position in this surface semiconductor layer 12, the stress being obtained using a nitride-based stress layer 30 in which the opening 33 has a critical dimension LetCh of 80 nm and for a finishing anneal carried out at 1050°C for 600 seconds. These curves are obtained for different thicknesses, respectively 20 nm (curves C60i, C602, C603), 30 nm (curves C604, C605, C6o6), 40 nm (curves C607, C6o8, C6o9) and 50 nm of the stress layer 30 and different intrinsic stress levels respectively of 0.5 GPa (curves C60i, C6o4, C6O7, C6o1), 1 GPa (curves C602, C605, C608, C6n), 1.5 GPa (curves C603, C606, C609, C6i2). This [Fig.6] shows the influence of the thickness of the stress-straining layer and the intrinsic stress level in this layer to allow adequate stress transfer in the semiconductor surface layer.

[0104] Figure 7 shows various curves C7i, C72, C73, C74, C75, C76, C77, and C78, ​​representing the evolution of a stress level in an active region of length Lact of 500 nm as a function of the position in this surface semiconductor layer 12. The stress is obtained using a nitride-based stress-inducing layer 30 with a thickness of 50 nm, an intrinsic stress level of 1.5 GPa, and for different critical dimensions Letch, respectively 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, and 400 nm. This figure demonstrates that it is preferable to show the impact of the choice of the critical dimension Letch on the resulting stress profile.

[0105] Figure 8 shows different curves C80i, C8o2, C803, C804, C8o5, C8o6, C807, C808, C8o9, representative of the evolution of a stress level in an active zone of The Lact length of 500 nm is determined as a function of the position in this surface semiconductor layer 12, the stress being obtained using a nitride-based stress-inducing layer 30 in which at least one opening is made, and for a finishing anneal carried out at 1050°C for 600 seconds. These curves are obtained for different thicknesses respectively of 25 nm (curves C80i, C802, C803), 50 nm (curves C804, C805, C8oe), 75 nm (curves C807, C808, C809) and different intrinsic stress levels respectively of 0.5 GPa (curves C8oi, C804, C807), 1 GPa (curves C802, C805, C808), 1.5 GPa (curves C803, C806, C809). Again, this figure shows the influence of the thickness of the stress layer and the level of intrinsic stress in that layer.

[0106] The C9b C92 curves of [Fig. 9] and the Ciooi, CiOo2 curves of [Fig. 10] are used to illustrate the impact of the finishing annealing temperature on the stress level in an active zone with a Lact length of 700 nm (curves C9i, C92) or in an active zone with a Lact length of 1000 nm (curves Ciooi, CiOo2), the stress being obtained using a 75 nm thick nitride-based stress-stressing layer and an intrinsic stress level of 1.5 GPa. These curves were obtained for annealing carried out for a duration of approximately 600 seconds and at temperatures of 1050°C (C9i Ciooi curve) and 1200°C (C92Cioo2 curve), respectively. Thus, an increase in the refining temperature leads to an increase in stress at the center of the semiconductor region under tension.

[0107] In either of the embodiments just described, a stress-bearing layer is provided, based on a material exhibiting tensile stress, in this case, in particular, SiN under tension. The process can also be applied to different stress-bearing layers, for example, based on a material exhibiting compressive stress, such as amorphous carbon or TiN. The stress-bearing layer can be based on an amorphous material or on a layer of semiconductor material, for example, SiGe, which is grown on the surface layer 12.

[0108] In the embodiment described above, a semiconductor region that is initially relaxed or unstressed is subjected to tension. The process can also be applied to increasing the stress in a region already under stress, or even to relaxing a region that is initially under stress. For example, a process such as the one described above can be applied to relaxing a silicon layer that is initially under compression, for example, by SiGe growth followed by a condensation process, or by using a specific substrate.

[0109] A variant of a method for modifying the stress state of a semiconductor region 1120 belonging to a superficial semiconductor layer 12 of a semiconductor-on-insulator substrate is illustrated in Figures 11A-1 IC.

[0110] A "full plate" deposit of a stress layer 30 ([Fig. 11 A]), that is, over the entire extent of substrate 5, is carried out. The stress layer 30 can, for example, be a SiN layer as described previously.

[0111] An opening 1133 ([Fig.1 IB]) is then formed in the layer 30 of the setting stress in relation to a semiconducting region 1112 of said surface semiconducting layer 12 while retaining a portion 1130A of the layer 30 of stress in relation to a part of the substrate which is disposed against and in contact with the semiconducting region 1112. This part of the substrate covered by the portion 1130A comprises a distinct semiconducting zone 1121 and in this particular example separated from the semiconducting region 1112 by means of an isolation trench 21.

[0112] A second stress-bearing layer 1150 is then deposited ([Fig. 1 IC]) on the stress-bearing layer 30 and on the semiconductor region 1112 exposed by the opening 1133. According to one particular embodiment, the second stress-bearing layer 1150 can also be made of silicon nitride (SixNy) with an intrinsic tensile strength, for example, between 0.5 GPa and 1.5 GPa, for a thickness that can be, for example, between 20 nm and 100 nm. Alternatively, the stress-bearing layers 30 and 1150 can be made of different thicknesses and / or materials.

[0113] A finishing anneal is then carried out with a duration and temperature adapted to allow the finishing of the insulating layer 11 of the substrate and to release both the portion 1130A of the stress layer 30 and the second stress layer 1150.

[0114] With such a variant, a semiconducting zone 1120 can be obtained, having an asymmetric or at least non-uniformly distributed stress between the insulation trenches 21, insofar as, during the finishing annealing, the semiconducting region 1112 is coated only with the second stress layer 1150, while another region 1113 is coated with a stack of stress layers 30, 1150.

[0115] With such a variant, active zones with different respective stresses can also be obtained. A semiconductor zone 1120, here facing only the second stress layer 1150, and another semiconductor zone 1121 facing a stack of portion 1130A and second layer 1150 have, after the finishing annealing, different stress states.

[0116] To implement semiconducting zones with different stresses in the surface layer 12 of the same substrate, an alternative embodiment provides for making the stress layer 30 on one part of the substrate and, on another part of the substrate, a second stress layer 1230 different from the stress layer 30 and in particular based on another material.

[0117] In the embodiment illustrated in [Fig. 12], an aperture 33 is formed in the stress-bearing layer 30, for example, of silicon nitride, opposite a semiconducting region 120a of the surface layer 12. In a second stress-bearing layer 1230, for example, of amorphous carbide or TiN, an aperture 1233 is formed opposite another semiconducting region 1200b of said surface semiconducting layer. Once these apertures 1233, 33 are formed, at least annealing is carried out to allow the insulating layer 11 to be thinned and the retained portions of the stress-bearing layers 30, 1230 to be released. This modifies the respective stresses in the semiconducting regions 120a, 1200b.

[0118] In another embodiment illustrated in [Fig. 13], a stress-bearing layer 30, for example made of silicon nitride, in which an aperture 33 is formed, is provided with a first thickness eb, for example, between 20 nm and 100 nm. Another stress-bearing layer 1330 with an aperture 1333 is provided with a second thickness e2, for example, between 20 nm and 100 nm, which is different from the first thickness eb.

[0119] The stress-bearing layers 30 and 1330 can be made of the same material, for example, SiN with a tensile stress. A finishing anneal is then performed on the insulating layer 11, which allows the remaining portions of layers 30 and 1330 to be released and modifies the state of the semiconductor region 120a opposite the opening 33 and of the other region 1300b opposite the other opening 1333.

[0120] In this way, different stress levels can be obtained respectively in a semiconductor region 120a opposite the aperture 33 and in another region 1300b opposite the other aperture 1333 made in the thinner stress layer. With such a variant, by adjusting the respective thicknesses e1, e2 according to the dimensions of the active zones, identical stresses can also be obtained in different active zones despite the different sizes of these active zones.

[0121] It is also possible, as an alternative to the examples just described in connection with Figures 12 and 13, to produce stress layers on different parts of the same substrate having both different thicknesses and different materials.

[0122] In another embodiment illustrated in [Fig.14], the stress layer 30 comprises an opening 33 having a first critical dimension DI and another opening 1433 having a second critical dimension D2 different from the first D1. By "critical dimension" we mean the smallest dimension of a motif, here of an opening, measured parallel to the plane [O; x; y] of the coordinate system [O; x; y; z] excluding its height (measured parallel to the z-axis).

[0123] Once these openings 1433, 33 have been made, annealing is carried out to allow the insulating layer 11 to be finished and the retained portions of the stress layer 30 to be released, in order to modify the stress in semiconducting regions 120a, 1400b located respectively opposite the opening 33 and the other opening 1433. In this way, different stresses can be obtained in this example in the semiconducting region 120a opposite the opening 33 and in the other region 1400b opposite the other opening 1433.

[0124] Here again, with such a variant, by adjusting the respective dimensions Dl, D2 according to those of the dimensions of the active zones, we can also obtain identical constraints in different active zones despite different respective sizes of these active zones.

Claims

Demands

1. A method for modifying the stress state of at least one semiconductor region (120a, 412a, 412b, 1112) of a semiconductor device, the method comprising, in this order, the following steps: a) coating a semiconductor layer (12) referred to as the "surface" layer of a semiconductor-on-insulator substrate with a stress layer (30), said substrate (5) comprising a support layer (10), an insulating layer (11) resting on the support layer (10) and said surface semiconductor layer (12) resting on said insulating layer (11), then b) forming in the stress layer (30) at least one opening (33;433b 4332,1133) traversing the stress layer (30) and arranged opposite a first semiconductor region (120a, 412a, 412b, 1112) of said surface semiconductor layer while retaining at least a portion (30B, 430B, 430D) of the stress layer (30) on and opposite at least a part of the substrate, said part being disposed against and in contact with the first semiconductor region (120a), then, c) perform a "finishing" annealing for a duration and at a temperature adapted to allow the finishing of the insulating layer (11) of the substrate and release said portion (30B, 430B, 430D) of the stress layer so as to modify a stress state of the first semiconductor region (120a; 412a, 412b).;

2. A method according to claim 1, wherein in step a), the substrate (5) comprises insulation zones based on insulating material (23) passing through the "surface" semiconductor layer (12), in particular insulation trenches (21), arranged on either side of a so-called "active" semiconductor zone (120) comprising the first semiconductor region (120a).

3. A method according to claim 1 or 2, wherein said part is a second semiconductor region (120b) of said surface semiconductor layer disposed against and in contact with the first semiconductor region (120a) and wherein said opening (33) is made so as to retain a second portion (30C) of the stress layer (30) facing at least a third region (120c) of the surface semiconductor layer (12) disposed against and in contact with the first semiconductor region (120a), said at least one portion (30B) of the stress layer (30) and said second portion (30C) being arranged on either side of said opening (33), the second semiconductor region (120b) and the third semiconductor region (120c) being arranged on either side of the first semiconductor region (120a).

4. A method according to claim 3, wherein the stress layer (30) in which the opening (33) is formed in step b) has a tensile stress and wherein in step c) of annealing, the thinning of the insulating layer (11) of the substrate and the release of portions (30B, 30C) of the stress layer (30) cause compression of the second semiconducting region (120b) and the third semiconducting region (120c), so as to put the first semiconducting region (120a) under tension.

5. A method according to claims 1 to 4, wherein the first semiconductor region (120a) belongs to a semiconductor area (120) called the "active area" intended to accommodate at least one N-type transistor (Ti), and wherein said opening (33) is made so as to keep a portion of the stress layer (30) opposite another active area, the other active area being intended to accommodate one or more P-type transistors (T2T3).

6. A method according to any one of claims 1 to 5, wherein, after formation of said opening (1133) and prior to said refining annealing, the method further comprises the deposition of a second stress layer (1150) on the stress layer (30) as well as on the first semiconducting region (1112).

7. A method according to any one of claims 1 to 6, wherein a second opening (1433) is formed in the stress layer (30) exposing another semiconducting region (1400b) of said surface semiconducting layer (12), said at least one opening (33) and said second opening (1433) having different respective dimensions (D1, D2).

8. A method according to any one of claims 1 to 7, wherein, prior to the finishing annealing step, a portion of the substrate is coated with a second stress-relieving layer (1330). different from said stress layer (30) and / or of different thickness from said stress layer (30), the process further comprising prior to the finishing annealing step, making at least one opening in the second stress layer (1330) revealing another semiconducting region (1300b) of said surface semiconducting layer.

9. A method according to any one of the preceding claims, wherein the material of the stress layer (30) is tensile-stressed silicon nitride.

10. A method according to any one of the preceding claims wherein the stress layer (30) has a thickness between 20 nm and 100 nm.

11. A method according to any one of claims 1 to 10, wherein the finishing anneal in step b) is carried out at a temperature between 900°C and 1200°C, in particular for a duration between 1 and 30 minutes.

12. A method according to any one of claims 1 to 11, wherein said first semiconductor region (12a) is Si-based, and wherein at least one other semiconductor region (221, 222) of the substrate coated by the stress-strain layer (30) is SixGei x (with 0 < x < 1).

13. A method according to claim 12, wherein said at least one other semiconductor zone (221, 222) is a Germanium-enriched zone of the surface semiconductor layer (12), the surface semiconductor layer (12) being silicon, the method comprising, prior to step a), the steps of: - forming a block (54b, 54c) of silicon Germanium on the other semiconductor zone, - thermal oxidation of the silicon Germanium semiconductor block (54b, 54c) and of said surface semiconductor layer so as to achieve germanium enrichment of the other semiconductor zone (12).

14. A method for manufacturing a transistor device, comprising: - carrying out a method according to any one of claims 1 to 13, then, after the finishing annealing step c), - removing the stress layer, the method further comprising, after removal of the stress layer: the formation of at least one transistor (Ti) in the first semi- conductive (12a) and at least one other transistor (T2) in another semiconducting region of the surface layer of the substrate.

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